Tools: Support ESP-IDF installed in system-wide shared directory for all users
Closes IDFGH-7790 and IDFGH-7791
See merge request espressif/esp-idf!19479
Test cases calling test_case_uses_tcpip() set critical lwip leak level to 4095, but do not reset it to default.
Hence, 4095 used to get added while calculating the critical threshold for the testcases following them.
This commit removes the riscv_interrupts.h header is it has become redundant. The previously
exposed API has been handled as follows:
- "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions
were declarations only and never had any implementation.
- "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to
"rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now
placed in rv_utils.h
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
dl.espressif.com is now using the same root certificate as github.com.
This commit replaces the previously-used ISRG X1 root certificate
with the DigiCert Root CA certificate.
As a result, even if the certificates are not installed (as it happens
on macOS with python.org installers, if the user forgets to run
'Install Certificates.command'), the download is successful.
Related to https://github.com/espressif/esp-idf/issues/4081
This commit fixes build issue because of function `bootloader_common_reset_rtc_retain_mem`
getting inlined with compiler optimization level set to `PERF` (-O2).
Build failure log:
-----------------
In function 'bootloader_common_reset_rtc_retain_mem',
inlined from 'bootloader_common_update_rtc_retain_mem' at /h/esp-idf/components/bootloader_support/src/bootloader_common_loader.c:183:13:
/h/esp-idf/components/bootloader_support/src/bootloader_common_loader.c:159:5: error: 'memset' writing 16 bytes into a region of size 0 overflows the destination [-Werror=stringop-overflow=]
159 | memset(rtc_retain_mem, 0, sizeof(rtc_retain_mem_t));
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2
then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal
Closes https://github.com/espressif/esp-idf/issues/8876
In previous gpio default isr, interrupt status bits get cleared at the exit of the isr.
However, for edge-triggered interrupt type, the interrupt status bit should be cleared before entering the per-pin handlers to avoid any potential interrupt lost.
Closes https://github.com/espressif/esp-idf/pull/6853
