alex/esp-idf
alex/esp-idf
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14 Commits

Author SHA1 Message Date
morris
c159984264 separate rom from esp32 component to esp_rom 
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
 2019-03-21 18:51:45 +08:00
chenjianqiang
bd8733f74f feature(psram): add psram support for esp32-pico chip 
1. esp32-pico use standard spi driver to access psram
2. for esp32-pico, flash and psram share the clock
3. for esp32-pico, psram cs io can be overwrite via menuconfig
 2019-01-09 10:49:07 +08:00
chenjianqiang
a0beff99d2 bugfix(psram): fix psram size acquisition method 
1. Use BIT[7:5] of EID to determine psram size
2. Add ID support for 16Mbit psram
3. Remove module reset on SPI1
4. Confirmed with the vendor that only the old 32Mbit psram need special clock timing. For other psram chips, we should use standard QPI mode.
 2018-11-28 17:05:37 +08:00
Michael (XIAO Xufeng)
20a666fe03 esp32: support to use hspi to output clock for 4MB PSRAM 
Resolves https://github.com/espressif/esp-idf/issues/2128.
 2018-10-29 20:22:44 +08:00
Michael (XIAO Xufeng)
9b5d0f3322 spi: shown owner of spi host explicitly 2018-10-29 20:22:44 +08:00
chenjianqiang
a10b7e892c bugfix(psram): fix psram driver 
1. remove use EID to distinguish psram voltage
2. 1V8 64Mbit psram and 3V3 64Mbit psram use the same psram driver(standard spi interface)
3. set cs hold time register as 1
 2018-10-08 19:55:13 +08:00
Wangjialin
6e9c59bfc3 feature(psram): add support for 64MBit psram of 1.8v and 3.3v. 
1. Add reading psram EID.
2. Configure different clock mode for different EID.
3. add API to get psram size and voltage.
4. Remove unnecessary VSPI claim.

For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level.
For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case.

EID for psram:
32MBit 1.8v: 0x20
64MBit 1.8v: 0x26
64MBit 3.3v: 0x46
 2018-07-10 14:24:59 +08:00
Angus Gratton
d775cc4c4c soc: Fix description of rtc_config_t.tieh, add macros 
Usage of TIEH was correct but description had 1.8V & 3.3V backwards.

Add macro definitions for TIEH values to improve readability.
 2018-05-25 14:58:37 +10:00
jack
c384fa2492 rename clock enable and reset bits for SPI modules 
1.The names of clock enable and reset bits do not match with TRM, just rename them.
 2018-05-14 16:45:03 +08:00
Wangjialin
b1dcb52fec feature(psram): configure flash and psram speed during runtime 
1. Bootloader reads SPI configuration from bin header, so that the burning configuration can be different with compiling configuration.
2. Psram mode init will overwrite original flash speed mode, so that users can change psram and flash speed after OTA.
3. Flash read mode(QIO/DIO…) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
4. Add read flash ID function, and save flash ID in g_rom_flashchip
5. Set drive ability for all related GPIOs
6. Check raise VDDSDIO voltage in 80Mhz mode
7. Add check flash ID and update settings in bootloader
8. Read flash ID once and keep in global variable
9. Read flash image header once and reuse the result

Tested cases:
1. Test new and old version of bootloader
boot Flash 20M —> app Flash 80M + Psram 80M
boot Flash 40M —> app Flash 80M + Psram 80M
boot Flash 80M —> app Flash 80M + Psram 80M
boot Flash 20M —> app Flash 80M + Psram 40M
boot Flash 40M —> app Flash 80M + Psram 40M
boot Flash 80M —> app Flash 80M + Psram 40M
boot Flash 20M —> app Flash 40M + Psram 40M
boot Flash 40M —> app Flash 40M + Psram 40M
boot Flash 80M —> app Flash 40M + Psram 40M
2. Working after esp_restart reboot.
 2018-04-20 20:51:44 +08:00
Jeroen Domburg
569bfad2e3 Fix the clock subsystem so it doesn't undo the weird condition spiram_psram.c jams the enable/reset bits of SPI3 in when 80MHz mode is selected anymore 2017-12-19 19:12:58 +08:00
Wangjialin
cea7dfbe90 psram: improve clock signal generation, increase drive strength 
Also check the chip type when initializing.
 2017-11-03 16:30:10 +08:00
Jeroen Domburg
6d95934a3c Make 80MHz PSRAM work as well, add testcase for weirdness reported on esp32 forums, clean up unused define in psram code 2017-09-14 10:47:44 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00