1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API
docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3
temperature_sensor: Fix issue that have conflict with phy / Fix phy pwdet and tsens power cannot be set twice issue (backport v4.3)
See merge request espressif/esp-idf!24968
1. Concurrency might cause ESP_ERR_TIMEOUT when calling uart_wait_tx_done
2. Concurrency might cause RTS line being de-assreted during tx transmission for rs485 mode
If CONFIG_SPIRAM_USE_MALLOC is enabled, and cache is disabled when GPIO ISR is triggered,
it would lead to Guru Meditation Error due to "Cache disabled but cached memory region accessed".
Closes https://github.com/espressif/esp-idf/issues/11876
This commit adds a workaround for the TWAI listen only mode errata which is
present on the ESP32, ESP32-S2, ESP32-S3, and ESP32-C3. twai_get_status_info()
has also been updated to account for the fact that TEC/REC are frozen in
listen only mode.
Errata Description:
When the TWAI controller is put into listen only mode, it should not influence
the TWAI bus in any way (i.e., should never send a dominant bit). However,
on the targets listed above, the TWAI controller will send dominant bits in an
error frame (i.e., active error frame), even if the controller is set to listen
only mode.
Workaround:
We can force the TWAI controller into the error passive state on startup (by
setting the REC to >= 128). Since the TEC/REC are frozen in listen only mode,
the TWAI controller will remain error passive and only send recessive bits
(i.e., passive error frames), thus will not influence the TWAI bus.
Closes https://github.com/espressif/esp-idf/issues/9157
Before this fix, when we call esp_pm_configure after gpio_wakeup_enable,
the configuration of GPIO in sleep state in gpio_wakeup_enable will be
overwritten by esp_pm_configure.
In previous transmission(s), the TX_DONE interrupt raw bit may be raised, but never been cleared.
TX_DONE interrrupt status bit should be cleared before enabling it to check the new transmission.
Since cpu retention dma use rc fast as clk source, so rc_fast_digi
will be enabled when we config to pd cpu. And cpu retention does not
need rc fast keep on during light sleep. So, if we use rc_fast_digi
to determine whether rc fast can be powered down, then cpu and and
rc fast cannot pd at the same time.
ledc_ls_timer_update is required only when CLK_DIV and DUTY_RES bits are changed.
Calling ledc_timer_rst while re-configure PWM frequency through ledc_set_freq can cause glitch in the signal
define: lock_bits = (lock->status & LOCK_MASK) >> LOCK_SHIFT; This `lock_bits` is the Bit 29-20 of the lock->status
1. spi_hdl_1:
acquire_end_core():
uint32_t status = lock_status_clear(lock, dev_handle->mask & LOCK_MASK);
Becuase this is the first `spi_hdl_1`, so after this , lock_bits == 0`b0. status == 0
2. spi_hdl_2:
acquire_core:
uint32_t status = lock_status_fetch_set(lock, dev_handle->mask & LOCK_MASK);
Then here status is 0`b0, but lock_bits == 0`b10. Because this is the `spi_hdl_2`
3. spi_hdl_2:
`acquire_core` return true, because status == 0. `spi_bus_lock_acquire_start(spi_hdl_2)` then won't block.
4. spi_hdl_2:
spi_device_polling_end(spi_hdl_2).
5. spi_hdl_1:
acquire_end_core:
status is 0, so it cleas the lock->acquiring_dev
6. spi_hdl_2:
spi_device_polling_end:
assert(handle == get_acquiring_dev(host)); Fail
Closes https://github.com/espressif/esp-idf/issues/8179
