system: support USB_OTG CDC console on ESP32-S3
Closes IDF-2048, IDF-2987, IDFGH-7134, IDFGH-7291, and IDFGH-7835
See merge request espressif/esp-idf!19312
For RAM loadable ELF, entire firmware is running from RAM and hence the
IROM/DROM size must be treated as 0 (no cache mappings created for
code/rodata).
Memprot functions are no longer placed by default in IRAM,
selecting ESP_PANIC_HANDLER_IRAM will still force panic related memprot
functions to be placed in IRAM.
esp_rom_spiflash_attach is called in cpu_start.c when it's
CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP.
This function will:
- reset MSPI
- configure MSPI IOs
- configure MSPI into slow read mode
Prior to this commit, this function is put quite late. It's OK for chips
earlier than C6. On C6 and H2, MMU registers are in SPI_MEM_x, so
resetting MSPI registers will also reset MMU registers.
After this commit, this funciton is called eariler, before
cpu_start.c: bootloader_init().
esp_execute_shared_stack_function always restored the stack watchpoint
regardless of CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK. This would lead
to an abondoned but active watchpoint on a former stack once the task
calling esp_execute_shared_stack_function is deleted, if
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is inactive.
This has been fixed now.
Closes https://github.com/espressif/esp-idf/issues/10414
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep
Closes IDFGH-6887
See merge request espressif/esp-idf!20973
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
During sleep, BBPLL clock always gets disabled
esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
When this option is selected, IDF will constantly monitor USB CDC port connection status.
As long as it gets connected to a HOST, automatic light-sleep will not happen.
Closes https://github.com/espressif/esp-idf/issues/8507
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API
docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3 and C2
This commit removes the riscv_interrupts.h header is it has become redundant. The previously
exposed API has been handled as follows:
- "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions
were declarations only and never had any implementation.
- "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to
"rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now
placed in rv_utils.h
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
For RISC-V and Xtensa targets, in case a panic needs to happen when
Task WDT is triggered (ESP_TASK_WDT_PANIC), the interruptee's stack
is now used for printing the backtrace.
Abort after Task Watchdog is triggered can happen on APP CPU (second core).
Functions used for burning this efuse would log, but at this point
esp_log is not initialized. Moved to a later point in the startup process.
Closes https://github.com/espressif/esp-idf/issues/9457
Blocking read from cdcacm VFS could return less bytes than requested.
This didn’t match the behaviour of other VFS drivers, and higher level
code could misbehave.
Previously, reset over USB CDC was done by calling esp_restart from
an interrupt handler. This works only until some restart hook function
is registered using esp_register_shutdown_handler, and the hook
function tries to do something that isn’t allowed in an interrupt
handler. One such case is with Wi-Fi. When Wi-Fi driver is installed,
it registers esp_wifi_stop as a shutdown handler function. However
esp_wifi_stop cannot be called from an ISR, and hence we shouldn’t
call esp_restart from an ISR either.
This commit modifies USB CDC driver to call esp_restart by posting it
to esp_timer task.
Closes https://github.com/espressif/esp-idf/issues/7404
Spinlocks themselves do not constitute critical sections as after a spinlock is acquired, interrupts
can remain enabled. However, there are some places where spinlocks are used direclty instead of using
the portMUX_TYPE and portENTER_CRITICAL_...() APIs. This commit fixes those calls.
- Remove esp_cpu_in_ocd_mode() from esp_cpu.h. Users should call esp_cpu_dbgr_is_attached() instead.
- Remove esp_cpu_get_ccount() from esp_cpu.h. Users should call esp_cpu_get_cycle_count() instead.
- Remove esp_cpu_set_ccount() from esp_cpu.h. Users should call esp_cpu_set_cycle_count() instead.
- Other IDF components updated to call esp_cpu_dbgr_is_attached(), esp_cpu_get_cycle_count() and esp_cpu_set_cycle_count() as well.
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
The following two functions in bootloader_support are private now:
* esp_secure_boot_verify_sbv2_signature_block()
* esp_secure_boot_verify_rsa_signature_block()
They have been moved into private header files
inside bootloader_private/
* Removed bootloader_reset_reason.h and
bootloader_common_get_reset_reason() completely.
Alternative in ROM component is available.
* made esp_efuse.h independent of target-specific rom header
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
SMP FreeRTOS uses a single kernel lock for all critical sections. There is a known
issue with esp_ipc_isr_stall_other_cpu() that can cause dead if the other CPU is
already in a critical section.
This commit adds a temporary workaround to reduce the chance of deadlock by taking
the SMP FreeRTOS kernel lock first before stalling the other CPU.
See IDF-5257 for more details.
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:
- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead
Also updated soc_hal.h as follows:
- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.
This commit also updates the XCHAL_ERRATUM_572 workaround by
- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
Was: Backtrace: N:M N:M N:M ...
Now: Backtrace:N:MN:M N:M ...
The problem with the new format is that it is hard to parse and
breaks the parser that is used by PlatformIO. The old format
is much more reasonable. I do not see how the pattern in IDFDUT.py
can work with the new format, due to the missing space after the :
The behavior of portSET_INTERRUPT_MASK_FROM_ISR() has changed in SMP FreeRTOS. It's
previous behavior is now implemented in portDISABLE_INTERRUPTS() and portRESTORE_INTERRUPTS().
This commit replaces all portSET_INTERRUPT_MASK_FROM_ISR() and portCLEAR_INTERRUPT_MASK_FROM_ISR()
calls with portDISABLE_INTERRUPTS() and portRESTORE_INTERRUPTS() respectively
Moved the following kconfig options out of the target component:
* CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
* ESP*_REV_MIN -> esp_hw_support
* ESP*_TIME_SYSCALL -> newlib
* ESP*_RTC_* -> esp_hw_support
Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
Modify the NGed drivers to adopt new clock ids
This commit updates the visibility of various header files and cleans up
some unnecessary inclusions. Also, this commit removes certain header
include paths which were maintained for backward compatibility.
If a windowoverflow8 happened after changing the SP, the exception handler would look for
the extra save area by looking at the previous frame's SP. This SP would be a garbage value
and could cause the windowoverflow exception to write to invalid memory ares.
Moved the following kconfig options out of the target component:
* ESP32_X_BROWNOUT_* -> esp_system
* ESP32_X_DEBUG_OCDAWARE -> esp_system
* APP_NO_BLOBS -> build type (main kconfig)
This commit removes the usage of all legacy FreeRTOS data types that
are exposed via configENABLE_BACKWARD_COMPATIBILITY. Legacy types can
still be used by enabling CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY.
Upstream xtensa exception handling will save PS, PC, and a0 registers
together when saving a minimal context. This commit ppdates the xtensa
exception handling to match upstream behavior.
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h
The following functions are deprecated:
- get_sp()
The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()
The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()
All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
peripheral enable/disable usually should be managed by driver itself,
so make it as espressif private APIs, not recommended for user to use it
in application code.
However, if user want to re-write the driver or ports to other platform,
this is still possible by including the header in this way:
"esp_private/peripheral_ctrl.h"
esp_restart()/panic_restart() never resets the Digital system (so far required only by the Memprot feature) as there's a typo in the corresponding #define:
it checks CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE instead of CONFIG_ESP_SYSTEM_MEMPROT_FEATURE.
Issue fixed.
IDF-4094
There was race condition where interrupt entries set by APP cpu core
could have been cleared during PRO cpu startup.
This was observed while setting up "cache access error" interrupt in
SMP mode for ESP32-S3.
This fix allows to NOT modify or clear any entries set by other core
(APP or PRO) and thus avoiding any race conditions during startup code.
As branches/jumps on Xtensa have a maximum range for the destination, it is
unsafe to refer to a label to another compilation unit in a branch/jump instruction.
The labels have been replaced by absolute addresses.
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt
components/os: high level interrupt(5)
components/os: hli_api: meta queue: fix out of bounds access, check for overflow
components/os: hli: don't spill registers, instead save them to a separate region
Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).
Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.
components/bt: using high level interrupt in lc
components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`
components/bt: optimize code structure
components/os: Modify the BT assert process to adapt to coredump and HLI
components/os: Disable exception mode after saving special registers
To store some registers first, avoid stuck due to live lock after disabling exception mode
components/os: using dport instead of AHB in BT to fix live lock
components/bt: Fix hli queue send error
components/bt: Fix CI fail
# Conflicts:
# components/bt/CMakeLists.txt
# components/bt/component.mk
# components/bt/controller/bt.c
# components/bt/controller/lib
# components/esp_common/src/int_wdt.c
# components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
# components/soc/esp32/include/soc/soc.h
