alex/esp-idf
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39,946 Commits 20 Branches 148 Tags 384 MiB
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156 Commits

Author SHA1 Message Date
Marius Vikhammer
5486653a18 Merge branch 'contrib/github_pr_14422' into 'master' 
feat(esp_system,ulp): LP core reserved mem optionally executable from HP core (GitHub PR)

Closes IDFGH-13533

See merge request espressif/esp-idf!33139
 2024-09-12 09:10:22 +08:00
wuzhenghui
13e42707a0
feat(esp_hw_support): add clk tree source gate management api 2024-09-11 10:53:01 +08:00
wuzhenghui
05e74480f5
feat(esp_system): gate some clock by default to optmize esp32p4 active power 2024-09-11 10:53:00 +08:00
andylinpersonal
0e30c42625 feat(esp_system,ulp): Make LP core reserved memory optionally executable in HP core 2024-09-10 12:17:38 +08:00
Li Shuai
1fa27cbb0d Merge branch 'feature/esp32c5mp_light_sleep_support_stage_2' into 'master' 
feat(esp_hw_support): esp32c5mp sleep support (system part)

Closes IDF-8643, PM-195, PM-169, IDF-8641, IDF-8640, IDF-8639, IDF-8638, CV-259, IDF-10308, IDF-10317, IDF-10310, PM-202, IDF-10918, PM-207, PM-208, PM-210, and PM-214

See merge request espressif/esp-idf!31645
 2024-08-29 19:32:05 +08:00
harshal.patil
95f286555a
fix(esp_hw_support): Use _iram_text_end instead of _iram_end for I/D-RAM split 2024-08-28 11:16:27 +05:30
Lou Tianhao
d6737c3207 refactor(esp_hw_support): refactor sleep clock, split it to support multiple targets 2024-08-28 10:44:08 +08:00
Lou Tianhao
5e5fb89c10 change(esp_hw_support): modify the root clock source of pmu modem state to pll for esp32c5 2024-08-28 10:44:08 +08:00
laokaiyao
1c2f8b8ce0 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-26 10:02:31 +08:00
harshal.patil
488b2a741d change(esp_security): Move the crypto locking layer into the security component 2024-08-20 12:35:22 +08:00
Song Ruo Jing
335d39b869 feat(clk): Add basic clock support for esp32c61 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-07-31 22:41:22 +08:00
Song Ruo Jing
3aa27ae960 refactor(regi2c): add LL function to control analog i2c master clock 2024-07-24 12:26:59 +08:00
Marius Vikhammer
41d39a419f fix(pmp): fixed alignment of PMP addr for RTC mem on C5 
Also refactored it for C6/H2/C61 to keep the approach consistent between targets
 2024-07-04 16:24:46 +08:00
wuzhenghui
2b70104761
fix(esp_hw_support): wait eFuse controller idle after sleep wakeup 2024-06-27 17:36:21 +08:00
Song Ruo Jing
40f3bc2e57 feat(clk): Add basic clock support for esp32c5 mp 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-06-26 14:26:34 +08:00
Wu Zheng Hui
2d36e81ccd Merge branch 'fix/remove_esp32c6_h2_solved_todos' into 'master' 
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos

Closes IDF-5781 and IDF-6254

See merge request espressif/esp-idf!31401
 2024-06-24 13:35:04 +08:00
Wu Zheng Hui
e254647b0a Merge branch 'feature/support_esp32p4_dcdc_always_on' into 'master' 
feat(esp_hw_support): support esp32p4 dcdc always on during lightsleep

Closes PM-104 and PM-131

See merge request espressif/esp-idf!30449
 2024-06-24 11:46:34 +08:00
Wu Zheng Hui
54c4984256 Merge branch 'fix/trigger_system_reset_in_brownout_isr' into 'master' 
change(esp_system): trigger digital system reset in brownout isr

See merge request espressif/esp-idf!30512
 2024-06-24 11:15:54 +08:00
wuzhenghui
1679b509be
feat(esp_hw_support): support DCDC always on 2024-06-21 16:55:49 +08:00
Xiao Xufeng
5b71b949be fix(startup): move rtc initialization before MSPI timing tuning to improve stability 2024-06-18 01:16:24 +08:00
Song Ruo Jing
ac6101bf4e feat(clk): support ESP32C5 XTAL 40M/48M selection 2024-06-11 17:42:43 +08:00
wuzhenghui
083ef29dcd
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos 2024-06-11 10:20:23 +08:00
wuzhenghui
cca222948a
fix(esp_driver_gpio): manage lp_io module clock by driver 
Closes https://github.com/espressif/esp-idf/issues/13683
 2024-06-05 17:56:37 +08:00
Li Shuai
b959a3e3c7 fix(wifi): fixed the issue of tg0 watchdog reset caused by wifi module retention 2024-05-22 20:21:57 +08:00
Hong Shu Qing
1a6060fa3a Merge branch 'feature/esp32c6_pu8m_in_sleep_support' into 'master' 
feat(sleep): support 8m force pu in sleep for esp32c6 & esp32h2

See merge request espressif/esp-idf!30532
 2024-05-17 11:34:47 +08:00
chaijie@espressif.com
36bbb64992 feat(sleep): support 8m force pu in sleep for esp32c6/esp32h2 2024-05-16 21:15:05 +08:00
Linda
52cfd1bf24 docs: fix clock sources for esp32c6 2024-05-07 17:35:39 +08:00
wuzhenghui
5d783cb613
change(esp_hw_support): update xtal_freq after assume to avoid mass print in DFS 2024-04-29 11:59:16 +08:00
Jiang Jiang Jian
9081d54aa7 Merge branch 'fix/fix_pmu_power_domain_initialize_order' into 'master' 
fix(esp_hw_support): fix pmu power domain initialize order

See merge request espressif/esp-idf!30095
 2024-04-10 17:23:47 +08:00
morris
e8b6d2280d change(gptimer): use private unsafe RCC LL functions in bootloader 2024-04-08 17:48:20 +08:00
wuzhenghui
24244f04f2
fix(esp_hw_support): fix pmu power domain initialize order 2024-04-08 15:47:59 +08:00
Laukik Hase
48503dd39f
fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-02 18:41:07 +05:30
Li Shuai
262be04b21 change(esp_hw_support): modify system and modem clock to support modem domain power down 2024-03-29 16:13:52 +08:00
wuzhenghui
194c38479e
refactor(esp_hw_support): split pd_top clock retention initialization by target 2024-03-28 19:18:24 +08:00
wuzhenghui
acd263d006
fix(esp_hw_support): fix pmu analog parameter configuration missing 2024-03-28 19:18:20 +08:00
Omar Chebib
a79c6f7f67 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-03-27 16:21:25 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Jiang Jiang Jian
6a879bf2d2 Merge branch 'bugfix/fix_maximum_value_of_config_rtc_clk_cal_cycles_bug' into 'master' 
ESP All Chip: fixed the maximum value of config RTC_CLK_CAL_SYCLES bug

See merge request espressif/esp-idf!29423
 2024-03-14 10:44:17 +08:00
Wu Zheng Hui
bb25cc1234 Merge branch 'feature/esp32p4_sleep_support' into 'master' 
feat(esp_hw_support): esp32p4 sleep support (Stage 1: support basic pmu sleep function 💤)

Closes IDF-7528 and IDF-7527

See merge request espressif/esp-idf!28196
 2024-03-14 10:17:32 +08:00
Mahavir Jain
2b17acb4b0 Merge branch 'bugfix/memprot_cleanup' into 'master' 
fix: cleanup memprot files for C6/H2/P4

See merge request espressif/esp-idf!29556
 2024-03-13 11:12:52 +08:00
Konstantin Kondrashov
3f89072af1 feat(all): Use PRIx macro in all logs 2024-03-12 11:15:53 +02:00
Mahavir Jain
fd6c710b27
fix: cleanup memprot files for C6/H2/P4 
There is no separate permission control peripheral in C6/H2/P4.
Memory protection is achieved using built-in PMA/PMP and hence
removing permission control specific files.
 2024-03-11 17:10:40 +05:30
wuzhenghui
129bfce02e feat(esp_hw_support): support esp32p4 pll start/stop event callback 2024-03-10 10:51:28 +08:00
wuzhenghui
856f043331 feat(esp_hw_support): add esp32p4 pmu initial support 2024-03-10 10:51:28 +08:00
wuzhenghui
f5707c6ab8
feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
Omar Chebib
eeb5e2f080 Merge branch 'refactor/cpu_interrupt_table' into 'master' 
refactor(Core System/Interrupts): changed reserved interrupt functions to be now defined per SoC

Closes IDF-5728

See merge request espressif/esp-idf!29020
 2024-03-06 11:26:17 +08:00
hongshuqing
d78805670a fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-05 19:33:30 +08:00
Omar Chebib
c1849df791 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-02-28 15:21:10 +08:00
Laukik Hase
366e4ee944
refactor(esp_hw_support): Remove redundant PMP entry for ROM region 
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
 2024-02-28 10:54:38 +05:30
Laukik Hase
ff839be31d
fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-02-28 10:54:37 +05:30