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Fix panic config ifdefs, un-stall app cpu on boot so it restarts after panic

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This commit is contained in:
Jeroen Domburg 2016-10-27 11:17:24 +08:00
parent fd887dbeea
commit ff6b8addd9
2 changed files with 10 additions and 4 deletions
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4
components/esp32/cpu_start.c
View File

@ -102,6 +102,10 @@ void IRAM_ATTR call_start_cpu0()
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1); ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
//Un-stall the app cpu; the panic handler may have stalled it.
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
//Enable clock gating and reset the app cpu.
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);

10
components/esp32/panic.c
View File

@ -38,7 +38,7 @@ task switching / interrupt code runs into an unrecoverable error. The default ta
overflow handler also is in here. overflow handler also is in here.
*/ */
#if !CONFIG_FREERTOS_PANIC_SILENT_REBOOT #if !CONFIG_ESP32_PANIC_SILENT_REBOOT
//printf may be broken, so we fix our own printing fns... //printf may be broken, so we fix our own printing fns...
inline static void panicPutchar(char c) { inline static void panicPutchar(char c) {
while (((READ_PERI_REG(UART_STATUS_REG(0))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT)>=126) ; while (((READ_PERI_REG(UART_STATUS_REG(0))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT)>=126) ;
@ -123,7 +123,7 @@ static void haltOtherCore() {
//Returns true when a debugger is attached using JTAG. //Returns true when a debugger is attached using JTAG.
static int inOCDMode() { static int inOCDMode() {
#if CONFIG_FREERTOS_DEBUG_OCDAWARE #if CONFIG_ESP32_DEBUG_OCDAWARE
int dcr; int dcr;
int reg=0x10200C; //DSRSET register int reg=0x10200C; //DSRSET register
asm("rer %0,%1":"=r"(dcr):"r"(reg)); asm("rer %0,%1":"=r"(dcr):"r"(reg));
@ -218,6 +218,7 @@ static void reconfigureAllWdts() {
TIMERG1.wdt_wprotect=0; TIMERG1.wdt_wprotect=0;
} }
#if CONFIG_ESP32_PANIC_GDBSTUB || CONFIG_ESP32_PANIC_PRINT_HALT
/* /*
This disables all the watchdogs for when we call the gdbstub. This disables all the watchdogs for when we call the gdbstub.
*/ */
@ -230,6 +231,7 @@ static void disableAllWdts() {
TIMERG0.wdt_wprotect=0; TIMERG0.wdt_wprotect=0;
} }
#endif
/* /*
We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the
@ -259,11 +261,11 @@ void commonErrorHandler(XtExcFrame *frame) {
} }
panicPutStr("\r\n"); panicPutStr("\r\n");
} }
#if CONFIG_FREERTOS_PANIC_GDBSTUB #if CONFIG_ESP32_PANIC_GDBSTUB
disableAllWdts(); disableAllWdts();
panicPutStr("Entering gdb stub now.\r\n"); panicPutStr("Entering gdb stub now.\r\n");
esp_gdbstub_panic_handler(frame); esp_gdbstub_panic_handler(frame);
#elif CONFIG_FREERTOS_PANIC_PRINT_REBOOT || CONFIG_FREERTOS_PANIC_SILENT_REBOOT #elif CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT
panicPutStr("Rebooting...\r\n"); panicPutStr("Rebooting...\r\n");
for (x=0; x<100; x++) ets_delay_us(1000); for (x=0; x<100; x++) ets_delay_us(1000);
software_reset(); software_reset();