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lcd: add rgb isr iram safe callback test
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@ -64,7 +64,7 @@ typedef struct {
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unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
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unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
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unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
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unsigned int pclk_active_pos: 1; /*!< Whether the display data is clocked out on the rising edge of PCLK */
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unsigned int pclk_active_neg: 1; /*!< Whether the display data is clocked out on the falling edge of PCLK */
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unsigned int pclk_idle_high: 1; /*!< The PCLK stays at high level in IDLE phase */
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} flags;
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} esp_lcd_rgb_timing_t;
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@ -254,7 +254,7 @@ static esp_err_t panel_io_spi_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons
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ESP_GOTO_ON_ERROR(ret, err, TAG, "spi transmit (polling) command failed");
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// split to chunks if required:
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// the SPI bus has a maximum transaction size determined by SPI_USR_MOSI_DBITLEN's bit width
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// the SPI bus has a maximum transaction size determined by SPI_LL_DATA_MAX_BIT_LEN
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do {
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size_t chunk_size = color_size;
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@ -266,7 +266,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
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rgb_panel->timings.pclk_hz = rgb_panel->resolution_hz / pclk_prescale;
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// pixel clock phase and polarity
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lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_idle_high);
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lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, !rgb_panel->timings.flags.pclk_active_pos);
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lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_active_neg);
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// enable RGB mode and set data width
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lcd_ll_enable_rgb_mode(rgb_panel->hal.dev, true);
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lcd_ll_set_data_width(rgb_panel->hal.dev, rgb_panel->data_width);
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@ -134,13 +134,22 @@ TEST_CASE("lcd_rgb_panel_one_shot_mode", "[lcd]")
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}
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#if CONFIG_LCD_RGB_ISR_IRAM_SAFE
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TEST_LCD_CALLBACK_ATTR static bool test_rgb_panel_count_in_callback(esp_lcd_panel_handle_t panel, esp_lcd_rgb_panel_event_data_t *edata, void *user_ctx)
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{
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uint32_t *count = (uint32_t *)user_ctx;
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*count = *count + 1;
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return false;
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}
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TEST_CASE("lcd_rgb_panel_with_nvs_read_write", "[lcd]")
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{
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uint8_t *img = malloc(TEST_IMG_SIZE);
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TEST_ASSERT_NOT_NULL(img);
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uint32_t callback_calls = 0;
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printf("initialize RGB panel with stream mode\r\n");
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esp_lcd_panel_handle_t panel_handle = test_rgb_panel_initialization(true, NULL, NULL);
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esp_lcd_panel_handle_t panel_handle = test_rgb_panel_initialization(true, test_rgb_panel_count_in_callback, &callback_calls);
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printf("flush one clock block to the LCD\r\n");
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uint8_t color_byte = esp_random() & 0xFF;
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int x_start = esp_random() % (TEST_LCD_H_RES - 100);
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@ -176,6 +185,8 @@ TEST_CASE("lcd_rgb_panel_with_nvs_read_write", "[lcd]")
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nvs_close(my_handle);
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TEST_ESP_OK(nvs_flash_deinit());
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TEST_ASSERT(callback_calls > 50);
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printf("delete RGB panel\r\n");
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TEST_ESP_OK(esp_lcd_panel_del(panel_handle));
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free(img);
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@ -116,10 +116,3 @@ I2C
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- ``rmt_set_intr_enable_mask`` and ``rmt_clr_intr_enable_mask`` are removed, as the interrupt is handled by the driver, user doesn't need to take care of it.
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- ``rmt_set_pin`` is removed, as ``rmt_set_gpio`` can do the same thing.
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- ``rmt_memory_rw_rst`` is removed, user can use ``rmt_tx_memory_reset`` and ``rmt_rx_memory_reset`` for TX and RX channel respectively.
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.. only:: SOC_LCD_RGB_SUPPORTED
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RGB LCD Driver
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--------------
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- The `pclk_active_neg` in the RGB timing configuration structure :cpp:type:`esp_lcd_rgb_timing_t` has been changed into `pclk_active_pos`. This was made to change the default PCLK sample moment to **falling** edge. From user side, you don't need to explicitly assign `pclk_active_neg = true` anymore.
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@ -83,6 +83,6 @@ I (741) example: Display LVGL Scatter Chart
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* The frame buffer of RGB panel is located in ESP side (unlike other controller based LCDs, where the frame buffer is located in external chip). As the frame buffer usually consumes much RAM (depends on the LCD resolution and color depth), we recommend to put the frame buffer into PSRAM (like what we do in this example). However, putting frame buffer in PSRAM will limit the PCLK to around 12MHz (due to the bandwidth of PSRAM).
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* LCD screen drift
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* Slow down the PCLK frequency
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* Adjust other timing parameters like PCLK clock edge (by `pclk_active_pos`), sync porches like HBP (by `hsync_back_porch`) according to your LCD spec
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* Adjust other timing parameters like PCLK clock edge (by `pclk_active_neg`), sync porches like HBP (by `hsync_back_porch`) according to your LCD spec
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For any technical queries, please open an [issue] (https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
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@ -124,6 +124,7 @@ void app_main(void)
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.vsync_back_porch = 8,
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.vsync_front_porch = 4,
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.vsync_pulse_width = 1,
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.flags.pclk_active_neg = true,
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},
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.flags.fb_in_psram = 1, // allocate frame buffer in PSRAM
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};
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