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esp32s3: fix interrupt names used by SystemView

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This commit is contained in:
Erhan Kurubas 2022-08-03 14:55:11 +02:00
parent bf622042b7
commit fdc839494f
3 changed files with 99 additions and 82 deletions
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2
components/soc/esp32s3/include/soc/periph_defs.h
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@ -151,7 +151,7 @@ typedef enum {
ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHE_CORE0_ACS_INTR_SOURCE,
ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHE_CORE1_ACS_INTR_SOURCE,
ETS_USB_SERIAL_JTAG_INTR_SOURCE, ETS_USB_SERIAL_JTAG_INTR_SOURCE,
ETS_PREI_BACKUP_INTR_SOURCE, ETS_PERI_BACKUP_INTR_SOURCE,
ETS_DMA_EXTMEM_REJECT_SOURCE, ETS_DMA_EXTMEM_REJECT_SOURCE,
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t; } periph_interrput_t;

178
components/soc/esp32s3/interrupts.c
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@ -1,87 +1,105 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/interrupts.h" #include "soc/interrupts.h"
const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[0] = "WIFI_MAC", [0] = "WIFI_MAC",
[1] = "WIFI_NMI", [1] = "WIFI_NMI",
[2] = "WIFI_BB", [2] = "WIFI_PWR",
[3] = "BT_MAC", [3] = "WIFI_BB",
[4] = "BT_BB", [4] = "BT_MAC",
[5] = "BT_BB_NMI", [5] = "BT_BB",
[6] = "RWBT", [6] = "BT_BB_NMI",
[7] = "RWBLE", [7] = "RWBT",
[8] = "RWBT_NMI", [8] = "RWBLE",
[9] = "RWBLE_NMI", [9] = "RWBT_NMI",
[10] = "SLC0", [10] = "RWBLE_NMI",
[11] = "SLC1", [11] = "I2C_MASTER",
[12] = "UHCI0", [12] = "SLC0",
[13] = "UHCI1", [13] = "SLC1",
[14] = "TG0_T0_LEVEL", [14] = "UHCI0",
[15] = "TG0_T1_LEVEL", [15] = "UHCI1",
[16] = "TG0_WDT_LEVEL", [16] = "GPIO",
[17] = "TG0_LACT_LEVEL", [17] = "GPIO_NMI",
[18] = "TG1_T0_LEVEL", [18] = "GPIO_INTR_2",
[19] = "TG1_T1_LEVEL", [19] = "GPIO_NMI_2",
[20] = "TG1_WDT_LEVEL", [20] = "SPI1",
[21] = "TG1_LACT_LEVEL", [21] = "SPI2",
[22] = "GPIO", [22] = "SPI3",
[23] = "GPIO_NMI", [24] = "LCD_CAM",
[24] = "FROM_CPU0", [25] = "I2S0",
[25] = "FROM_CPU1", [26] = "I2S1",
[26] = "FROM_CPU2", [27] = "UART0",
[27] = "FROM_CPU3", [28] = "UART1",
[28] = "SPI0", [29] = "UART2",
[29] = "SPI1", [30] = "SDIO_HOST",
[30] = "SPI2", [31] = "PWM0",
[31] = "SPI3", [32] = "PWM1",
[32] = "I2S0", [35] = "LEDC",
[33] = "I2S1", [36] = "EFUSE",
[34] = "UART0", [37] = "TWAI",
[35] = "UART1", [38] = "USB",
[36] = "UART2", [39] = "RTC_CORE",
[37] = "SDIO_HOST", [40] = "RMT",
[38] = "ETH_MAC", [41] = "PCNT",
[39] = "PWM0", [42] = "I2C_EXT0",
[40] = "PWM1", [43] = "I2C_EXT1",
[41] = "PWM2", [44] = "SPI2_DMA",
[42] = "PWM3", [45] = "SPI3_DMA",
[43] = "LEDC", [47] = "WDT",
[44] = "EFUSE", [48] = "TIMER1",
[45] = "TWAI", [49] = "TIMER2",
[46] = "RTC_CORE", [50] = "TG0_T0_LEVEL",
[47] = "RMT", [51] = "TG0_T1_LEVEL",
[48] = "PCNT", [52] = "TG0_WDT_LEVEL",
[49] = "I2C_EXT0", [53] = "TG1_T0_LEVEL",
[50] = "I2C_EXT1", [54] = "TG1_T1_LEVEL",
[51] = "RSA", [55] = "TG1_WDT_LEVEL",
[52] = "SPI1_DMA", [56] = "CACHE_IA",
[53] = "SPI2_DMA", [57] = "SYSTIMER_TARGET0",
[54] = "SPI3_DMA", [58] = "SYSTIMER_TARGET1",
[55] = "WDT", [59] = "SYSTIMER_TARGET2",
[56] = "TIMER1", [60] = "SPI_MEM_REJECT_CACHE",
[57] = "TIMER2", [61] = "DCACHE_PRELOAD0",
[58] = "TG0_T0_EDGE", [62] = "ICACHE_PRELOAD0",
[59] = "TG0_T1_EDGE", [63] = "DCACHE_SYNC0",
[60] = "TG0_WDT_EDGE", [64] = "ICACHE_SYNC0",
[61] = "TG0_LACT_EDGE", [65] = "APB_ADC",
[62] = "TG1_T0_EDGE", [66] = "DMA_IN_CH0",
[63] = "TG1_T1_EDGE", [67] = "DMA_IN_CH1",
[64] = "TG1_WDT_EDGE", [68] = "DMA_IN_CH2",
[65] = "TG1_LACT_EDGE", [69] = "DMA_IN_CH3",
[66] = "MMU_IA", [70] = "DMA_IN_CH4",
[67] = "MPU_IA", [71] = "DMA_OUT_CH0",
[68] = "CACHE_IA", [72] = "DMA_OUT_CH1",
[73] = "DMA_OUT_CH2",
[74] = "DMA_OUT_CH3",
[75] = "DMA_OUT_CH4",
[76] = "RSA",
[77] = "SHA",
[78] = "AES",
[79] = "FROM_CPU_INTR0",
[80] = "FROM_CPU_INTR1",
[81] = "FROM_CPU_INTR2",
[82] = "FROM_CPU_INTR3",
[83] = "ASSIST_DEBUG",
[84] = "DMA_APBPERI_PMS",
[85] = "CORE0_IRAM0_PMS",
[86] = "CORE0_DRAM0_PMS",
[87] = "CORE0_PIF_PMS",
[88] = "CORE0_PIF_PMS_SIZE",
[89] = "CORE1_IRAM0_PMS",
[90] = "CORE1_DRAM0_PMS",
[91] = "CORE1_PIF_PMS",
[92] = "CORE1_PIF_PMS_SIZE",
[93] = "BACKUP_PMS_VIOLATE",
[94] = "CACHE_CORE0_ACS",
[95] = "CACHE_CORE1_ACS",
[96] = "USB_SERIAL_JTAG",
[97] = "PERI_BACKUP",
[98] = "DMA_EXTMEM_REJECT",
}; };

1
tools/ci/check_copyright_ignore.txt
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@ -1257,7 +1257,6 @@ components/soc/esp32s3/include/soc/usb_wrap_struct.h
components/soc/esp32s3/include/soc/usbh_struct.h components/soc/esp32s3/include/soc/usbh_struct.h
components/soc/esp32s3/include/soc/wdev_reg.h components/soc/esp32s3/include/soc/wdev_reg.h
components/soc/esp32s3/include/soc/world_controller_reg.h components/soc/esp32s3/include/soc/world_controller_reg.h
components/soc/esp32s3/interrupts.c
components/soc/esp32s3/ledc_periph.c components/soc/esp32s3/ledc_periph.c
components/soc/esp32s3/rtc_io_periph.c components/soc/esp32s3/rtc_io_periph.c
components/soc/esp32s3/sdio_slave_periph.c components/soc/esp32s3/sdio_slave_periph.c