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sdm: fixed wrong sdm struct sequence on esp32h2

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This commit is contained in:
laokaiyao 2023-02-24 15:46:15 +08:00 committed by morris
parent af805df3cb
commit fd5bfb2cd4
4 changed files with 49 additions and 48 deletions
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62
components/soc/esp32c6/include/soc/gpio_ext_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -34,58 +34,58 @@ extern "C" {
* Duty Cycle Configure Register of SDM1
*/
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4)
/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0;
/** GPIO_SD1_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD0_IN 0x000000FFU
#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S)
#define GPIO_SD0_IN_V 0x000000FFU
#define GPIO_SD0_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
#define GPIO_SD1_IN 0x000000FFU
#define GPIO_SD1_IN_M (GPIO_SD1_IN_V << GPIO_SD1_IN_S)
#define GPIO_SD1_IN_V 0x000000FFU
#define GPIO_SD1_IN_S 0
/** GPIO_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD1_PRESCALE 0x000000FFU
#define GPIO_SD1_PRESCALE_M (GPIO_SD1_PRESCALE_V << GPIO_SD1_PRESCALE_S)
#define GPIO_SD1_PRESCALE_V 0x000000FFU
#define GPIO_SD1_PRESCALE_S 8
/** GPIO_SIGMADELTA2_REG register
* Duty Cycle Configure Register of SDM2
*/
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8)
/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0;
/** GPIO_SD2_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD0_IN 0x000000FFU
#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S)
#define GPIO_SD0_IN_V 0x000000FFU
#define GPIO_SD0_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
#define GPIO_SD2_IN 0x000000FFU
#define GPIO_SD2_IN_M (GPIO_SD2_IN_V << GPIO_SD2_IN_S)
#define GPIO_SD2_IN_V 0x000000FFU
#define GPIO_SD2_IN_S 0
/** GPIO_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD2_PRESCALE 0x000000FFU
#define GPIO_SD2_PRESCALE_M (GPIO_SD2_PRESCALE_V << GPIO_SD2_PRESCALE_S)
#define GPIO_SD2_PRESCALE_V 0x000000FFU
#define GPIO_SD2_PRESCALE_S 8
/** GPIO_SIGMADELTA3_REG register
* Duty Cycle Configure Register of SDM3
*/
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc)
/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0;
/** GPIO_SD3_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD0_IN 0x000000FFU
#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S)
#define GPIO_SD0_IN_V 0x000000FFU
#define GPIO_SD0_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
#define GPIO_SD3_IN 0x000000FFU
#define GPIO_SD3_IN_M (GPIO_SD3_IN_V << GPIO_SD3_IN_S)
#define GPIO_SD3_IN_V 0x000000FFU
#define GPIO_SD3_IN_S 0
/** GPIO_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD3_PRESCALE 0x000000FFU
#define GPIO_SD3_PRESCALE_M (GPIO_SD3_PRESCALE_V << GPIO_SD3_PRESCALE_S)
#define GPIO_SD3_PRESCALE_V 0x000000FFU
#define GPIO_SD3_PRESCALE_S 8
/** GPIO_CLOCK_GATE_REG register
* Clock Gating Configure Register

32
components/soc/esp32h2/include/soc/gpio_ext_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -41,13 +41,13 @@ extern "C" {
#define GPIO_SD1_IN_M (GPIO_SD1_IN_V << GPIO_SD1_IN_S)
#define GPIO_SD1_IN_V 0x000000FFU
#define GPIO_SD1_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
/** GPIO_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD1_PRESCALE 0x000000FFU
#define GPIO_SD1_PRESCALE_M (GPIO_SD1_PRESCALE_V << GPIO_SD1_PRESCALE_S)
#define GPIO_SD1_PRESCALE_V 0x000000FFU
#define GPIO_SD1_PRESCALE_S 8
/** GPIO_SIGMADELTA2_REG register
* Duty Cycle Configure Register of SDM2
@ -60,13 +60,13 @@ extern "C" {
#define GPIO_SD2_IN_M (GPIO_SD2_IN_V << GPIO_SD2_IN_S)
#define GPIO_SD2_IN_V 0x000000FFU
#define GPIO_SD2_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
/** GPIO_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD2_PRESCALE 0x000000FFU
#define GPIO_SD2_PRESCALE_M (GPIO_SD2_PRESCALE_V << GPIO_SD2_PRESCALE_S)
#define GPIO_SD2_PRESCALE_V 0x000000FFU
#define GPIO_SD2_PRESCALE_S 8
/** GPIO_SIGMADELTA3_REG register
* Duty Cycle Configure Register of SDM3
@ -79,13 +79,13 @@ extern "C" {
#define GPIO_SD3_IN_M (GPIO_SD3_IN_V << GPIO_SD3_IN_S)
#define GPIO_SD3_IN_V 0x000000FFU
#define GPIO_SD3_IN_S 0
/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
/** GPIO_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD0_PRESCALE 0x000000FFU
#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S)
#define GPIO_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD0_PRESCALE_S 8
#define GPIO_SD3_PRESCALE 0x000000FFU
#define GPIO_SD3_PRESCALE_M (GPIO_SD3_PRESCALE_V << GPIO_SD3_PRESCALE_S)
#define GPIO_SD3_PRESCALE_V 0x000000FFU
#define GPIO_SD3_PRESCALE_S 8
/** GPIO_CLOCK_GATE_REG register
* Clock Gating Configure Register

2
components/soc/esp32h2/include/soc/gpio_ext_struct.h
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@ -275,8 +275,8 @@ typedef union {
typedef struct gpio_sd_dev_t {
volatile gpio_sigmadelta_chn_reg_t channel[4];
uint32_t reserved_010[4];
volatile gpio_sigmadelta_misc_reg_t misc;
volatile gpio_sigmadelta_clock_gate_reg_t clock_gate;
volatile gpio_sigmadelta_misc_reg_t misc;
} gpio_sd_dev_t;
typedef struct {

1
components/soc/esp32h2/include/soc/reg_base.h
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@ -40,6 +40,7 @@
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_LPPERI_BASE 0x600B2800
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_GPIO_EXT_BASE 0x60091f00
#define DR_REG_MEM_ACS_MONITOR_BASE 0x60092000
#define DR_REG_REGDMA_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000