From fd325c9fa2891b974de4b3c15fedf46019dd1535 Mon Sep 17 00:00:00 2001
From: morris <maoshengrong@espressif.com>
Date: Thu, 15 Sep 2022 10:53:35 +0800
Subject: [PATCH] fast_gpio: bring up fast gpio driver on esp32c6

---
 .../esp32c6/include/hal/dedic_gpio_cpu_ll.h   | 55 +++++++++++++++++++
 components/soc/esp32c6/CMakeLists.txt         |  1 -
 .../esp32c6/include/soc/Kconfig.soc_caps.in   |  4 ++
 components/soc/esp32c6/include/soc/soc_caps.h |  3 +-
 4 files changed, 60 insertions(+), 3 deletions(-)
 create mode 100644 components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h

diff --git a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h
new file mode 100644
index 0000000000..0b08505346
--- /dev/null
+++ b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "riscv/csr.h"
+
+/*fast gpio*/
+#define CSR_GPIO_OEN_USER   0x803
+#define CSR_GPIO_IN_USER    0x804
+#define CSR_GPIO_OUT_USER   0x805
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
+{
+    RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
+}
+
+static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
+{
+    RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
+{
+    RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
+    RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/CMakeLists.txt b/components/soc/esp32c6/CMakeLists.txt
index 56d16c0e71..be4b01b78f 100644
--- a/components/soc/esp32c6/CMakeLists.txt
+++ b/components/soc/esp32c6/CMakeLists.txt
@@ -18,7 +18,6 @@ set(srcs
 # ESP32C6-TODO
 list(REMOVE_ITEM srcs
         "adc_periph.c"                  # TODO: IDF-5310
-        "dedic_gpio_periph.c"           # TODO: IDF-5331
         "ledc_periph.c"                 # TODO: IDF-5328
         "i2s_periph.c"                  # TODO: IDF-5314
         "i2c_periph.c"                  # TODO: IDF-5326
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index c654e5472c..80d7c073a7 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -3,6 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_DEDICATED_GPIO_SUPPORTED
+    bool
+    default y
+
 config SOC_GDMA_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 46836c604f..1732c80996 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -26,7 +26,7 @@
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1 // TODO: IDF-5310
-// #define SOC_DEDICATED_GPIO_SUPPORTED    1 // TODO: IDF-5331
+#define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_PCNT_SUPPORTED              1
 // #define SOC_TWAI_SUPPORTED              1 // TODO: IDF-5313
@@ -161,7 +161,6 @@
 // Support to configure sleep status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
 
-// TODO: IDF-5331 (Copy from esp32c3, need check)
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */