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Merge branch 'bugfix/fix_esp32p4_deepsleep_gpio_wakeup_support' into 'master'

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feat(esp_hw_support): support esp32p4 gpio/ext1 wakeup deepsleep

Closes PM-158

See merge request espressif/esp-idf!31583
This commit is contained in:
Wu Zheng Hui 2024-07-16 22:09:44 +08:00
commit fcd0b82c1c
17 changed files with 63 additions and 9 deletions
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6
components/esp_hw_support/include/esp_private/esp_pmu.h
View File

@ -62,7 +62,11 @@ typedef enum {
#define RTC_EXT1_TRIG_EN 0
#endif
#define RTC_GPIO_TRIG_EN PMU_GPIO_WAKEUP_EN //!< GPIO wakeup
#if SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN | PMU_LP_GPIO_WAKEUP_EN) //!< GPIO & LP_GPIO wakeup
#else
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN)
#endif
#if SOC_LP_TIMER_SUPPORTED
#define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup

9
components/esp_hw_support/port/esp32p4/pmu_sleep.c
View File

@ -154,6 +154,10 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(pd_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
config->analog = analog_default;
} else {
@ -200,6 +204,7 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
{
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all);
}
static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
@ -255,9 +260,7 @@ void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
{
assert(PMU_instance());
pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
if(!dslp){
pmu_sleep_digital_init(PMU_instance(), &config->digital);
}
pmu_sleep_digital_init(PMU_instance(), &config->digital);
pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
}

11
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
View File

@ -314,9 +314,18 @@ typedef struct {
pmu_hp_sys_cntl_reg_t syscntl;
} pmu_sleep_digital_config_t;
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(pd_flags) { \
.syscntl = { \
.dig_pad_slp_sel = 0, \
.lp_pad_hold_all = (pd_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
} \
}
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags) { \
.syscntl = { \
.dig_pad_slp_sel = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pad_slp_sel = (pd_flags & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.lp_pad_hold_all = (pd_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
} \
}

4
components/esp_hw_support/sleep_modes.c
View File

@ -217,8 +217,8 @@ typedef struct {
uint32_t ext0_rtc_gpio_num : 5;
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
uint32_t gpio_wakeup_mask : 8; // 8 is the maximum RTCIO number in all chips that support GPIO wakeup
uint32_t gpio_trigger_mode : 8;
uint32_t gpio_wakeup_mask : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT; // Only RTC_GPIO supports wakeup deepsleep
uint32_t gpio_trigger_mode : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT;
#endif
uint32_t sleep_time_adjustment;
uint32_t ccount_ticks_record;

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -311,6 +311,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 6
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000001FFFC0

1
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -135,6 +135,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -403,6 +403,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 6
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000003FFFC0

1
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -173,6 +173,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -351,6 +351,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 8
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000001FFFF00

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -210,6 +210,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -503,6 +503,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 8
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000007FFFFF00

1
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -204,6 +204,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -191,6 +191,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 7
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000003FFF80

1
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -201,6 +201,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -599,6 +599,10 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE
bool
default y
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x007FFFFFFFFFFFFF
@ -615,6 +619,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 16
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x007FFFFFFFFF0000

2
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -233,6 +233,7 @@
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1)
#define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
@ -241,6 +242,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 54
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (16)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL

7
examples/system/deep_sleep/main/Kconfig.projbuild
View File

@ -44,6 +44,7 @@ menu "Example Configuration"
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
range 0 15 if IDF_TARGET_ESP32P4
choice EXAMPLE_EXT1_WAKEUP_PIN_1_SEL
prompt "Enable wakeup from PIN_1"
@ -118,6 +119,7 @@ menu "Example Configuration"
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
range 0 15 if IDF_TARGET_ESP32P4
choice EXAMPLE_EXT1_WAKEUP_PIN_2_SEL
prompt "Enable wakeup from PIN_2"
@ -247,7 +249,7 @@ menu "Example Configuration"
if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH domain,
we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep.
but if we turn on the RTC_PERIPH domain, we don not need to use HOLD feature and this will
increase some power comsumption.
increase some power consumption.
EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal
pull-up/downs are always available. There's no need to explicitly force it on for EXT0.
@ -259,7 +261,7 @@ menu "Example Configuration"
depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
help
This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly
recommand you to connect external pull-up resistance.
recommend you to connect external pull-up resistance.
menu "GPIO wakeup configuration"
visible if EXAMPLE_GPIO_WAKEUP
@ -268,6 +270,7 @@ menu "Example Configuration"
int "Enable wakeup from GPIO"
default 0
range 0 7 if IDF_TARGET_ESP32C6
range 0 15 if IDF_TARGET_ESP32P4
range 0 5 if !IDF_TARGET_ESP32C6
config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL