diff --git a/components/esp_hw_support/port/esp32/esp_clk_tree.c b/components/esp_hw_support/port/esp32/esp_clk_tree.c
index e748df5d4c..03f29bd875 100644
--- a/components/esp_hw_support/port/esp32/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32/esp_clk_tree.c
@@ -55,7 +55,7 @@ uint32_t *freq_value)
         clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
         break;
     case SOC_MOD_CLK_REF_TICK:
-        clk_src_freq = 1 * MHZ;
+        clk_src_freq = REF_CLK_FREQ;
         break;
     case SOC_MOD_CLK_APLL:
         clk_src_freq = clk_hal_apll_get_freq_hz();
diff --git a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c
index ff9e20571d..cccf7ebf0a 100644
--- a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c
@@ -53,7 +53,7 @@ uint32_t *freq_value)
         clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
         break;
     case SOC_MOD_CLK_REF_TICK:
-        clk_src_freq = 1 * MHZ;
+        clk_src_freq = REF_CLK_FREQ;
         break;
     case SOC_MOD_CLK_APLL:
         clk_src_freq = clk_hal_apll_get_freq_hz();
diff --git a/components/hal/esp32/include/hal/clk_tree_ll.h b/components/hal/esp32/include/hal/clk_tree_ll.h
index f8467a7c0a..300ad8cb76 100644
--- a/components/hal/esp32/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32/include/hal/clk_tree_ll.h
@@ -669,31 +669,31 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_fro
 }
 
 /**
- * @brief Set REF_TICK divider to make REF_TICK frequency at 1MHz
+ * @brief Set REF_TICK divider to make REF_TICK frequency at REF_CLK_FREQ
  *
  * @param cpu_clk_src Selected CPU clock source (one of soc_cpu_clk_src_t values)
  * @param cpu_freq_mhz CPU frequency value, in MHz
  *
- * Divider = APB_CLK freq in Hz / 1MHz. Value in register = divider - 1.
+ * Divider = APB_CLK freq in Hz / (REF_CLK_FREQ / MHZ). Value in register = divider - 1.
  */
 static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(soc_cpu_clk_src_t cpu_clk_src, uint32_t cpu_freq_mhz)
 {
     uint32_t apb_freq_mhz;
     switch (cpu_clk_src) {
     case SOC_CPU_CLK_SRC_XTAL:
-        apb_freq_mhz = cpu_freq_mhz;
+        apb_freq_mhz = cpu_freq_mhz / (REF_CLK_FREQ / MHZ);
         REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, apb_freq_mhz - 1);
         break;
     case SOC_CPU_CLK_SRC_PLL:
-        apb_freq_mhz = 80;
+        apb_freq_mhz = 80 / (REF_CLK_FREQ / MHZ);
         REG_WRITE(SYSCON_PLL_TICK_CONF_REG, apb_freq_mhz - 1);
         break;
     case SOC_CPU_CLK_SRC_RC_FAST:
-        apb_freq_mhz = cpu_freq_mhz;
+        apb_freq_mhz = cpu_freq_mhz / (REF_CLK_FREQ / MHZ);
         REG_WRITE(SYSCON_CK8M_TICK_CONF_REG, apb_freq_mhz - 1);
         break;
     case SOC_CPU_CLK_SRC_APLL:
-        apb_freq_mhz = cpu_freq_mhz >> 1;
+        apb_freq_mhz = (cpu_freq_mhz / (REF_CLK_FREQ / MHZ)) >> 1;
         REG_WRITE(SYSCON_APLL_TICK_CONF_REG, apb_freq_mhz - 1);
         break;
     default: