From fb3d24739ac66ab44c152da71d687bde882199f1 Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 24 Apr 2023 13:33:12 +0800 Subject: [PATCH] soc: sync lcd_cam register description with TRM Closes https://github.com/espressif/esp-idf/issues/11257 --- .../soc/esp32s3/include/soc/lcd_cam_reg.h | 396 +++++++++--------- .../soc/esp32s3/include/soc/lcd_cam_struct.h | 388 ++++++++--------- 2 files changed, 398 insertions(+), 386 deletions(-) diff --git a/components/soc/esp32s3/include/soc/lcd_cam_reg.h b/components/soc/esp32s3/include/soc/lcd_cam_reg.h index 85c5cc0160..a51d26c6a3 100644 --- a/components/soc/esp32s3/include/soc/lcd_cam_reg.h +++ b/components/soc/esp32s3/include/soc/lcd_cam_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -12,68 +12,74 @@ extern "C" { #endif /** LCD_CAM_LCD_CLOCK_REG register - * LCD clock register + * LCD clock configuration register */ #define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0) -/** LCD_CAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3; - * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. +/** LCD_CAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 0; + * fLCD_PCLK + * = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is + * 0. Note: this field must not be configured to 0. */ #define LCD_CAM_LCD_CLKCNT_N 0x0000003FU #define LCD_CAM_LCD_CLKCNT_N_M (LCD_CAM_LCD_CLKCNT_N_V << LCD_CAM_LCD_CLKCNT_N_S) #define LCD_CAM_LCD_CLKCNT_N_V 0x0000003FU #define LCD_CAM_LCD_CLKCNT_N_S 0 -/** LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1; - * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). +/** LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 0; + * 1: fLCD_PCLK + * = fLCD_CLK. 0: fLCD_PCLK + * = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1). */ #define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) #define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (LCD_CAM_LCD_CLK_EQU_SYSCLK_V << LCD_CAM_LCD_CLK_EQU_SYSCLK_S) #define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x00000001U #define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 /** LCD_CAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0; - * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + * 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle. */ #define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) #define LCD_CAM_LCD_CK_IDLE_EDGE_M (LCD_CAM_LCD_CK_IDLE_EDGE_V << LCD_CAM_LCD_CK_IDLE_EDGE_S) #define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x00000001U #define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 /** LCD_CAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0; - * 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock - * cycle. + * 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first + * half clock cycle. */ #define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) #define LCD_CAM_LCD_CK_OUT_EDGE_M (LCD_CAM_LCD_CK_OUT_EDGE_V << LCD_CAM_LCD_CK_OUT_EDGE_S) #define LCD_CAM_LCD_CK_OUT_EDGE_V 0x00000001U #define LCD_CAM_LCD_CK_OUT_EDGE_S 8 -/** LCD_CAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; - * Integral LCD clock divider value +/** LCD_CAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 0; + * Integral LCD clock divider value. */ #define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FFU #define LCD_CAM_LCD_CLKM_DIV_NUM_M (LCD_CAM_LCD_CLKM_DIV_NUM_V << LCD_CAM_LCD_CLKM_DIV_NUM_S) #define LCD_CAM_LCD_CLKM_DIV_NUM_V 0x000000FFU #define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 /** LCD_CAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value + * Fractional clock divider numerator value. */ #define LCD_CAM_LCD_CLKM_DIV_B 0x0000003FU #define LCD_CAM_LCD_CLKM_DIV_B_M (LCD_CAM_LCD_CLKM_DIV_B_V << LCD_CAM_LCD_CLKM_DIV_B_S) #define LCD_CAM_LCD_CLKM_DIV_B_V 0x0000003FU #define LCD_CAM_LCD_CLKM_DIV_B_S 17 /** LCD_CAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value + * Fractional clock divider denominator value. */ #define LCD_CAM_LCD_CLKM_DIV_A 0x0000003FU #define LCD_CAM_LCD_CLKM_DIV_A_M (LCD_CAM_LCD_CLKM_DIV_A_V << LCD_CAM_LCD_CLKM_DIV_A_S) #define LCD_CAM_LCD_CLKM_DIV_A_V 0x0000003FU #define LCD_CAM_LCD_CLKM_DIV_A_S 23 /** LCD_CAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0; - * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + * Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: + * PLL_D2_CLK. 3: PLL_F160M_CLK. */ #define LCD_CAM_LCD_CLK_SEL 0x00000003U #define LCD_CAM_LCD_CLK_SEL_M (LCD_CAM_LCD_CLK_SEL_V << LCD_CAM_LCD_CLK_SEL_S) #define LCD_CAM_LCD_CLK_SEL_V 0x00000003U #define LCD_CAM_LCD_CLK_SEL_S 29 /** LCD_CAM_CLK_EN : R/W; bitpos: [31]; default: 0; - * Set this bit to enable clk gate + * Set this bit to force enable the clock for all configuration registers. Clock gate + * is not used. */ #define LCD_CAM_CLK_EN (BIT(31)) #define LCD_CAM_CLK_EN_M (LCD_CAM_CLK_EN_V << LCD_CAM_CLK_EN_S) @@ -81,11 +87,12 @@ extern "C" { #define LCD_CAM_CLK_EN_S 31 /** LCD_CAM_CAM_CTRL_REG register - * Camera configuration register + * Camera clock configuration register */ #define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4) /** LCD_CAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0; - * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + * Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not + * stop. */ #define LCD_CAM_CAM_STOP_EN (BIT(0)) #define LCD_CAM_CAM_STOP_EN_M (LCD_CAM_CAM_STOP_EN_V << LCD_CAM_CAM_STOP_EN_S) @@ -98,66 +105,67 @@ extern "C" { #define LCD_CAM_CAM_VSYNC_FILTER_THRES_M (LCD_CAM_CAM_VSYNC_FILTER_THRES_V << LCD_CAM_CAM_VSYNC_FILTER_THRES_S) #define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x00000007U #define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 -/** LCD_CAM_CAM_UPDATE_REG : R/W; bitpos: [4]; default: 0; - * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. +/** LCD_CAM_CAM_UPDATE : R/W; bitpos: [4]; default: 0; + * 1: Update camera registers. This bit is cleared by hardware. 0: Do not care. */ -#define LCD_CAM_CAM_UPDATE_REG (BIT(4)) -#define LCD_CAM_CAM_UPDATE_REG_M (LCD_CAM_CAM_UPDATE_REG_V << LCD_CAM_CAM_UPDATE_REG_S) -#define LCD_CAM_CAM_UPDATE_REG_V 0x00000001U -#define LCD_CAM_CAM_UPDATE_REG_S 4 +#define LCD_CAM_CAM_UPDATE (BIT(4)) +#define LCD_CAM_CAM_UPDATE_M (LCD_CAM_CAM_UPDATE_V << LCD_CAM_CAM_UPDATE_S) +#define LCD_CAM_CAM_UPDATE_V 0x00000001U +#define LCD_CAM_CAM_UPDATE_S 4 /** LCD_CAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + * 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change. */ #define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) #define LCD_CAM_CAM_BYTE_ORDER_M (LCD_CAM_CAM_BYTE_ORDER_V << LCD_CAM_CAM_BYTE_ORDER_S) #define LCD_CAM_CAM_BYTE_ORDER_V 0x00000001U #define LCD_CAM_CAM_BYTE_ORDER_S 5 /** LCD_CAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit + * mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. */ #define LCD_CAM_CAM_BIT_ORDER (BIT(6)) #define LCD_CAM_CAM_BIT_ORDER_M (LCD_CAM_CAM_BIT_ORDER_V << LCD_CAM_CAM_BIT_ORDER_S) #define LCD_CAM_CAM_BIT_ORDER_V 0x00000001U #define LCD_CAM_CAM_BIT_ORDER_S 6 /** LCD_CAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0; - * 1: Enable to generate CAM_HS_INT. 0: Disable. + * 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable. */ #define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) #define LCD_CAM_CAM_LINE_INT_EN_M (LCD_CAM_CAM_LINE_INT_EN_V << LCD_CAM_CAM_LINE_INT_EN_S) #define LCD_CAM_CAM_LINE_INT_EN_V 0x00000001U #define LCD_CAM_CAM_LINE_INT_EN_S 7 /** LCD_CAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0; - * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by - * reg_cam_rec_data_cyclelen. + * 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * LCD_CAM_CAM_REC_DATA_BYTELEN. */ #define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) #define LCD_CAM_CAM_VS_EOF_EN_M (LCD_CAM_CAM_VS_EOF_EN_V << LCD_CAM_CAM_VS_EOF_EN_S) #define LCD_CAM_CAM_VS_EOF_EN_V 0x00000001U #define LCD_CAM_CAM_VS_EOF_EN_S 8 -/** LCD_CAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; - * Integral Camera clock divider value +/** LCD_CAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 0; + * Integral camera clock divider value. */ #define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FFU #define LCD_CAM_CAM_CLKM_DIV_NUM_M (LCD_CAM_CAM_CLKM_DIV_NUM_V << LCD_CAM_CAM_CLKM_DIV_NUM_S) #define LCD_CAM_CAM_CLKM_DIV_NUM_V 0x000000FFU #define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 /** LCD_CAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value + * Fractional clock divider numerator value. */ #define LCD_CAM_CAM_CLKM_DIV_B 0x0000003FU #define LCD_CAM_CAM_CLKM_DIV_B_M (LCD_CAM_CAM_CLKM_DIV_B_V << LCD_CAM_CAM_CLKM_DIV_B_S) #define LCD_CAM_CAM_CLKM_DIV_B_V 0x0000003FU #define LCD_CAM_CAM_CLKM_DIV_B_S 17 /** LCD_CAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value + * Fractional clock divider denominator value. */ #define LCD_CAM_CAM_CLKM_DIV_A 0x0000003FU #define LCD_CAM_CAM_CLKM_DIV_A_M (LCD_CAM_CAM_CLKM_DIV_A_V << LCD_CAM_CAM_CLKM_DIV_A_S) #define LCD_CAM_CAM_CLKM_DIV_A_V 0x0000003FU #define LCD_CAM_CAM_CLKM_DIV_A_S 23 /** LCD_CAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0; - * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + * Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: + * PLL_D2_CLK. 3: PLL_F160M_CLK. */ #define LCD_CAM_CAM_CLK_SEL 0x00000003U #define LCD_CAM_CAM_CLK_SEL_M (LCD_CAM_CAM_CLK_SEL_V << LCD_CAM_CAM_CLK_SEL_S) @@ -165,39 +173,41 @@ extern "C" { #define LCD_CAM_CAM_CLK_SEL_S 29 /** LCD_CAM_CAM_CTRL1_REG register - * Camera configuration register + * Camera control register */ #define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8) /** LCD_CAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0; - * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + * Configure camera received data byte length. When the length of received data + * reaches this value + 1, GDMA in_suc_eof_int is triggered. */ #define LCD_CAM_CAM_REC_DATA_BYTELEN 0x0000FFFFU #define LCD_CAM_CAM_REC_DATA_BYTELEN_M (LCD_CAM_CAM_REC_DATA_BYTELEN_V << LCD_CAM_CAM_REC_DATA_BYTELEN_S) #define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0x0000FFFFU #define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 /** LCD_CAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0; - * The line number minus 1 to generate cam_hs_int. + * Configure line number. When the number of received lines reaches this value + 1, + * LCD_CAM_CAM_HS_INT is triggered. */ #define LCD_CAM_CAM_LINE_INT_NUM 0x0000003FU #define LCD_CAM_CAM_LINE_INT_NUM_M (LCD_CAM_CAM_LINE_INT_NUM_V << LCD_CAM_CAM_LINE_INT_NUM_S) #define LCD_CAM_CAM_LINE_INT_NUM_V 0x0000003FU #define LCD_CAM_CAM_LINE_INT_NUM_S 16 /** LCD_CAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0; - * 1: Invert the input signal CAM_PCLK. 0: Not invert. + * 1: Invert the input signal CAM_PCLK. 0: Do not invert. */ #define LCD_CAM_CAM_CLK_INV (BIT(22)) #define LCD_CAM_CAM_CLK_INV_M (LCD_CAM_CAM_CLK_INV_V << LCD_CAM_CAM_CLK_INV_S) #define LCD_CAM_CAM_CLK_INV_V 0x00000001U #define LCD_CAM_CAM_CLK_INV_S 22 /** LCD_CAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0; - * 1: Enable CAM_VSYNC filter function. 0: bypass. + * 1: Enable CAM_VSYNC filter function. 0: Bypass. */ #define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) #define LCD_CAM_CAM_VSYNC_FILTER_EN_M (LCD_CAM_CAM_VSYNC_FILTER_EN_V << LCD_CAM_CAM_VSYNC_FILTER_EN_S) #define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x00000001U #define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 /** LCD_CAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0; - * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + * 1: The width of input data is 16 bits. 0: The width of input data is 8 bits. */ #define LCD_CAM_CAM_2BYTE_EN (BIT(24)) #define LCD_CAM_CAM_2BYTE_EN_M (LCD_CAM_CAM_2BYTE_EN_V << LCD_CAM_CAM_2BYTE_EN_S) @@ -225,8 +235,9 @@ extern "C" { #define LCD_CAM_CAM_VSYNC_INV_V 0x00000001U #define LCD_CAM_CAM_VSYNC_INV_S 27 /** LCD_CAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0; - * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control - * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + * 1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control + * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same + * time. */ #define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) #define LCD_CAM_CAM_VH_DE_MODE_EN_M (LCD_CAM_CAM_VH_DE_MODE_EN_V << LCD_CAM_CAM_VH_DE_MODE_EN_S) @@ -247,7 +258,7 @@ extern "C" { #define LCD_CAM_CAM_RESET_V 0x00000001U #define LCD_CAM_CAM_RESET_S 30 /** LCD_CAM_CAM_AFIFO_RESET : WO; bitpos: [31]; default: 0; - * Camera AFIFO reset signal. + * Camera Async Rx FIFO reset signal. */ #define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) #define LCD_CAM_CAM_AFIFO_RESET_M (LCD_CAM_CAM_AFIFO_RESET_V << LCD_CAM_CAM_AFIFO_RESET_S) @@ -255,62 +266,66 @@ extern "C" { #define LCD_CAM_CAM_AFIFO_RESET_S 31 /** LCD_CAM_CAM_RGB_YUV_REG register - * Camera configuration register + * Camera data format conversion register */ #define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xc) /** LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. + * Swap every two 8-bit input data. 1: Enabled. 0: Disabled. */ #define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (LCD_CAM_CAM_CONV_8BITS_DATA_INV_V << LCD_CAM_CAM_CONV_8BITS_DATA_INV_S) #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x00000001U #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 -/** LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. +/** LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 0; + * In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to + * YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable + * YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1. */ #define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003U #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M (LCD_CAM_CAM_CONV_YUV2YUV_MODE_V << LCD_CAM_CAM_CONV_YUV2YUV_MODE_S) #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x00000003U #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 /** LCD_CAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in + * In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV + * mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 + * format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted + * to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to + * YUV411 format. */ #define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003U #define LCD_CAM_CAM_CONV_YUV_MODE_M (LCD_CAM_CAM_CONV_YUV_MODE_V << LCD_CAM_CAM_CONV_YUV_MODE_S) #define LCD_CAM_CAM_CONV_YUV_MODE_V 0x00000003U #define LCD_CAM_CAM_CONV_YUV_MODE_S 24 /** LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. + * 0: BT601. 1: BT709. */ #define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (LCD_CAM_CAM_CONV_PROTOCOL_MODE_V << LCD_CAM_CAM_CONV_PROTOCOL_MODE_S) #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x00000001U #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 /** LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full + * Configure color range for output data. 0: limited color range. 1: full color range. */ #define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (LCD_CAM_CAM_CONV_DATA_OUT_MODE_V << LCD_CAM_CAM_CONV_DATA_OUT_MODE_S) #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x00000001U #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 /** LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full + * Configure color range for input data. 0: limited color range. 1: full color range. */ #define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) #define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (LCD_CAM_CAM_CONV_DATA_IN_MODE_V << LCD_CAM_CAM_CONV_DATA_IN_MODE_S) #define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x00000001U #define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 /** LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. + * 0: 16-bit mode. 1: 8-bit mode. */ #define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (LCD_CAM_CAM_CONV_MODE_8BITS_ON_V << LCD_CAM_CAM_CONV_MODE_8BITS_ON_S) #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x00000001U #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 /** LCD_CAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. + * 0: converted to RGB format. 1: converted to YUV format. */ #define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) #define LCD_CAM_CAM_CONV_TRANS_MODE_M (LCD_CAM_CAM_CONV_TRANS_MODE_V << LCD_CAM_CAM_CONV_TRANS_MODE_S) @@ -325,11 +340,11 @@ extern "C" { #define LCD_CAM_CAM_CONV_BYPASS_S 31 /** LCD_CAM_LCD_RGB_YUV_REG register - * LCD configuration register + * LCD data format conversion register */ #define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10) /** LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. + * Swap every two 8-bit input data. 1: Enabled. 0: Disabled. */ #define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) #define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (LCD_CAM_LCD_CONV_8BITS_DATA_INV_V << LCD_CAM_LCD_CONV_8BITS_DATA_INV_S) @@ -342,52 +357,56 @@ extern "C" { #define LCD_CAM_LCD_CONV_TXTORX_M (LCD_CAM_LCD_CONV_TXTORX_V << LCD_CAM_LCD_CONV_TXTORX_S) #define LCD_CAM_LCD_CONV_TXTORX_V 0x00000001U #define LCD_CAM_LCD_CONV_TXTORX_S 21 -/** LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. +/** LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 0; + * In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to + * YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable + * YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1. */ #define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003U #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M (LCD_CAM_LCD_CONV_YUV2YUV_MODE_V << LCD_CAM_LCD_CONV_YUV2YUV_MODE_S) #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x00000003U #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 /** LCD_CAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in + * In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV + * mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 + * format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted + * to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to + * YUV411 format. */ #define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003U #define LCD_CAM_LCD_CONV_YUV_MODE_M (LCD_CAM_LCD_CONV_YUV_MODE_V << LCD_CAM_LCD_CONV_YUV_MODE_S) #define LCD_CAM_LCD_CONV_YUV_MODE_V 0x00000003U #define LCD_CAM_LCD_CONV_YUV_MODE_S 24 /** LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. + * 0: BT601. 1: BT709. */ #define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (LCD_CAM_LCD_CONV_PROTOCOL_MODE_V << LCD_CAM_LCD_CONV_PROTOCOL_MODE_S) #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x00000001U #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 /** LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full + * Configure color range for output data. 0: limited color range. 1: full color range. */ #define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (LCD_CAM_LCD_CONV_DATA_OUT_MODE_V << LCD_CAM_LCD_CONV_DATA_OUT_MODE_S) #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x00000001U #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 /** LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full + * Configure color range for input data. 0: limited color range. 1: full color range. */ #define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) #define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (LCD_CAM_LCD_CONV_DATA_IN_MODE_V << LCD_CAM_LCD_CONV_DATA_IN_MODE_S) #define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x00000001U #define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 /** LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. + * 0: 16-bit mode. 1: 8-bit mode. */ #define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (LCD_CAM_LCD_CONV_MODE_8BITS_ON_V << LCD_CAM_LCD_CONV_MODE_8BITS_ON_S) #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x00000001U #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 /** LCD_CAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. + * 0: converted to RGB format. 1: converted to YUV format. */ #define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) #define LCD_CAM_LCD_CONV_TRANS_MODE_M (LCD_CAM_LCD_CONV_TRANS_MODE_V << LCD_CAM_LCD_CONV_TRANS_MODE_S) @@ -402,56 +421,56 @@ extern "C" { #define LCD_CAM_LCD_CONV_BYPASS_S 31 /** LCD_CAM_LCD_USER_REG register - * LCD configuration register + * LCD user configuration register */ #define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14) -/** LCD_CAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1; - * The output data cycles minus 1 of LCD module. +/** LCD_CAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 0; + * Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1. */ #define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFFU #define LCD_CAM_LCD_DOUT_CYCLELEN_M (LCD_CAM_LCD_DOUT_CYCLELEN_V << LCD_CAM_LCD_DOUT_CYCLELEN_S) #define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x00001FFFU #define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 /** LCD_CAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0; - * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or - * reg_lcd_reset is set. + * LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is + * cleared or LCD_CAM_LCD_RESET is set. */ #define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) #define LCD_CAM_LCD_ALWAYS_OUT_EN_M (LCD_CAM_LCD_ALWAYS_OUT_EN_V << LCD_CAM_LCD_ALWAYS_OUT_EN_S) #define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x00000001U #define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 /** LCD_CAM_LCD_8BITS_ORDER : R/W; bitpos: [19]; default: 0; - * 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + * 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap. */ #define LCD_CAM_LCD_8BITS_ORDER (BIT(19)) #define LCD_CAM_LCD_8BITS_ORDER_M (LCD_CAM_LCD_8BITS_ORDER_V << LCD_CAM_LCD_8BITS_ORDER_S) #define LCD_CAM_LCD_8BITS_ORDER_V 0x00000001U #define LCD_CAM_LCD_8BITS_ORDER_S 19 -/** LCD_CAM_LCD_UPDATE_REG : R/W; bitpos: [20]; default: 0; - * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. +/** LCD_CAM_LCD_UPDATE : R/W; bitpos: [20]; default: 0; + * 1: Update LCD registers. This bit is cleared by hardware. 0: Do not care. */ -#define LCD_CAM_LCD_UPDATE_REG (BIT(20)) -#define LCD_CAM_LCD_UPDATE_REG_M (LCD_CAM_LCD_UPDATE_REG_V << LCD_CAM_LCD_UPDATE_REG_S) -#define LCD_CAM_LCD_UPDATE_REG_V 0x00000001U -#define LCD_CAM_LCD_UPDATE_REG_S 20 +#define LCD_CAM_LCD_UPDATE (BIT(20)) +#define LCD_CAM_LCD_UPDATE_M (LCD_CAM_LCD_UPDATE_V << LCD_CAM_LCD_UPDATE_S) +#define LCD_CAM_LCD_UPDATE_V 0x00000001U +#define LCD_CAM_LCD_UPDATE_S 20 /** LCD_CAM_LCD_BIT_ORDER : R/W; bitpos: [21]; default: 0; - * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + * 1: Change data bit order. Change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in 8-bit + * mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. */ #define LCD_CAM_LCD_BIT_ORDER (BIT(21)) #define LCD_CAM_LCD_BIT_ORDER_M (LCD_CAM_LCD_BIT_ORDER_V << LCD_CAM_LCD_BIT_ORDER_S) #define LCD_CAM_LCD_BIT_ORDER_V 0x00000001U #define LCD_CAM_LCD_BIT_ORDER_S 21 /** LCD_CAM_LCD_BYTE_ORDER : R/W; bitpos: [22]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + * 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert. */ #define LCD_CAM_LCD_BYTE_ORDER (BIT(22)) #define LCD_CAM_LCD_BYTE_ORDER_M (LCD_CAM_LCD_BYTE_ORDER_V << LCD_CAM_LCD_BYTE_ORDER_S) #define LCD_CAM_LCD_BYTE_ORDER_V 0x00000001U #define LCD_CAM_LCD_BYTE_ORDER_S 22 /** LCD_CAM_LCD_2BYTE_EN : R/W; bitpos: [23]; default: 0; - * 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data - * is 0~8. + * 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 + * bits. */ #define LCD_CAM_LCD_2BYTE_EN (BIT(23)) #define LCD_CAM_LCD_2BYTE_EN_M (LCD_CAM_LCD_2BYTE_EN_V << LCD_CAM_LCD_2BYTE_EN_S) @@ -479,28 +498,28 @@ extern "C" { #define LCD_CAM_LCD_CMD_V 0x00000001U #define LCD_CAM_LCD_CMD_S 26 /** LCD_CAM_LCD_START : R/W; bitpos: [27]; default: 0; - * LCD start sending data enable signal, valid in high level. + * LCD starts sending data enable signal, valid in high level. */ #define LCD_CAM_LCD_START (BIT(27)) #define LCD_CAM_LCD_START_M (LCD_CAM_LCD_START_V << LCD_CAM_LCD_START_S) #define LCD_CAM_LCD_START_V 0x00000001U #define LCD_CAM_LCD_START_S 27 /** LCD_CAM_LCD_RESET : WO; bitpos: [28]; default: 0; - * The value of command. + * Reset LCD module. */ #define LCD_CAM_LCD_RESET (BIT(28)) #define LCD_CAM_LCD_RESET_M (LCD_CAM_LCD_RESET_V << LCD_CAM_LCD_RESET_S) #define LCD_CAM_LCD_RESET_V 0x00000001U #define LCD_CAM_LCD_RESET_S 28 /** LCD_CAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0; - * The dummy cycle length minus 1. + * Configure DUMMY cycles. DUMMY cycles = this value + 1. */ #define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003U #define LCD_CAM_LCD_DUMMY_CYCLELEN_M (LCD_CAM_LCD_DUMMY_CYCLELEN_V << LCD_CAM_LCD_DUMMY_CYCLELEN_S) #define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x00000003U #define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 /** LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0; - * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */ #define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) #define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (LCD_CAM_LCD_CMD_2_CYCLE_EN_V << LCD_CAM_LCD_CMD_2_CYCLE_EN_S) @@ -508,26 +527,29 @@ extern "C" { #define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 /** LCD_CAM_LCD_MISC_REG register - * LCD configuration register + * LCD MISC configuration register */ #define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18) -/** LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W; bitpos: [5:1]; default: 11; - * The awfull threshold number of lcd_afifo. +/** LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W; bitpos: [5:1]; default: 17; + * Set the threshold for Async Tx FIFO full event. */ #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001FU #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V << LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S) #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x0000001FU #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1 -/** LCD_CAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3; - * The setup cycle length minus 1 in LCD non-RGB mode. +/** LCD_CAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 0; + * Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + * + 1. */ #define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003FU #define LCD_CAM_LCD_VFK_CYCLELEN_M (LCD_CAM_LCD_VFK_CYCLELEN_V << LCD_CAM_LCD_VFK_CYCLELEN_S) #define LCD_CAM_LCD_VFK_CYCLELEN_V 0x0000003FU #define LCD_CAM_LCD_VFK_CYCLELEN_S 6 /** LCD_CAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0; - * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - * time cycle length in LCD non-RGB mode. + * Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this + * value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, + * the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, + * the cycles = this value + 1. */ #define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFFU #define LCD_CAM_LCD_VBK_CYCLELEN_M (LCD_CAM_LCD_VBK_CYCLELEN_V << LCD_CAM_LCD_VBK_CYCLELEN_S) @@ -549,31 +571,31 @@ extern "C" { #define LCD_CAM_LCD_BK_EN_V 0x00000001U #define LCD_CAM_LCD_BK_EN_S 26 /** LCD_CAM_LCD_AFIFO_RESET : WO; bitpos: [27]; default: 0; - * LCD AFIFO reset signal. + * Async Tx FIFO reset signal. */ #define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) #define LCD_CAM_LCD_AFIFO_RESET_M (LCD_CAM_LCD_AFIFO_RESET_V << LCD_CAM_LCD_AFIFO_RESET_S) #define LCD_CAM_LCD_AFIFO_RESET_V 0x00000001U #define LCD_CAM_LCD_AFIFO_RESET_S 27 /** LCD_CAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ #define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) #define LCD_CAM_LCD_CD_DATA_SET_M (LCD_CAM_LCD_CD_DATA_SET_V << LCD_CAM_LCD_CD_DATA_SET_S) #define LCD_CAM_LCD_CD_DATA_SET_V 0x00000001U #define LCD_CAM_LCD_CD_DATA_SET_S 28 /** LCD_CAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ #define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) #define LCD_CAM_LCD_CD_DUMMY_SET_M (LCD_CAM_LCD_CD_DUMMY_SET_V << LCD_CAM_LCD_CD_DUMMY_SET_S) #define LCD_CAM_LCD_CD_DUMMY_SET_V 0x00000001U #define LCD_CAM_LCD_CD_DUMMY_SET_S 29 /** LCD_CAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ #define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) #define LCD_CAM_LCD_CD_CMD_SET_M (LCD_CAM_LCD_CD_CMD_SET_V << LCD_CAM_LCD_CD_CMD_SET_S) @@ -588,7 +610,7 @@ extern "C" { #define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 /** LCD_CAM_LCD_CTRL_REG register - * LCD configuration register + * LCD signal configuration register */ #define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1c) /** LCD_CAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; @@ -613,7 +635,7 @@ extern "C" { #define LCD_CAM_LCD_VT_HEIGHT_V 0x000003FFU #define LCD_CAM_LCD_VT_HEIGHT_S 21 /** LCD_CAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0; - * 1: Enable reg mode input vsync, hsync, de. 0: Disable. + * 1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable. */ #define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) #define LCD_CAM_LCD_RGB_MODE_EN_M (LCD_CAM_LCD_RGB_MODE_EN_V << LCD_CAM_LCD_RGB_MODE_EN_S) @@ -621,7 +643,7 @@ extern "C" { #define LCD_CAM_LCD_RGB_MODE_EN_S 31 /** LCD_CAM_LCD_CTRL1_REG register - * LCD configuration register + * LCD signal configuration register 1 */ #define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20) /** LCD_CAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; @@ -647,11 +669,11 @@ extern "C" { #define LCD_CAM_LCD_HT_WIDTH_S 20 /** LCD_CAM_LCD_CTRL2_REG register - * LCD configuration register + * LCD signal configuration register 2 */ #define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24) -/** LCD_CAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1; - * It is the position of LCD_VSYNC active pulse in a line. +/** LCD_CAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 0; + * It is the width of LCD_VSYNC active pulse in a line. */ #define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007FU #define LCD_CAM_LCD_VSYNC_WIDTH_M (LCD_CAM_LCD_VSYNC_WIDTH_V << LCD_CAM_LCD_VSYNC_WIDTH_S) @@ -672,15 +694,15 @@ extern "C" { #define LCD_CAM_LCD_DE_IDLE_POL_V 0x00000001U #define LCD_CAM_LCD_DE_IDLE_POL_S 8 /** LCD_CAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0; - * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC - * pulse is valid only in active region lines in RGB mode. + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: + * LCD_HSYNC pulse is valid only in active region lines in RGB mode. */ #define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) #define LCD_CAM_LCD_HS_BLANK_EN_M (LCD_CAM_LCD_HS_BLANK_EN_V << LCD_CAM_LCD_HS_BLANK_EN_S) #define LCD_CAM_LCD_HS_BLANK_EN_V 0x00000001U #define LCD_CAM_LCD_HS_BLANK_EN_S 9 -/** LCD_CAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1; - * It is the position of LCD_HSYNC active pulse in a line. +/** LCD_CAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 0; + * It is the width of LCD_HSYNC active pulse in a line. */ #define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007FU #define LCD_CAM_LCD_HSYNC_WIDTH_M (LCD_CAM_LCD_HSYNC_WIDTH_V << LCD_CAM_LCD_HSYNC_WIDTH_S) @@ -702,7 +724,7 @@ extern "C" { #define LCD_CAM_LCD_HSYNC_POSITION_S 24 /** LCD_CAM_LCD_CMD_VAL_REG register - * LCD configuration register + * LCD command value configuration register */ #define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28) /** LCD_CAM_LCD_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; @@ -714,36 +736,36 @@ extern "C" { #define LCD_CAM_LCD_CMD_VALUE_S 0 /** LCD_CAM_LCD_DLY_MODE_REG register - * LCD configuration register + * LCD signal delay configuration register */ #define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x30) /** LCD_CAM_LCD_CD_MODE : R/W; bitpos: [1:0]; default: 0; - * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: + * delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_LCD_CD_MODE 0x00000003U #define LCD_CAM_LCD_CD_MODE_M (LCD_CAM_LCD_CD_MODE_V << LCD_CAM_LCD_CD_MODE_S) #define LCD_CAM_LCD_CD_MODE_V 0x00000003U #define LCD_CAM_LCD_CD_MODE_S 0 /** LCD_CAM_LCD_DE_MODE : R/W; bitpos: [3:2]; default: 0; - * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: + * delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_LCD_DE_MODE 0x00000003U #define LCD_CAM_LCD_DE_MODE_M (LCD_CAM_LCD_DE_MODE_V << LCD_CAM_LCD_DE_MODE_S) #define LCD_CAM_LCD_DE_MODE_V 0x00000003U #define LCD_CAM_LCD_DE_MODE_S 2 /** LCD_CAM_LCD_HSYNC_MODE : R/W; bitpos: [5:4]; default: 0; - * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_LCD_HSYNC_MODE 0x00000003U #define LCD_CAM_LCD_HSYNC_MODE_M (LCD_CAM_LCD_HSYNC_MODE_V << LCD_CAM_LCD_HSYNC_MODE_S) #define LCD_CAM_LCD_HSYNC_MODE_V 0x00000003U #define LCD_CAM_LCD_HSYNC_MODE_S 4 /** LCD_CAM_LCD_VSYNC_MODE : R/W; bitpos: [7:6]; default: 0; - * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK. */ #define LCD_CAM_LCD_VSYNC_MODE 0x00000003U #define LCD_CAM_LCD_VSYNC_MODE_M (LCD_CAM_LCD_VSYNC_MODE_V << LCD_CAM_LCD_VSYNC_MODE_S) @@ -751,148 +773,132 @@ extern "C" { #define LCD_CAM_LCD_VSYNC_MODE_S 6 /** LCD_CAM_LCD_DATA_DOUT_MODE_REG register - * LCD configuration register + * LCD data delay configuration register */ #define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x38) /** LCD_CAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT0_MODE 0x00000003U #define LCD_CAM_DOUT0_MODE_M (LCD_CAM_DOUT0_MODE_V << LCD_CAM_DOUT0_MODE_S) #define LCD_CAM_DOUT0_MODE_V 0x00000003U #define LCD_CAM_DOUT0_MODE_S 0 /** LCD_CAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT1_MODE 0x00000003U #define LCD_CAM_DOUT1_MODE_M (LCD_CAM_DOUT1_MODE_V << LCD_CAM_DOUT1_MODE_S) #define LCD_CAM_DOUT1_MODE_V 0x00000003U #define LCD_CAM_DOUT1_MODE_S 2 /** LCD_CAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT2_MODE 0x00000003U #define LCD_CAM_DOUT2_MODE_M (LCD_CAM_DOUT2_MODE_V << LCD_CAM_DOUT2_MODE_S) #define LCD_CAM_DOUT2_MODE_V 0x00000003U #define LCD_CAM_DOUT2_MODE_S 4 /** LCD_CAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT3_MODE 0x00000003U #define LCD_CAM_DOUT3_MODE_M (LCD_CAM_DOUT3_MODE_V << LCD_CAM_DOUT3_MODE_S) #define LCD_CAM_DOUT3_MODE_V 0x00000003U #define LCD_CAM_DOUT3_MODE_S 6 /** LCD_CAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT4_MODE 0x00000003U #define LCD_CAM_DOUT4_MODE_M (LCD_CAM_DOUT4_MODE_V << LCD_CAM_DOUT4_MODE_S) #define LCD_CAM_DOUT4_MODE_V 0x00000003U #define LCD_CAM_DOUT4_MODE_S 8 /** LCD_CAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT5_MODE 0x00000003U #define LCD_CAM_DOUT5_MODE_M (LCD_CAM_DOUT5_MODE_V << LCD_CAM_DOUT5_MODE_S) #define LCD_CAM_DOUT5_MODE_V 0x00000003U #define LCD_CAM_DOUT5_MODE_S 10 /** LCD_CAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT6_MODE 0x00000003U #define LCD_CAM_DOUT6_MODE_M (LCD_CAM_DOUT6_MODE_V << LCD_CAM_DOUT6_MODE_S) #define LCD_CAM_DOUT6_MODE_V 0x00000003U #define LCD_CAM_DOUT6_MODE_S 12 /** LCD_CAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT7_MODE 0x00000003U #define LCD_CAM_DOUT7_MODE_M (LCD_CAM_DOUT7_MODE_V << LCD_CAM_DOUT7_MODE_S) #define LCD_CAM_DOUT7_MODE_V 0x00000003U #define LCD_CAM_DOUT7_MODE_S 14 /** LCD_CAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT8_MODE 0x00000003U #define LCD_CAM_DOUT8_MODE_M (LCD_CAM_DOUT8_MODE_V << LCD_CAM_DOUT8_MODE_S) #define LCD_CAM_DOUT8_MODE_V 0x00000003U #define LCD_CAM_DOUT8_MODE_S 16 /** LCD_CAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT9_MODE 0x00000003U #define LCD_CAM_DOUT9_MODE_M (LCD_CAM_DOUT9_MODE_V << LCD_CAM_DOUT9_MODE_S) #define LCD_CAM_DOUT9_MODE_V 0x00000003U #define LCD_CAM_DOUT9_MODE_S 18 /** LCD_CAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT10_MODE 0x00000003U #define LCD_CAM_DOUT10_MODE_M (LCD_CAM_DOUT10_MODE_V << LCD_CAM_DOUT10_MODE_S) #define LCD_CAM_DOUT10_MODE_V 0x00000003U #define LCD_CAM_DOUT10_MODE_S 20 /** LCD_CAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT11_MODE 0x00000003U #define LCD_CAM_DOUT11_MODE_M (LCD_CAM_DOUT11_MODE_V << LCD_CAM_DOUT11_MODE_S) #define LCD_CAM_DOUT11_MODE_V 0x00000003U #define LCD_CAM_DOUT11_MODE_S 22 /** LCD_CAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT12_MODE 0x00000003U #define LCD_CAM_DOUT12_MODE_M (LCD_CAM_DOUT12_MODE_V << LCD_CAM_DOUT12_MODE_S) #define LCD_CAM_DOUT12_MODE_V 0x00000003U #define LCD_CAM_DOUT12_MODE_S 24 /** LCD_CAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT13_MODE 0x00000003U #define LCD_CAM_DOUT13_MODE_M (LCD_CAM_DOUT13_MODE_V << LCD_CAM_DOUT13_MODE_S) #define LCD_CAM_DOUT13_MODE_V 0x00000003U #define LCD_CAM_DOUT13_MODE_S 26 /** LCD_CAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT14_MODE 0x00000003U #define LCD_CAM_DOUT14_MODE_M (LCD_CAM_DOUT14_MODE_V << LCD_CAM_DOUT14_MODE_S) #define LCD_CAM_DOUT14_MODE_V 0x00000003U #define LCD_CAM_DOUT14_MODE_S 28 /** LCD_CAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ #define LCD_CAM_DOUT15_MODE 0x00000003U #define LCD_CAM_DOUT15_MODE_M (LCD_CAM_DOUT15_MODE_V << LCD_CAM_DOUT15_MODE_S) @@ -900,32 +906,32 @@ extern "C" { #define LCD_CAM_DOUT15_MODE_S 30 /** LCD_CAM_LC_DMA_INT_ENA_REG register - * LCD_camera DMA inturrupt enable register + * LCD_CAM GDMA interrupt enable register */ #define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64) /** LCD_CAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable bit for LCD frame end interrupt. + * The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ #define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) #define LCD_CAM_LCD_VSYNC_INT_ENA_M (LCD_CAM_LCD_VSYNC_INT_ENA_V << LCD_CAM_LCD_VSYNC_INT_ENA_S) #define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x00000001U #define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 /** LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable bit for lcd transfer end interrupt. + * The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ #define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (LCD_CAM_LCD_TRANS_DONE_INT_ENA_V << LCD_CAM_LCD_TRANS_DONE_INT_ENA_S) #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x00000001U #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 /** LCD_CAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0; - * The enable bit for Camera frame end interrupt. + * The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ #define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) #define LCD_CAM_CAM_VSYNC_INT_ENA_M (LCD_CAM_CAM_VSYNC_INT_ENA_V << LCD_CAM_CAM_VSYNC_INT_ENA_S) #define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x00000001U #define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 /** LCD_CAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for Camera line interrupt. + * The enable bit for LCD_CAM_CAM_HS_INT interrupt. */ #define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) #define LCD_CAM_CAM_HS_INT_ENA_M (LCD_CAM_CAM_HS_INT_ENA_V << LCD_CAM_CAM_HS_INT_ENA_S) @@ -933,32 +939,32 @@ extern "C" { #define LCD_CAM_CAM_HS_INT_ENA_S 3 /** LCD_CAM_LC_DMA_INT_RAW_REG register - * LCD_camera DMA raw inturrupt status register + * LCD_CAM GDMA raw interrupt status register */ #define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68) /** LCD_CAM_LCD_VSYNC_INT_RAW : RO; bitpos: [0]; default: 0; - * The raw bit for LCD frame end interrupt. + * The raw bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ #define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) #define LCD_CAM_LCD_VSYNC_INT_RAW_M (LCD_CAM_LCD_VSYNC_INT_RAW_V << LCD_CAM_LCD_VSYNC_INT_RAW_S) #define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x00000001U #define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 /** LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO; bitpos: [1]; default: 0; - * The raw bit for lcd transfer end interrupt. + * The raw bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ #define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (LCD_CAM_LCD_TRANS_DONE_INT_RAW_V << LCD_CAM_LCD_TRANS_DONE_INT_RAW_S) #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x00000001U #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 /** LCD_CAM_CAM_VSYNC_INT_RAW : RO; bitpos: [2]; default: 0; - * The raw bit for Camera frame end interrupt. + * The raw bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ #define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) #define LCD_CAM_CAM_VSYNC_INT_RAW_M (LCD_CAM_CAM_VSYNC_INT_RAW_V << LCD_CAM_CAM_VSYNC_INT_RAW_S) #define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x00000001U #define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 /** LCD_CAM_CAM_HS_INT_RAW : RO; bitpos: [3]; default: 0; - * The raw bit for Camera line interrupt. + * The raw bit for LCD_CAM_CAM_HS_INT interrupt. */ #define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) #define LCD_CAM_CAM_HS_INT_RAW_M (LCD_CAM_CAM_HS_INT_RAW_V << LCD_CAM_CAM_HS_INT_RAW_S) @@ -966,32 +972,32 @@ extern "C" { #define LCD_CAM_CAM_HS_INT_RAW_S 3 /** LCD_CAM_LC_DMA_INT_ST_REG register - * LCD_camera DMA masked inturrupt status register + * LCD_CAM GDMA masked interrupt status register */ #define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6c) /** LCD_CAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0; - * The status bit for LCD frame end interrupt. + * The status bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ #define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) #define LCD_CAM_LCD_VSYNC_INT_ST_M (LCD_CAM_LCD_VSYNC_INT_ST_V << LCD_CAM_LCD_VSYNC_INT_ST_S) #define LCD_CAM_LCD_VSYNC_INT_ST_V 0x00000001U #define LCD_CAM_LCD_VSYNC_INT_ST_S 0 /** LCD_CAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status bit for lcd transfer end interrupt. + * The status bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ #define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) #define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (LCD_CAM_LCD_TRANS_DONE_INT_ST_V << LCD_CAM_LCD_TRANS_DONE_INT_ST_S) #define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x00000001U #define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 /** LCD_CAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0; - * The status bit for Camera frame end interrupt. + * The status bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ #define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) #define LCD_CAM_CAM_VSYNC_INT_ST_M (LCD_CAM_CAM_VSYNC_INT_ST_V << LCD_CAM_CAM_VSYNC_INT_ST_S) #define LCD_CAM_CAM_VSYNC_INT_ST_V 0x00000001U #define LCD_CAM_CAM_VSYNC_INT_ST_S 2 /** LCD_CAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for Camera transfer end interrupt. + * The status bit for LCD_CAM_CAM_HS_INT interrupt. */ #define LCD_CAM_CAM_HS_INT_ST (BIT(3)) #define LCD_CAM_CAM_HS_INT_ST_M (LCD_CAM_CAM_HS_INT_ST_V << LCD_CAM_CAM_HS_INT_ST_S) @@ -999,32 +1005,32 @@ extern "C" { #define LCD_CAM_CAM_HS_INT_ST_S 3 /** LCD_CAM_LC_DMA_INT_CLR_REG register - * LCD_camera DMA inturrupt clear register + * LCD_CAM GDMA interrupt clear register */ #define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70) /** LCD_CAM_LCD_VSYNC_INT_CLR : WO; bitpos: [0]; default: 0; - * The clear bit for LCD frame end interrupt. + * The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ #define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) #define LCD_CAM_LCD_VSYNC_INT_CLR_M (LCD_CAM_LCD_VSYNC_INT_CLR_V << LCD_CAM_LCD_VSYNC_INT_CLR_S) #define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x00000001U #define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 /** LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO; bitpos: [1]; default: 0; - * The clear bit for lcd transfer end interrupt. + * The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ #define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (LCD_CAM_LCD_TRANS_DONE_INT_CLR_V << LCD_CAM_LCD_TRANS_DONE_INT_CLR_S) #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x00000001U #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 /** LCD_CAM_CAM_VSYNC_INT_CLR : WO; bitpos: [2]; default: 0; - * The clear bit for Camera frame end interrupt. + * The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ #define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) #define LCD_CAM_CAM_VSYNC_INT_CLR_M (LCD_CAM_CAM_VSYNC_INT_CLR_V << LCD_CAM_CAM_VSYNC_INT_CLR_S) #define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x00000001U #define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 /** LCD_CAM_CAM_HS_INT_CLR : WO; bitpos: [3]; default: 0; - * The clear bit for Camera line interrupt. + * The clear bit for LCD_CAM_CAM_HS_INT interrupt. */ #define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) #define LCD_CAM_CAM_HS_INT_CLR_M (LCD_CAM_CAM_HS_INT_CLR_V << LCD_CAM_CAM_HS_INT_CLR_S) @@ -1032,11 +1038,11 @@ extern "C" { #define LCD_CAM_CAM_HS_INT_CLR_S 3 /** LCD_CAM_LC_REG_DATE_REG register - * Version register + * Version control register */ #define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xfc) /** LCD_CAM_LC_DATE : R/W; bitpos: [27:0]; default: 33566752; - * LCD_CAM version control register + * Version control register */ #define LCD_CAM_LC_DATE 0x0FFFFFFFU #define LCD_CAM_LC_DATE_M (LCD_CAM_LC_DATE_V << LCD_CAM_LC_DATE_S) diff --git a/components/soc/esp32s3/include/soc/lcd_cam_struct.h b/components/soc/esp32s3/include/soc/lcd_cam_struct.h index acb1d499c3..7d673a90ed 100644 --- a/components/soc/esp32s3/include/soc/lcd_cam_struct.h +++ b/components/soc/esp32s3/include/soc/lcd_cam_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,47 +10,53 @@ extern "C" { #endif -/** Group: LCD Configuration Register */ +/** Group: LCD configuration registers */ /** Type of lcd_clock register - * LCD clock register + * LCD clock configuration register */ typedef union { struct { - /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; - * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 0; + * fLCD_PCLK + * = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is + * 0. Note: this field must not be configured to 0. */ uint32_t lcd_clkcnt_n: 6; - /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; - * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 0; + * 1: fLCD_PCLK + * = fLCD_CLK. 0: fLCD_PCLK + * = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1). */ uint32_t lcd_clk_equ_sysclk: 1; /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; - * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + * 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle. */ uint32_t lcd_ck_idle_edge: 1; /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; - * 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock - * cycle. + * 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first + * half clock cycle. */ uint32_t lcd_ck_out_edge: 1; - /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral LCD clock divider value + /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 0; + * Integral LCD clock divider value. */ uint32_t lcd_clkm_div_num: 8; /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value + * Fractional clock divider numerator value. */ uint32_t lcd_clkm_div_b: 6; /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value + * Fractional clock divider denominator value. */ uint32_t lcd_clkm_div_a: 6; /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + * Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: + * PLL_D2_CLK. 3: PLL_F160M_CLK. */ uint32_t lcd_clk_sel: 2; /** clk_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable clk gate + * Set this bit to force enable the clock for all configuration registers. Clock gate + * is not used. */ uint32_t clk_en: 1; }; @@ -58,47 +64,51 @@ typedef union { } lcd_cam_lcd_clock_reg_t; /** Type of lcd_rgb_yuv register - * LCD configuration register + * LCD data format conversion register */ typedef union { struct { uint32_t reserved_0: 20; /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. + * Swap every two 8-bit input data. 1: Enabled. 0: Disabled. */ uint32_t lcd_conv_8bits_data_inv: 1; /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; * 0: txtorx mode off. 1: txtorx mode on. */ uint32_t lcd_conv_txtorx: 1; - /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. + /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 0; + * In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to + * YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable + * YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1. */ uint32_t lcd_conv_yuv2yuv_mode: 2; /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in + * In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV + * mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 + * format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted + * to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to + * YUV411 format. */ uint32_t lcd_conv_yuv_mode: 2; /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. + * 0: BT601. 1: BT709. */ uint32_t lcd_conv_protocol_mode: 1; /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full + * Configure color range for output data. 0: limited color range. 1: full color range. */ uint32_t lcd_conv_data_out_mode: 1; /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full + * Configure color range for input data. 0: limited color range. 1: full color range. */ uint32_t lcd_conv_data_in_mode: 1; /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. + * 0: 16-bit mode. 1: 8-bit mode. */ uint32_t lcd_conv_mode_8bits_on: 1; /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. + * 0: converted to RGB format. 1: converted to YUV format. */ uint32_t lcd_conv_trans_mode: 1; /** lcd_conv_bypass : R/W; bitpos: [31]; default: 0; @@ -110,40 +120,40 @@ typedef union { } lcd_cam_lcd_rgb_yuv_reg_t; /** Type of lcd_user register - * LCD configuration register + * LCD user configuration register */ typedef union { struct { - /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; - * The output data cycles minus 1 of LCD module. + /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 0; + * Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1. */ uint32_t lcd_dout_cyclelen: 13; /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; - * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or - * reg_lcd_reset is set. + * LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is + * cleared or LCD_CAM_LCD_RESET is set. */ uint32_t lcd_always_out_en: 1; uint32_t reserved_14: 5; /** lcd_8bits_order : R/W; bitpos: [19]; default: 0; - * 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + * 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap. */ uint32_t lcd_8bits_order: 1; - /** lcd_update_reg : R/W; bitpos: [20]; default: 0; - * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + /** lcd_update : R/W; bitpos: [20]; default: 0; + * 1: Update LCD registers. This bit is cleared by hardware. 0: Do not care. */ uint32_t lcd_update: 1; /** lcd_bit_order : R/W; bitpos: [21]; default: 0; - * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + * 1: Change data bit order. Change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in 8-bit + * mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. */ uint32_t lcd_bit_order: 1; /** lcd_byte_order : R/W; bitpos: [22]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + * 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert. */ uint32_t lcd_byte_order: 1; /** lcd_2byte_en : R/W; bitpos: [23]; default: 0; - * 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data - * is 0~8. + * 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 + * bits. */ uint32_t lcd_2byte_en: 1; /** lcd_dout : R/W; bitpos: [24]; default: 0; @@ -159,19 +169,19 @@ typedef union { */ uint32_t lcd_cmd: 1; /** lcd_start : R/W; bitpos: [27]; default: 0; - * LCD start sending data enable signal, valid in high level. + * LCD starts sending data enable signal, valid in high level. */ uint32_t lcd_start: 1; /** lcd_reset : WO; bitpos: [28]; default: 0; - * The value of command. + * Reset LCD module. */ uint32_t lcd_reset: 1; /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; - * The dummy cycle length minus 1. + * Configure DUMMY cycles. DUMMY cycles = this value + 1. */ uint32_t lcd_dummy_cyclelen: 2; /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; - * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */ uint32_t lcd_cmd_2_cycle_en: 1; }; @@ -179,22 +189,25 @@ typedef union { } lcd_cam_lcd_user_reg_t; /** Type of lcd_misc register - * LCD configuration register + * LCD MISC configuration register */ typedef union { struct { uint32_t reserved_0: 1; - /** lcd_afifo_threshold_num : R/W; bitpos: [5:1]; default: 11; - * The awfull threshold number of lcd_afifo. + /** lcd_afifo_threshold_num : R/W; bitpos: [5:1]; default: 17; + * Set the threshold for Async Tx FIFO full event. */ uint32_t lcd_afifo_threshold_num: 5; - /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; - * The setup cycle length minus 1 in LCD non-RGB mode. + /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 0; + * Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + * + 1. */ uint32_t lcd_vfk_cyclelen: 6; /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; - * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - * time cycle length in LCD non-RGB mode. + * Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this + * value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, + * the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, + * the cycles = this value + 1. */ uint32_t lcd_vbk_cyclelen: 13; /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; @@ -207,22 +220,22 @@ typedef union { */ uint32_t lcd_bk_en: 1; /** lcd_afifo_reset : WO; bitpos: [27]; default: 0; - * LCD AFIFO reset signal. + * Async Tx FIFO reset signal. */ uint32_t lcd_afifo_reset: 1; /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ uint32_t lcd_cd_data_set: 1; /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ uint32_t lcd_cd_dummy_set: 1; /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - * reg_cd_idle_edge. + * 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = + * LCD_CAM_LCD_CD_IDLE_EDGE. */ uint32_t lcd_cd_cmd_set: 1; /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; @@ -234,7 +247,7 @@ typedef union { } lcd_cam_lcd_misc_reg_t; /** Type of lcd_ctrl register - * LCD configuration register + * LCD signal configuration register */ typedef union { struct { @@ -251,7 +264,7 @@ typedef union { */ uint32_t lcd_vt_height: 10; /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; - * 1: Enable reg mode input vsync, hsync, de. 0: Disable. + * 1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable. */ uint32_t lcd_rgb_mode_en: 1; }; @@ -259,7 +272,7 @@ typedef union { } lcd_cam_lcd_ctrl_reg_t; /** Type of lcd_ctrl1 register - * LCD configuration register + * LCD signal configuration register 1 */ typedef union { struct { @@ -280,12 +293,12 @@ typedef union { } lcd_cam_lcd_ctrl1_reg_t; /** Type of lcd_ctrl2 register - * LCD configuration register + * LCD signal configuration register 2 */ typedef union { struct { - /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; - * It is the position of LCD_VSYNC active pulse in a line. + /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 0; + * It is the width of LCD_VSYNC active pulse in a line. */ uint32_t lcd_vsync_width: 7; /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; @@ -297,13 +310,13 @@ typedef union { */ uint32_t lcd_de_idle_pol: 1; /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; - * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC - * pulse is valid only in active region lines in RGB mode. + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: + * LCD_HSYNC pulse is valid only in active region lines in RGB mode. */ uint32_t lcd_hs_blank_en: 1; uint32_t reserved_10: 6; - /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; - * It is the position of LCD_HSYNC active pulse in a line. + /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 0; + * It is the width of LCD_HSYNC active pulse in a line. */ uint32_t lcd_hsync_width: 7; /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; @@ -319,7 +332,7 @@ typedef union { } lcd_cam_lcd_ctrl2_reg_t; /** Type of lcd_cmd_val register - * LCD configuration register + * LCD command value configuration register */ typedef union { struct { @@ -332,28 +345,28 @@ typedef union { } lcd_cam_lcd_cmd_val_reg_t; /** Type of lcd_dly_mode register - * LCD configuration register + * LCD signal delay configuration register */ typedef union { struct { /** lcd_cd_mode : R/W; bitpos: [1:0]; default: 0; - * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: + * delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t lcd_cd_mode: 2; /** lcd_de_mode : R/W; bitpos: [3:2]; default: 0; - * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: + * delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t lcd_de_mode: 2; /** lcd_hsync_mode : R/W; bitpos: [5:4]; default: 0; - * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t lcd_hsync_mode: 2; /** lcd_vsync_mode : R/W; bitpos: [7:6]; default: 0; - * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK. */ uint32_t lcd_vsync_mode: 2; uint32_t reserved_8: 24; @@ -362,104 +375,88 @@ typedef union { } lcd_cam_lcd_dly_mode_reg_t; /** Type of lcd_data_dout_mode register - * LCD configuration register + * LCD data delay configuration register */ typedef union { struct { /** dout0_mode : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout0_mode: 2; /** dout1_mode : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout1_mode: 2; /** dout2_mode : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout2_mode: 2; /** dout3_mode : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout3_mode: 2; /** dout4_mode : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout4_mode: 2; /** dout5_mode : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout5_mode: 2; /** dout6_mode : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout6_mode: 2; /** dout7_mode : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout7_mode: 2; /** dout8_mode : R/W; bitpos: [17:16]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout8_mode: 2; /** dout9_mode : R/W; bitpos: [19:18]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout9_mode: 2; /** dout10_mode : R/W; bitpos: [21:20]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout10_mode: 2; /** dout11_mode : R/W; bitpos: [23:22]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout11_mode: 2; /** dout12_mode : R/W; bitpos: [25:24]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout12_mode: 2; /** dout13_mode : R/W; bitpos: [27:26]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout13_mode: 2; /** dout14_mode : R/W; bitpos: [29:28]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout14_mode: 2; /** dout15_mode : R/W; bitpos: [31:30]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. + * The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. + * 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK. */ uint32_t dout15_mode: 2; }; @@ -467,56 +464,58 @@ typedef union { } lcd_cam_lcd_data_dout_mode_reg_t; -/** Group: Camera Configuration Register */ +/** Group: Camera configuration registers */ /** Type of cam_ctrl register - * Camera configuration register + * Camera clock configuration register */ typedef union { struct { /** cam_stop_en : R/W; bitpos: [0]; default: 0; - * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + * Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not + * stop. */ uint32_t cam_stop_en: 1; /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; * Filter threshold value for CAM_VSYNC signal. */ uint32_t cam_vsync_filter_thres: 3; - /** cam_update_reg : R/W; bitpos: [4]; default: 0; - * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + /** cam_update : R/W; bitpos: [4]; default: 0; + * 1: Update camera registers. This bit is cleared by hardware. 0: Do not care. */ uint32_t cam_update: 1; /** cam_byte_order : R/W; bitpos: [5]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + * 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change. */ uint32_t cam_byte_order: 1; /** cam_bit_order : R/W; bitpos: [6]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit + * mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change. */ uint32_t cam_bit_order: 1; /** cam_line_int_en : R/W; bitpos: [7]; default: 0; - * 1: Enable to generate CAM_HS_INT. 0: Disable. + * 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable. */ uint32_t cam_line_int_en: 1; /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; - * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by - * reg_cam_rec_data_cyclelen. + * 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * LCD_CAM_CAM_REC_DATA_BYTELEN. */ uint32_t cam_vs_eof_en: 1; - /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral Camera clock divider value + /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 0; + * Integral camera clock divider value. */ uint32_t cam_clkm_div_num: 8; /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value + * Fractional clock divider numerator value. */ uint32_t cam_clkm_div_b: 6; /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value + * Fractional clock divider denominator value. */ uint32_t cam_clkm_div_a: 6; /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + * Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: + * PLL_D2_CLK. 3: PLL_F160M_CLK. */ uint32_t cam_clk_sel: 2; uint32_t reserved_31: 1; @@ -525,28 +524,30 @@ typedef union { } lcd_cam_cam_ctrl_reg_t; /** Type of cam_ctrl1 register - * Camera configuration register + * Camera control register */ typedef union { struct { /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; - * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + * Configure camera received data byte length. When the length of received data + * reaches this value + 1, GDMA in_suc_eof_int is triggered. */ uint32_t cam_rec_data_bytelen: 16; /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; - * The line number minus 1 to generate cam_hs_int. + * Configure line number. When the number of received lines reaches this value + 1, + * LCD_CAM_CAM_HS_INT is triggered. */ uint32_t cam_line_int_num: 6; /** cam_clk_inv : R/W; bitpos: [22]; default: 0; - * 1: Invert the input signal CAM_PCLK. 0: Not invert. + * 1: Invert the input signal CAM_PCLK. 0: Do not invert. */ uint32_t cam_clk_inv: 1; /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; - * 1: Enable CAM_VSYNC filter function. 0: bypass. + * 1: Enable CAM_VSYNC filter function. 0: Bypass. */ uint32_t cam_vsync_filter_en: 1; /** cam_2byte_en : R/W; bitpos: [24]; default: 0; - * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + * 1: The width of input data is 16 bits. 0: The width of input data is 8 bits. */ uint32_t cam_2byte_en: 1; /** cam_de_inv : R/W; bitpos: [25]; default: 0; @@ -562,8 +563,9 @@ typedef union { */ uint32_t cam_vsync_inv: 1; /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; - * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control - * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + * 1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control + * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same + * time. */ uint32_t cam_vh_de_mode_en: 1; /** cam_start : R/W; bitpos: [29]; default: 0; @@ -575,7 +577,7 @@ typedef union { */ uint32_t cam_reset: 1; /** cam_afifo_reset : WO; bitpos: [31]; default: 0; - * Camera AFIFO reset signal. + * Camera Async Rx FIFO reset signal. */ uint32_t cam_afifo_reset: 1; }; @@ -583,43 +585,47 @@ typedef union { } lcd_cam_cam_ctrl1_reg_t; /** Type of cam_rgb_yuv register - * Camera configuration register + * Camera data format conversion register */ typedef union { struct { uint32_t reserved_0: 21; /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. + * Swap every two 8-bit input data. 1: Enabled. 0: Disabled. */ uint32_t cam_conv_8bits_data_inv: 1; - /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. + /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 0; + * In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to + * YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable + * YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1. */ uint32_t cam_conv_yuv2yuv_mode: 2; /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in + * In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV + * mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 + * format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted + * to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to + * YUV411 format. */ uint32_t cam_conv_yuv_mode: 2; /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. + * 0: BT601. 1: BT709. */ uint32_t cam_conv_protocol_mode: 1; /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full + * Configure color range for output data. 0: limited color range. 1: full color range. */ uint32_t cam_conv_data_out_mode: 1; /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full + * Configure color range for input data. 0: limited color range. 1: full color range. */ uint32_t cam_conv_data_in_mode: 1; /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. + * 0: 16-bit mode. 1: 8-bit mode. */ uint32_t cam_conv_mode_8bits_on: 1; /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. + * 0: converted to RGB format. 1: converted to YUV format. */ uint32_t cam_conv_trans_mode: 1; /** cam_conv_bypass : R/W; bitpos: [31]; default: 0; @@ -631,26 +637,26 @@ typedef union { } lcd_cam_cam_rgb_yuv_reg_t; -/** Group: Interrupt Register */ +/** Group: Interrupt registers */ /** Type of lc_dma_int_ena register - * LCD_camera DMA inturrupt enable register + * LCD_CAM GDMA interrupt enable register */ typedef union { struct { /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; - * The enable bit for LCD frame end interrupt. + * The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ uint32_t lcd_vsync_int_ena: 1; /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable bit for lcd transfer end interrupt. + * The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ uint32_t lcd_trans_done_int_ena: 1; /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; - * The enable bit for Camera frame end interrupt. + * The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ uint32_t cam_vsync_int_ena: 1; /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for Camera line interrupt. + * The enable bit for LCD_CAM_CAM_HS_INT interrupt. */ uint32_t cam_hs_int_ena: 1; uint32_t reserved_4: 28; @@ -659,24 +665,24 @@ typedef union { } lcd_cam_lc_dma_int_ena_reg_t; /** Type of lc_dma_int_raw register - * LCD_camera DMA raw inturrupt status register + * LCD_CAM GDMA raw interrupt status register */ typedef union { struct { /** lcd_vsync_int_raw : RO; bitpos: [0]; default: 0; - * The raw bit for LCD frame end interrupt. + * The raw bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ uint32_t lcd_vsync_int_raw: 1; /** lcd_trans_done_int_raw : RO; bitpos: [1]; default: 0; - * The raw bit for lcd transfer end interrupt. + * The raw bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ uint32_t lcd_trans_done_int_raw: 1; /** cam_vsync_int_raw : RO; bitpos: [2]; default: 0; - * The raw bit for Camera frame end interrupt. + * The raw bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ uint32_t cam_vsync_int_raw: 1; /** cam_hs_int_raw : RO; bitpos: [3]; default: 0; - * The raw bit for Camera line interrupt. + * The raw bit for LCD_CAM_CAM_HS_INT interrupt. */ uint32_t cam_hs_int_raw: 1; uint32_t reserved_4: 28; @@ -685,24 +691,24 @@ typedef union { } lcd_cam_lc_dma_int_raw_reg_t; /** Type of lc_dma_int_st register - * LCD_camera DMA masked inturrupt status register + * LCD_CAM GDMA masked interrupt status register */ typedef union { struct { /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; - * The status bit for LCD frame end interrupt. + * The status bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ uint32_t lcd_vsync_int_st: 1; /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; - * The status bit for lcd transfer end interrupt. + * The status bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ uint32_t lcd_trans_done_int_st: 1; /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; - * The status bit for Camera frame end interrupt. + * The status bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ uint32_t cam_vsync_int_st: 1; /** cam_hs_int_st : RO; bitpos: [3]; default: 0; - * The status bit for Camera transfer end interrupt. + * The status bit for LCD_CAM_CAM_HS_INT interrupt. */ uint32_t cam_hs_int_st: 1; uint32_t reserved_4: 28; @@ -711,24 +717,24 @@ typedef union { } lcd_cam_lc_dma_int_st_reg_t; /** Type of lc_dma_int_clr register - * LCD_camera DMA inturrupt clear register + * LCD_CAM GDMA interrupt clear register */ typedef union { struct { /** lcd_vsync_int_clr : WO; bitpos: [0]; default: 0; - * The clear bit for LCD frame end interrupt. + * The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt. */ uint32_t lcd_vsync_int_clr: 1; /** lcd_trans_done_int_clr : WO; bitpos: [1]; default: 0; - * The clear bit for lcd transfer end interrupt. + * The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. */ uint32_t lcd_trans_done_int_clr: 1; /** cam_vsync_int_clr : WO; bitpos: [2]; default: 0; - * The clear bit for Camera frame end interrupt. + * The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt. */ uint32_t cam_vsync_int_clr: 1; /** cam_hs_int_clr : WO; bitpos: [3]; default: 0; - * The clear bit for Camera line interrupt. + * The clear bit for LCD_CAM_CAM_HS_INT interrupt. */ uint32_t cam_hs_int_clr: 1; uint32_t reserved_4: 28; @@ -737,14 +743,14 @@ typedef union { } lcd_cam_lc_dma_int_clr_reg_t; -/** Group: Version Register */ +/** Group: Version register */ /** Type of lc_reg_date register - * Version register + * Version control register */ typedef union { struct { /** lc_date : R/W; bitpos: [27:0]; default: 33566752; - * LCD_CAM version control register + * Version control register */ uint32_t lc_date: 28; uint32_t reserved_28: 4;