mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feature/bringup_psram_c5' into 'master'
feat(spiram): psram support on esp32c5 Closes IDF-8690 See merge request espressif/esp-idf!31393
This commit is contained in:
C.S.M
commit
fabf68803d
@ -28,6 +28,7 @@
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#include "hal/mmu_ll.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "hal/mspi_timing_tuning_ll.h"
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void bootloader_flash_update_id()
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{
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@ -203,6 +204,12 @@ static void bootloader_spi_flash_resume(void)
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esp_err_t bootloader_init_spi_flash(void)
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{
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// Set source mspi pll clock as 80M in bootloader stage.
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// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
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// in this stage, set divider as 6
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mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
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mspi_ll_fast_set_hs_divider(6);
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bootloader_init_flash_configure();
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bootloader_spi_flash_resume();
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bootloader_flash_unlock();
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@ -3,6 +3,6 @@
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components/esp_common/test_apps/esp_common:
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disable:
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- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
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- if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32p4"]
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- if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32p4", "esp32c5"]
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temporary: true
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reason: esp32p4 is not supported yet # TODO: IDF-7557
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reason: esp32p4/c5 is not supported yet # TODO: IDF-7557
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48
components/esp_psram/esp32c5/Kconfig.spiram
Normal file
48
components/esp_psram/esp32c5/Kconfig.spiram
Normal file
@ -0,0 +1,48 @@
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config SPIRAM
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bool "Support for external, SPI-connected RAM"
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default "n"
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help
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This enables support for an external SPI RAM chip, connected in parallel with the
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main SPI flash chip.
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menu "SPI RAM config"
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depends on SPIRAM
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choice SPIRAM_MODE
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prompt "Mode of SPI RAM chip in use"
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default SPIRAM_MODE_QUAD
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config SPIRAM_MODE_QUAD
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bool "Quad Mode PSRAM"
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endchoice
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config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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bool "Allow external memory as an argument to xTaskCreateStatic"
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default y
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help
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Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate
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are by default allocated from internal RAM.
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This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
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This should only be used for tasks where the stack is never accessed while the cache is disabled.
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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config SPIRAM_SPEED_80M
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bool "80MHz clock speed"
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config SPIRAM_SPEED_40M
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bool "40Mhz clock speed"
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endchoice
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config SPIRAM_SPEED
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int
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default 80 if SPIRAM_SPEED_80M
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default 40 if SPIRAM_SPEED_40M
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source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here
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endmenu
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411
components/esp_psram/esp32c5/esp_psram_impl_quad.c
Normal file
411
components/esp_psram/esp32c5/esp_psram_impl_quad.c
Normal file
@ -0,0 +1,411 @@
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/*
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* SPDX-FileCopyrightText: 2013-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_bit_defs.h"
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#include "esp_log.h"
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#include "../esp_psram_impl.h"
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#include "esp32c5/rom/spi_flash.h"
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#include "esp32c5/rom/opi_flash.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "hal/gpio_hal.h"
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#include "esp_private/esp_gpio_reserve.h"
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#include "soc/spi1_mem_reg.h"
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#include "soc/spi_mem_reg.h"
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static const char* TAG = "quad_psram";
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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#define PSRAM_FAST_READ_DUMMY 4
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#define PSRAM_FAST_READ_QUAD_DUMMY 6
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// ID
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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#define PSRAM_ID_EID_M 0xff
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#define PSRAM_ID_EID_S 16
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// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
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//
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// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_EID_SIZE_M 0x07
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#define PSRAM_EID_SIZE_S 5
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#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
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#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
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#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
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#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
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#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
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#define PSRAM_IS_2T_APS3204(id) ((((id) >> 21) && 0xfffff) == 1)
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// IO-pins for PSRAM.
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
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#define FLASH_CS_IO SPI_CS0_GPIO_NUM
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// PSRAM clock and cs IO should be configured based on hardware design.
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#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
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#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
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#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
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#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
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#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
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#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
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#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
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#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
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#define SPI1_NUM 1
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#define SPI0_NUM 0
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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typedef esp_rom_spi_cmd_t psram_cmd_t;
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static uint32_t s_psram_id = 0;
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static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
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static void config_psram_spi_phases(void);
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extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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static uint8_t s_psram_cs_io = (uint8_t) -1;
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uint8_t esp_psram_impl_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
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{
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if (mode == PSRAM_CMD_QPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
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SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
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} else if (mode == PSRAM_CMD_SPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
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}
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}
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static void _psram_exec_cmd(int spi_num,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len)
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{
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esp_rom_spi_cmd_t conf;
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uint32_t _addr = addr;
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conf.addr = &_addr;
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conf.addrBitLen = addr_bit_len;
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conf.cmd = cmd;
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conf.cmdBitLen = cmd_bit_len;
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conf.dummyBitLen = dummy_bits;
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conf.txData = (uint32_t*) mosi_data;
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conf.txDataBitLen = mosi_bit_len;
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conf.rxData = (uint32_t*) miso_data;
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conf.rxDataBitLen = miso_bit_len;
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esp_rom_spi_cmd_config(spi_num, &conf);
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}
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void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
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uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
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uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
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uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
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psram_set_op_mode(spi_num, mode);
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_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
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dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
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esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
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WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
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WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
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WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
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WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
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PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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|
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//TODO IDF-4307
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//switch psram burst length(32 bytes or 1024 bytes)
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//datasheet says it should be 1024 bytes by default
|
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static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
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{
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psram_exec_cmd(spi_num, mode,
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PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
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CS_PSRAM_SEL, /* cs bit mask*/
|
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false); /* whether is program/erase operation */
|
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}
|
||||
|
||||
//send reset command to psram, in spi mode
|
||||
static void psram_reset_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
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PSRAM_RESET_EN, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
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PSRAM_RESET, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
esp_err_t psram_enable_wrap(uint32_t wrap_size)
|
||||
{
|
||||
//TODO: IDF-4307
|
||||
static uint32_t current_wrap_size = 0;
|
||||
if (current_wrap_size == wrap_size) {
|
||||
return ESP_OK;
|
||||
}
|
||||
switch (wrap_size) {
|
||||
case 32:
|
||||
case 0:
|
||||
psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
|
||||
current_wrap_size = wrap_size;
|
||||
return ESP_OK;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
bool psram_support_wrap_size(uint32_t wrap_size)
|
||||
{
|
||||
switch (wrap_size) {
|
||||
case 0:
|
||||
case 32:
|
||||
return true;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
|
||||
static void psram_read_id(int spi_num, uint32_t* dev_id)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
|
||||
0, 24, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//enter QPI mode
|
||||
static void psram_enable_qio_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
static void psram_set_cs_timing(void)
|
||||
{
|
||||
//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_TIME_V, 3, SPI_SMEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_SETUP_TIME_V, 3, SPI_SMEM_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_M | SPI_SMEM_CS_SETUP_M);
|
||||
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_DELAY_V, 3, SPI_SMEM_CS_HOLD_DELAY_S);
|
||||
}
|
||||
|
||||
static void psram_gpio_config(void)
|
||||
{
|
||||
//CS1
|
||||
uint8_t cs1_io = PSRAM_CS_IO;
|
||||
if (cs1_io == SPI_CS1_GPIO_NUM) {
|
||||
gpio_hal_iomux_func_sel(IO_MUX_GPIO15_REG, FUNC_SPICS1_SPICS1);
|
||||
} else {
|
||||
esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0);
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
|
||||
}
|
||||
s_psram_cs_io = cs1_io;
|
||||
|
||||
//WP HD
|
||||
uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
|
||||
//This ROM function will init both WP and HD pins.
|
||||
esp_rom_spiflash_select_qio_pins(wp_io, 0);
|
||||
|
||||
// Reserve psram pins
|
||||
esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
|
||||
}
|
||||
|
||||
esp_err_t esp_psram_impl_enable(void) //psram init
|
||||
{
|
||||
psram_gpio_config();
|
||||
psram_set_cs_timing();
|
||||
|
||||
//We use SPI1 to init PSRAM
|
||||
psram_disable_qio_mode(SPI1_NUM);
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
/* 16Mbit psram ID read error workaround:
|
||||
* treat the first read id as a dummy one as the pre-condition,
|
||||
* Send Read ID command again
|
||||
*/
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
|
||||
return ESP_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
if (PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_8MB;
|
||||
} else if (PSRAM_IS_2T_APS3204(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_4MB;
|
||||
} else {
|
||||
uint8_t density = PSRAM_SIZE_ID(s_psram_id);
|
||||
s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
|
||||
density == 0x1 ? PSRAM_SIZE_4MB :
|
||||
density == 0x2 ? PSRAM_SIZE_8MB : 0;
|
||||
}
|
||||
|
||||
//SPI1: send psram reset command
|
||||
psram_reset_mode(SPI1_NUM);
|
||||
//SPI1: send QPI enable command
|
||||
psram_enable_qio_mode(SPI1_NUM);
|
||||
|
||||
//Configure SPI0 PSRAM related SPI Phases
|
||||
config_psram_spi_phases();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv)
|
||||
{
|
||||
uint32_t freqbits = 0;
|
||||
if (1 >= freqdiv) {
|
||||
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
|
||||
} else {
|
||||
freqbits = (((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S);
|
||||
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
|
||||
}
|
||||
}
|
||||
|
||||
//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
|
||||
static void config_psram_spi_phases(void)
|
||||
{
|
||||
#if (CONFIG_SPIRAM_SPEED == 80)
|
||||
psram_clock_set(0, 1);
|
||||
#elif (CONFIG_SPIRAM_SPEED == 40)
|
||||
psram_clock_set(0, 2);
|
||||
#endif
|
||||
|
||||
//Config CMD phase
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
|
||||
|
||||
//Config ADDR phase
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
|
||||
|
||||
//Dummy
|
||||
/**
|
||||
* We set the PSRAM chip required dummy here. If timing tuning is needed,
|
||||
* the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
|
||||
*/
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
|
||||
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------
|
||||
* Following APIs are not required to be IRAM-Safe
|
||||
*
|
||||
* Consider moving these to another file if this kind of APIs grows dramatically
|
||||
*-------------------------------------------------------------------------------*/
|
||||
esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
|
||||
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
| Supported Targets | ESP32 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C5 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- |
|
||||
|
||||
This test app is used to test PSRAM
|
||||
|
||||
@ -86,3 +86,16 @@ def test_psram_esp32s3_octal(dut: Dut) -> None:
|
||||
)
|
||||
def test_psram_esp32p4(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
||||
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
[
|
||||
'esp32c5_release',
|
||||
],
|
||||
indirect=True,
|
||||
)
|
||||
def test_psram_esp32c5(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
CONFIG_IDF_TARGET="esp32c5"
|
||||
|
||||
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
|
||||
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
|
||||
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
|
||||
|
||||
CONFIG_SPIRAM=y
|
||||
@ -187,7 +187,6 @@ __attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
@ -219,12 +218,11 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
mmu_val |= (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
@ -240,7 +238,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
@ -263,7 +260,6 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
@ -322,7 +318,6 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
@ -361,7 +356,6 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
@ -385,7 +379,6 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
|
||||
69
components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
Normal file
69
components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/************************** MSPI pll clock configurations **************************/
|
||||
|
||||
/**
|
||||
* @brief Select mspi clock source
|
||||
*
|
||||
* @param clk_src the clock source of mspi clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src)
|
||||
{
|
||||
switch (clk_src) {
|
||||
case MSPI_CLK_SRC_XTAL:
|
||||
PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
|
||||
break;
|
||||
case MSPI_CLK_SRC_RC_FAST:
|
||||
PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
|
||||
break;
|
||||
case MSPI_CLK_SRC_SPLL:
|
||||
PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
|
||||
*
|
||||
* @param divider Divider.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void mspi_ll_fast_set_hs_divider(uint32_t divider)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the mspi bus clock
|
||||
*
|
||||
* @param enable enable the bus clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void mspi_ll_enable_bus_clock(bool enable)
|
||||
{
|
||||
PCR.mspi_conf.mspi_clk_en = enable;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -163,6 +163,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPIRAM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_XTAL_SUPPORT_40M
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -502,7 +502,7 @@ typedef enum {
|
||||
/**
|
||||
* @brief MSPI digital controller clock source
|
||||
*/
|
||||
typedef enum { // TODO: [ESP32C5] IDF-8649
|
||||
typedef enum {
|
||||
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
|
||||
|
||||
@ -137,6 +137,7 @@ extern "C" {
|
||||
#define SPI_CLK_GPIO_NUM 21
|
||||
#define SPI_D_GPIO_NUM 22
|
||||
#define SPI_Q_GPIO_NUM 17
|
||||
#define SPI_CS1_GPIO_NUM 15
|
||||
|
||||
#define USB_INT_PHY0_DM_GPIO_NUM 13
|
||||
#define USB_INT_PHY0_DP_GPIO_NUM 14
|
||||
|
||||
@ -77,6 +77,7 @@
|
||||
// #define SOC_DEEP_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
// #define SOC_PM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8643
|
||||
#define SOC_SPIRAM_SUPPORTED 1
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
@ -11,10 +11,10 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SPI_MEM_CMD_REG register
|
||||
/** SPI_MEM_CMD_REG(i) register
|
||||
* SPI1 memory command register
|
||||
*/
|
||||
#define SPI_MEM_CMD_REG (DR_REG_SPI_MEM_BASE + 0x0)
|
||||
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
|
||||
/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
|
||||
* The current status of SPI1 master FSM.
|
||||
*/
|
||||
@ -155,10 +155,10 @@ extern "C" {
|
||||
#define SPI_MEM_FLASH_READ_V 0x00000001U
|
||||
#define SPI_MEM_FLASH_READ_S 31
|
||||
|
||||
/** SPI_MEM_ADDR_REG register
|
||||
/** SPI_MEM_ADDR_REG(i) register
|
||||
* SPI1 address register
|
||||
*/
|
||||
#define SPI_MEM_ADDR_REG (DR_REG_SPI_MEM_BASE + 0x4)
|
||||
#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)
|
||||
/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
|
||||
* In user mode, it is the memory address. other then the bit0-bit23 is the memory
|
||||
* address, the bit24-bit31 are the byte length of a transfer.
|
||||
@ -168,10 +168,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_USR_ADDR_VALUE_S 0
|
||||
|
||||
/** SPI_MEM_CTRL_REG register
|
||||
/** SPI_MEM_CTRL_REG(i) register
|
||||
* SPI1 control register.
|
||||
*/
|
||||
#define SPI_MEM_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x8)
|
||||
#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)
|
||||
/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
|
||||
* In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
|
||||
* level of SPI bus is output by the MSPI controller.
|
||||
@ -314,10 +314,10 @@ extern "C" {
|
||||
#define SPI_MEM_FREAD_QIO_V 0x00000001U
|
||||
#define SPI_MEM_FREAD_QIO_S 24
|
||||
|
||||
/** SPI_MEM_CTRL1_REG register
|
||||
/** SPI_MEM_CTRL1_REG(i) register
|
||||
* SPI1 control1 register.
|
||||
*/
|
||||
#define SPI_MEM_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xc)
|
||||
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc)
|
||||
/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
|
||||
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
|
||||
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
|
||||
@ -336,10 +336,10 @@ extern "C" {
|
||||
#define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU
|
||||
#define SPI_MEM_CS_HOLD_DLY_RES_S 2
|
||||
|
||||
/** SPI_MEM_CTRL2_REG register
|
||||
/** SPI_MEM_CTRL2_REG(i) register
|
||||
* SPI1 control2 register.
|
||||
*/
|
||||
#define SPI_MEM_CTRL2_REG (DR_REG_SPI_MEM_BASE + 0x10)
|
||||
#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)
|
||||
/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
|
||||
* The FSM will be reset.
|
||||
*/
|
||||
@ -348,10 +348,10 @@ extern "C" {
|
||||
#define SPI_MEM_SYNC_RESET_V 0x00000001U
|
||||
#define SPI_MEM_SYNC_RESET_S 31
|
||||
|
||||
/** SPI_MEM_CLOCK_REG register
|
||||
/** SPI_MEM_CLOCK_REG(i) register
|
||||
* SPI1 clock division control register.
|
||||
*/
|
||||
#define SPI_MEM_CLOCK_REG (DR_REG_SPI_MEM_BASE + 0x14)
|
||||
#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
|
||||
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
|
||||
* In the master mode it must be equal to spi_mem_clkcnt_N.
|
||||
*/
|
||||
@ -382,10 +382,10 @@ extern "C" {
|
||||
#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U
|
||||
#define SPI_MEM_CLK_EQU_SYSCLK_S 31
|
||||
|
||||
/** SPI_MEM_USER_REG register
|
||||
/** SPI_MEM_USER_REG(i) register
|
||||
* SPI1 user register.
|
||||
*/
|
||||
#define SPI_MEM_USER_REG (DR_REG_SPI_MEM_BASE + 0x18)
|
||||
#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)
|
||||
/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
|
||||
* the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
|
||||
*/
|
||||
@ -480,10 +480,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_COMMAND_V 0x00000001U
|
||||
#define SPI_MEM_USR_COMMAND_S 31
|
||||
|
||||
/** SPI_MEM_USER1_REG register
|
||||
/** SPI_MEM_USER1_REG(i) register
|
||||
* SPI1 user1 register.
|
||||
*/
|
||||
#define SPI_MEM_USER1_REG (DR_REG_SPI_MEM_BASE + 0x1c)
|
||||
#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c)
|
||||
/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
|
||||
* The length in spi_mem_clk cycles of dummy phase. The register value shall be
|
||||
* (cycle_num-1).
|
||||
@ -500,10 +500,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU
|
||||
#define SPI_MEM_USR_ADDR_BITLEN_S 26
|
||||
|
||||
/** SPI_MEM_USER2_REG register
|
||||
/** SPI_MEM_USER2_REG(i) register
|
||||
* SPI1 user2 register.
|
||||
*/
|
||||
#define SPI_MEM_USER2_REG (DR_REG_SPI_MEM_BASE + 0x20)
|
||||
#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)
|
||||
/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
|
||||
* The value of command.
|
||||
*/
|
||||
@ -519,10 +519,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU
|
||||
#define SPI_MEM_USR_COMMAND_BITLEN_S 28
|
||||
|
||||
/** SPI_MEM_MOSI_DLEN_REG register
|
||||
/** SPI_MEM_MOSI_DLEN_REG(i) register
|
||||
* SPI1 send data bit length control register.
|
||||
*/
|
||||
#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x24)
|
||||
#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)
|
||||
/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
|
||||
* The length in bits of write-data. The register value shall be (bit_num-1).
|
||||
*/
|
||||
@ -531,10 +531,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_MOSI_DBITLEN_V 0x000003FFU
|
||||
#define SPI_MEM_USR_MOSI_DBITLEN_S 0
|
||||
|
||||
/** SPI_MEM_MISO_DLEN_REG register
|
||||
/** SPI_MEM_MISO_DLEN_REG(i) register
|
||||
* SPI1 receive data bit length control register.
|
||||
*/
|
||||
#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x28)
|
||||
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28)
|
||||
/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
|
||||
* The length in bits of read-data. The register value shall be (bit_num-1).
|
||||
*/
|
||||
@ -543,10 +543,10 @@ extern "C" {
|
||||
#define SPI_MEM_USR_MISO_DBITLEN_V 0x000003FFU
|
||||
#define SPI_MEM_USR_MISO_DBITLEN_S 0
|
||||
|
||||
/** SPI_MEM_RD_STATUS_REG register
|
||||
/** SPI_MEM_RD_STATUS_REG(i) register
|
||||
* SPI1 status register.
|
||||
*/
|
||||
#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_MEM_BASE + 0x2c)
|
||||
#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c)
|
||||
/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
|
||||
* The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
|
||||
*/
|
||||
@ -576,10 +576,10 @@ extern "C" {
|
||||
#define SPI_MEM_WB_MODE_EN_V 0x00000001U
|
||||
#define SPI_MEM_WB_MODE_EN_S 27
|
||||
|
||||
/** SPI_MEM_MISC_REG register
|
||||
/** SPI_MEM_MISC_REG(i) register
|
||||
* SPI1 misc register
|
||||
*/
|
||||
#define SPI_MEM_MISC_REG (DR_REG_SPI_MEM_BASE + 0x34)
|
||||
#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34)
|
||||
/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
|
||||
* SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
|
||||
* device, such as flash, external RAM and so on.
|
||||
@ -611,10 +611,10 @@ extern "C" {
|
||||
#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U
|
||||
#define SPI_MEM_CS_KEEP_ACTIVE_S 10
|
||||
|
||||
/** SPI_MEM_TX_CRC_REG register
|
||||
/** SPI_MEM_TX_CRC_REG(i) register
|
||||
* SPI1 TX CRC data register.
|
||||
*/
|
||||
#define SPI_MEM_TX_CRC_REG (DR_REG_SPI_MEM_BASE + 0x38)
|
||||
#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38)
|
||||
/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
|
||||
* For SPI1, the value of crc32.
|
||||
*/
|
||||
@ -623,10 +623,10 @@ extern "C" {
|
||||
#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_TX_CRC_DATA_S 0
|
||||
|
||||
/** SPI_MEM_CACHE_FCTRL_REG register
|
||||
/** SPI_MEM_CACHE_FCTRL_REG(i) register
|
||||
* SPI1 bit mode control register.
|
||||
*/
|
||||
#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_MEM_BASE + 0x3c)
|
||||
#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c)
|
||||
/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
|
||||
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
|
||||
*/
|
||||
@ -683,10 +683,10 @@ extern "C" {
|
||||
#define SPI_MEM_FADDR_QUAD_V 0x00000001U
|
||||
#define SPI_MEM_FADDR_QUAD_S 8
|
||||
|
||||
/** SPI_MEM_W0_REG register
|
||||
/** SPI_MEM_W0_REG(i) register
|
||||
* SPI1 memory data buffer0
|
||||
*/
|
||||
#define SPI_MEM_W0_REG (DR_REG_SPI_MEM_BASE + 0x58)
|
||||
#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58)
|
||||
/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -695,10 +695,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF0_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF0_S 0
|
||||
|
||||
/** SPI_MEM_W1_REG register
|
||||
/** SPI_MEM_W1_REG(i) register
|
||||
* SPI1 memory data buffer1
|
||||
*/
|
||||
#define SPI_MEM_W1_REG (DR_REG_SPI_MEM_BASE + 0x5c)
|
||||
#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c)
|
||||
/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -707,10 +707,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF1_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF1_S 0
|
||||
|
||||
/** SPI_MEM_W2_REG register
|
||||
/** SPI_MEM_W2_REG(i) register
|
||||
* SPI1 memory data buffer2
|
||||
*/
|
||||
#define SPI_MEM_W2_REG (DR_REG_SPI_MEM_BASE + 0x60)
|
||||
#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60)
|
||||
/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -719,10 +719,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF2_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF2_S 0
|
||||
|
||||
/** SPI_MEM_W3_REG register
|
||||
/** SPI_MEM_W3_REG(i) register
|
||||
* SPI1 memory data buffer3
|
||||
*/
|
||||
#define SPI_MEM_W3_REG (DR_REG_SPI_MEM_BASE + 0x64)
|
||||
#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64)
|
||||
/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -731,10 +731,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF3_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF3_S 0
|
||||
|
||||
/** SPI_MEM_W4_REG register
|
||||
/** SPI_MEM_W4_REG(i) register
|
||||
* SPI1 memory data buffer4
|
||||
*/
|
||||
#define SPI_MEM_W4_REG (DR_REG_SPI_MEM_BASE + 0x68)
|
||||
#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68)
|
||||
/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -743,10 +743,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF4_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF4_S 0
|
||||
|
||||
/** SPI_MEM_W5_REG register
|
||||
/** SPI_MEM_W5_REG(i) register
|
||||
* SPI1 memory data buffer5
|
||||
*/
|
||||
#define SPI_MEM_W5_REG (DR_REG_SPI_MEM_BASE + 0x6c)
|
||||
#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c)
|
||||
/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -755,10 +755,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF5_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF5_S 0
|
||||
|
||||
/** SPI_MEM_W6_REG register
|
||||
/** SPI_MEM_W6_REG(i) register
|
||||
* SPI1 memory data buffer6
|
||||
*/
|
||||
#define SPI_MEM_W6_REG (DR_REG_SPI_MEM_BASE + 0x70)
|
||||
#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70)
|
||||
/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -767,10 +767,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF6_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF6_S 0
|
||||
|
||||
/** SPI_MEM_W7_REG register
|
||||
/** SPI_MEM_W7_REG(i) register
|
||||
* SPI1 memory data buffer7
|
||||
*/
|
||||
#define SPI_MEM_W7_REG (DR_REG_SPI_MEM_BASE + 0x74)
|
||||
#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74)
|
||||
/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -779,10 +779,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF7_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF7_S 0
|
||||
|
||||
/** SPI_MEM_W8_REG register
|
||||
/** SPI_MEM_W8_REG(i) register
|
||||
* SPI1 memory data buffer8
|
||||
*/
|
||||
#define SPI_MEM_W8_REG (DR_REG_SPI_MEM_BASE + 0x78)
|
||||
#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78)
|
||||
/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -791,10 +791,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF8_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF8_S 0
|
||||
|
||||
/** SPI_MEM_W9_REG register
|
||||
/** SPI_MEM_W9_REG(i) register
|
||||
* SPI1 memory data buffer9
|
||||
*/
|
||||
#define SPI_MEM_W9_REG (DR_REG_SPI_MEM_BASE + 0x7c)
|
||||
#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c)
|
||||
/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -803,10 +803,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF9_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF9_S 0
|
||||
|
||||
/** SPI_MEM_W10_REG register
|
||||
/** SPI_MEM_W10_REG(i) register
|
||||
* SPI1 memory data buffer10
|
||||
*/
|
||||
#define SPI_MEM_W10_REG (DR_REG_SPI_MEM_BASE + 0x80)
|
||||
#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80)
|
||||
/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -815,10 +815,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF10_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF10_S 0
|
||||
|
||||
/** SPI_MEM_W11_REG register
|
||||
/** SPI_MEM_W11_REG(i) register
|
||||
* SPI1 memory data buffer11
|
||||
*/
|
||||
#define SPI_MEM_W11_REG (DR_REG_SPI_MEM_BASE + 0x84)
|
||||
#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84)
|
||||
/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -827,10 +827,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF11_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF11_S 0
|
||||
|
||||
/** SPI_MEM_W12_REG register
|
||||
/** SPI_MEM_W12_REG(i) register
|
||||
* SPI1 memory data buffer12
|
||||
*/
|
||||
#define SPI_MEM_W12_REG (DR_REG_SPI_MEM_BASE + 0x88)
|
||||
#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88)
|
||||
/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -839,10 +839,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF12_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF12_S 0
|
||||
|
||||
/** SPI_MEM_W13_REG register
|
||||
/** SPI_MEM_W13_REG(i) register
|
||||
* SPI1 memory data buffer13
|
||||
*/
|
||||
#define SPI_MEM_W13_REG (DR_REG_SPI_MEM_BASE + 0x8c)
|
||||
#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c)
|
||||
/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -851,10 +851,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF13_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF13_S 0
|
||||
|
||||
/** SPI_MEM_W14_REG register
|
||||
/** SPI_MEM_W14_REG(i) register
|
||||
* SPI1 memory data buffer14
|
||||
*/
|
||||
#define SPI_MEM_W14_REG (DR_REG_SPI_MEM_BASE + 0x90)
|
||||
#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90)
|
||||
/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -863,10 +863,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF14_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF14_S 0
|
||||
|
||||
/** SPI_MEM_W15_REG register
|
||||
/** SPI_MEM_W15_REG(i) register
|
||||
* SPI1 memory data buffer15
|
||||
*/
|
||||
#define SPI_MEM_W15_REG (DR_REG_SPI_MEM_BASE + 0x94)
|
||||
#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94)
|
||||
/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
|
||||
* data buffer
|
||||
*/
|
||||
@ -875,10 +875,10 @@ extern "C" {
|
||||
#define SPI_MEM_BUF15_V 0xFFFFFFFFU
|
||||
#define SPI_MEM_BUF15_S 0
|
||||
|
||||
/** SPI_MEM_FLASH_WAITI_CTRL_REG register
|
||||
/** SPI_MEM_FLASH_WAITI_CTRL_REG(i) register
|
||||
* SPI1 wait idle control register
|
||||
*/
|
||||
#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x98)
|
||||
#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98)
|
||||
/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
|
||||
* 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
|
||||
* Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
|
||||
@ -934,10 +934,10 @@ extern "C" {
|
||||
#define SPI_MEM_WAITI_CMD_V 0x0000FFFFU
|
||||
#define SPI_MEM_WAITI_CMD_S 16
|
||||
|
||||
/** SPI_MEM_FLASH_SUS_CTRL_REG register
|
||||
/** SPI_MEM_FLASH_SUS_CTRL_REG(i) register
|
||||
* SPI1 flash suspend control register
|
||||
*/
|
||||
#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x9c)
|
||||
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c)
|
||||
/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
|
||||
* program erase resume bit, program erase suspend operation will be triggered when
|
||||
* the bit is set. The bit will be cleared once the operation done.1: enable 0:
|
||||
@ -1032,10 +1032,10 @@ extern "C" {
|
||||
#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x0000007FU
|
||||
#define SPI_MEM_SUS_TIMEOUT_CNT_S 25
|
||||
|
||||
/** SPI_MEM_FLASH_SUS_CMD_REG register
|
||||
/** SPI_MEM_FLASH_SUS_CMD_REG(i) register
|
||||
* SPI1 flash suspend command register
|
||||
*/
|
||||
#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI_MEM_BASE + 0xa0)
|
||||
#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0)
|
||||
/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
|
||||
* Program/Erase suspend command.
|
||||
*/
|
||||
@ -1052,10 +1052,10 @@ extern "C" {
|
||||
#define SPI_MEM_WAIT_PESR_COMMAND_V 0x0000FFFFU
|
||||
#define SPI_MEM_WAIT_PESR_COMMAND_S 16
|
||||
|
||||
/** SPI_MEM_SUS_STATUS_REG register
|
||||
/** SPI_MEM_SUS_STATUS_REG(i) register
|
||||
* SPI1 flash suspend status register
|
||||
*/
|
||||
#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI_MEM_BASE + 0xa4)
|
||||
#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4)
|
||||
/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
|
||||
* The status of flash suspend, only used in SPI1.
|
||||
*/
|
||||
@ -1141,10 +1141,10 @@ extern "C" {
|
||||
#define SPI_MEM_FLASH_PER_COMMAND_V 0x0000FFFFU
|
||||
#define SPI_MEM_FLASH_PER_COMMAND_S 16
|
||||
|
||||
/** SPI_MEM_FLASH_WAITI_CTRL1_REG register
|
||||
/** SPI_MEM_FLASH_WAITI_CTRL1_REG(i) register
|
||||
* SPI1 wait idle control register
|
||||
*/
|
||||
#define SPI_MEM_FLASH_WAITI_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xac)
|
||||
#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac)
|
||||
/** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0;
|
||||
* SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
|
||||
*/
|
||||
@ -1160,10 +1160,10 @@ extern "C" {
|
||||
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V 0x00000001U
|
||||
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S 10
|
||||
|
||||
/** SPI_MEM_INT_ENA_REG register
|
||||
/** SPI_MEM_INT_ENA_REG(i) register
|
||||
* SPI1 interrupt enable register
|
||||
*/
|
||||
#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_MEM_BASE + 0xc0)
|
||||
#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0)
|
||||
/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The enable bit for SPI_MEM_PER_END_INT interrupt.
|
||||
*/
|
||||
@ -1207,10 +1207,10 @@ extern "C" {
|
||||
#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x00000001U
|
||||
#define SPI_MEM_BROWN_OUT_INT_ENA_S 10
|
||||
|
||||
/** SPI_MEM_INT_CLR_REG register
|
||||
/** SPI_MEM_INT_CLR_REG(i) register
|
||||
* SPI1 interrupt clear register
|
||||
*/
|
||||
#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_MEM_BASE + 0xc4)
|
||||
#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4)
|
||||
/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* The clear bit for SPI_MEM_PER_END_INT interrupt.
|
||||
*/
|
||||
@ -1254,10 +1254,10 @@ extern "C" {
|
||||
#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x00000001U
|
||||
#define SPI_MEM_BROWN_OUT_INT_CLR_S 10
|
||||
|
||||
/** SPI_MEM_INT_RAW_REG register
|
||||
/** SPI_MEM_INT_RAW_REG(i) register
|
||||
* SPI1 interrupt raw register
|
||||
*/
|
||||
#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_MEM_BASE + 0xc8)
|
||||
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8)
|
||||
/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
|
||||
* command (0x7A) is sent and flash is resumed successfully. 0: Others.
|
||||
@ -1310,10 +1310,10 @@ extern "C" {
|
||||
#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x00000001U
|
||||
#define SPI_MEM_BROWN_OUT_INT_RAW_S 10
|
||||
|
||||
/** SPI_MEM_INT_ST_REG register
|
||||
/** SPI_MEM_INT_ST_REG(i) register
|
||||
* SPI1 interrupt status register
|
||||
*/
|
||||
#define SPI_MEM_INT_ST_REG (DR_REG_SPI_MEM_BASE + 0xcc)
|
||||
#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc)
|
||||
/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for SPI_MEM_PER_END_INT interrupt.
|
||||
*/
|
||||
@ -1357,10 +1357,10 @@ extern "C" {
|
||||
#define SPI_MEM_BROWN_OUT_INT_ST_V 0x00000001U
|
||||
#define SPI_MEM_BROWN_OUT_INT_ST_S 10
|
||||
|
||||
/** SPI_MEM_DDR_REG register
|
||||
/** SPI_MEM_DDR_REG(i) register
|
||||
* SPI1 DDR control register
|
||||
*/
|
||||
#define SPI_MEM_DDR_REG (DR_REG_SPI_MEM_BASE + 0xd4)
|
||||
#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4)
|
||||
/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
|
||||
* 1: in ddr mode, 0 in sdr mode
|
||||
*/
|
||||
@ -1466,10 +1466,10 @@ extern "C" {
|
||||
#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x00000001U
|
||||
#define SPI_MEM_FMEM_HYPERBUS_CA_S 30
|
||||
|
||||
/** SPI_MEM_TIMING_CALI_REG register
|
||||
/** SPI_MEM_TIMING_CALI_REG(i) register
|
||||
* SPI1 timing control register
|
||||
*/
|
||||
#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_MEM_BASE + 0x180)
|
||||
#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180)
|
||||
/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
|
||||
* The bit is used to enable timing auto-calibration for all reading operations.
|
||||
*/
|
||||
@ -1485,10 +1485,10 @@ extern "C" {
|
||||
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U
|
||||
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2
|
||||
|
||||
/** SPI_MEM_CLOCK_GATE_REG register
|
||||
/** SPI_MEM_CLOCK_GATE_REG(i) register
|
||||
* SPI1 clk_gate register
|
||||
*/
|
||||
#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_MEM_BASE + 0x200)
|
||||
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
|
||||
/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Register clock gate enable signal. 1: Enable. 0: Disable.
|
||||
*/
|
||||
@ -1497,10 +1497,10 @@ extern "C" {
|
||||
#define SPI_MEM_CLK_EN_V 0x00000001U
|
||||
#define SPI_MEM_CLK_EN_S 0
|
||||
|
||||
/** SPI_MEM_DATE_REG register
|
||||
/** SPI_MEM_DATE_REG(i) register
|
||||
* Version control register
|
||||
*/
|
||||
#define SPI_MEM_DATE_REG (DR_REG_SPI_MEM_BASE + 0x3fc)
|
||||
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
|
||||
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400;
|
||||
* Version control register
|
||||
*/
|
||||
|
||||
@ -386,7 +386,7 @@ examples/system/unit_test/:
|
||||
|
||||
examples/system/xip_from_psram:
|
||||
enable:
|
||||
- if: SOC_SPIRAM_SUPPORTED == 1
|
||||
- if: SOC_SPIRAM_SUPPORTED == 1 and SOC_SPIRAM_XIP_SUPPORTED == 1
|
||||
reason: this feature is supported on chips that have PSRAM
|
||||
disable:
|
||||
- if: IDF_TARGET == "esp32"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user