Merge branch 'cherry_pick_to_release_v2.1' into 'release/v2.1'

Update release/v2.1 with some bug fixes

See merge request !952

components/driver/include/driver/uart.h

@@ -474,6 +474,8 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
  * @param rx_buffer_size UART RX ring buffer size, rx_buffer_size should be greater than UART_FIFO_LEN.
  * @param tx_buffer_size UART TX ring buffer size.
  *        If set to zero, driver will not use TX buffer, TX function will block task until all data have been sent out..
+ *        @note tx_buffer_size should be greater than UART_FIFO_LEN.
+ *
  * @param queue_size UART event queue size/depth.
  * @param uart_queue UART event queue handle (out param). On success, a new queue handle is written here to provide
  *        access to UART events. If set to NULL, driver will not use an event queue.

components/driver/uart.c

@@ -191,7 +191,7 @@ esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate)
 esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
-    UART_CHECK((((inverse_mask & ~UART_LINE_INV_MASK) == 0) && (inverse_mask != 0)), "inverse_mask error", ESP_FAIL);
+    UART_CHECK((((inverse_mask & ~UART_LINE_INV_MASK) == 0) || (inverse_mask == 0)), "inverse_mask error", ESP_FAIL);
     UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
     CLEAR_PERI_REG_MASK(UART_CONF0_REG(uart_num), UART_LINE_INV_MASK);
     SET_PERI_REG_MASK(UART_CONF0_REG(uart_num), inverse_mask);
@@ -970,6 +970,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
     UART_CHECK((rx_buffer_size > UART_FIFO_LEN), "uart rx buffer length error(>128)", ESP_FAIL);
+    UART_CHECK((tx_buffer_size > UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error(>128 or 0)", ESP_FAIL);
     if(p_uart_obj[uart_num] == NULL) {
         p_uart_obj[uart_num] = (uart_obj_t*) malloc(sizeof(uart_obj_t));
         if(p_uart_obj[uart_num] == NULL) {

components/esp32/Kconfig

@@ -199,8 +199,24 @@ config MAIN_TASK_STACK_SIZE
     int "Main task stack size"
     default 4096
     help
-        Config system event task stack size in different application.
+        Configure the "main task" stack size. This is the stack of the task
+        which calls app_main(). If app_main() returns then this task is deleted
+        and its stack memory is freed.
 
+config IPC_TASK_STACK_SIZE
+    int "Inter-Processor Call (IPC) task stack size"
+    default 1024
+    range 512 65536 if !ESP32_APPTRACE_ENABLE
+    range 2048 65536 if ESP32_APPTRACE_ENABLE
+    help
+        Configure the IPC tasks stack size. One IPC task runs on each core
+        (in dual core mode), and allows for cross-core function calls.
+
+        See IPC documentation for more details.
+
+        The default stack size should be enough for most common use cases.
+        It can be shrunk if you are sure that you do not use any custom
+        IPC functionality.
 
 config NEWLIB_STDOUT_ADDCR
     bool "Standard-out output adds carriage return before newline"

components/esp32/dport_access.c

@@ -22,6 +22,7 @@
 #include <stdint.h>
 #include <string.h>
 
+#include <sdkconfig.h>
 #include "esp_attr.h"
 #include "esp_err.h"
 #include "esp_intr.h"
@@ -145,16 +146,20 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
     DPORT_STALL_OTHER_CPU_END();
 }
 
-static void dport_access_init_core0(void *arg)
+static void dport_access_init_core(void *arg)
 {
-    int core_id = xPortGetCoreID();
+    int core_id = 0;
+    uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
 
-    assert(core_id == 0);
-
-    vPortCPUInitializeMutex(&g_dport_mux);
+#ifndef CONFIG_FREERTOS_UNICORE
+    core_id = xPortGetCoreID();
+    if (core_id == 1) {
+        intr_source = ETS_FROM_CPU_INTR3_SOURCE;
+    }
+#endif
 
     ESP_INTR_DISABLE(ETS_DPORT_INUM);
-    intr_matrix_set(core_id, ETS_FROM_CPU_INTR2_SOURCE, ETS_DPORT_INUM);
+    intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
     ESP_INTR_ENABLE(ETS_DPORT_INUM);
 
     dport_access_ref[core_id] = 0;
@@ -165,33 +170,10 @@ static void dport_access_init_core0(void *arg)
     vTaskDelete(NULL);
 }
 
-static void dport_access_init_core1(void *arg)
-{
-    int core_id = xPortGetCoreID();
-
-    assert(core_id == 1);
-
-    ESP_INTR_DISABLE(ETS_DPORT_INUM);
-    intr_matrix_set(core_id, ETS_FROM_CPU_INTR3_SOURCE, ETS_DPORT_INUM);
-    ESP_INTR_ENABLE(ETS_DPORT_INUM);
-
-    dport_access_ref[core_id] = 0;
-    dport_access_start[core_id] = 0;
-    dport_access_end[core_id] = 0;
-    dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
-
-    vTaskDelete(NULL);
-}
-
-
-/*  This initialise should be really effective after vTaskStartScheduler */
+/*  Defer initialisation until after scheduler is running */
 void esp_dport_access_int_init(void)
 {
-    if (xPortGetCoreID() == 0) {
-        xTaskCreatePinnedToCore(&dport_access_init_core0, "dport0", 512, NULL, 5, NULL, 0);
-    } else {
-        xTaskCreatePinnedToCore(&dport_access_init_core1, "dport1", 512, NULL, 5, NULL, 1);
-    }
+    xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
 }
 
 void esp_dport_access_int_deinit(void)

components/esp32/include/esp_ipc.h

@@ -57,6 +57,10 @@ void esp_ipc_init();
  *
  * In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
  *
+ * For complex functions, you may need to increase the stack size of the "IPC task"
+ * which runs the function must be sufficient. See the "Inter-Processor Call (IPC)
+ * task stack size" setting in menuconfig.
+ *
  * @param cpu_id CPU where function should be executed (0 or 1)
  * @param func pointer to a function which should be executed
  * @param arg arbitrary argument to be passed into function

components/esp32/ipc.c

@@ -80,7 +80,7 @@ void esp_ipc_init()
     const char* task_names[2] = {"ipc0", "ipc1"};
     for (int i = 0; i < portNUM_PROCESSORS; ++i) {
         s_ipc_sem[i] = xSemaphoreCreateBinary();
-        xTaskCreatePinnedToCore(ipc_task, task_names[i], XT_STACK_MIN_SIZE, (void*) i,
+        xTaskCreatePinnedToCore(ipc_task, task_names[i], CONFIG_IPC_TASK_STACK_SIZE, (void*) i,
                                 configMAX_PRIORITIES - 1, &s_ipc_tasks[i], i);
     }
 }

components/esp32/phy_init.c

@@ -119,7 +119,7 @@ const esp_phy_init_data_t* esp_phy_get_init_data()
         ESP_LOGE(TAG, "failed to validate PHY data partition");
         return NULL;
     }
-    ESP_LOGE(TAG, "PHY data partition validated");
+    ESP_LOGD(TAG, "PHY data partition validated");
     return (const esp_phy_init_data_t*) (init_data_store + sizeof(phy_init_magic_pre));
 }
 

components/esp32/system_api.c

@@ -349,6 +349,7 @@ const char* esp_get_idf_version(void)
 
 static void get_chip_info_esp32(esp_chip_info_t* out_info)
 {
+    out_info->model = CHIP_ESP32;
     uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
     memset(out_info, 0, sizeof(*out_info));
     if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {

components/freertos/include/freertos/FreeRTOSConfig.h

@@ -163,15 +163,13 @@
 #define configMAX_PRIORITIES			( 25 )
 #endif
 
-/* Minimal stack size. This may need to be increased for your application */
-/* NOTE: The FreeRTOS demos may not work reliably with stack size < 4KB.  */
-/* The Xtensa-specific examples should be fine with XT_STACK_MIN_SIZE.    */
-#if !(defined XT_STACK_MIN_SIZE)
-#error XT_STACK_MIN_SIZE not defined, did you include xtensa_config.h ?
+#ifndef CONFIG_ESP32_APPTRACE_ENABLE
+#define configMINIMAL_STACK_SIZE		512
+#else
+/* apptrace module requires at least 2KB of stack per task */
+#define configMINIMAL_STACK_SIZE		2048
 #endif
 
-#define configMINIMAL_STACK_SIZE		(XT_STACK_MIN_SIZE > 1024 ? XT_STACK_MIN_SIZE : 1024)
-
 /* The Xtensa port uses a separate interrupt stack. Adjust the stack size */
 /* to suit the needs of your specific application.                        */
 #ifndef configISR_STACK_SIZE

components/mbedtls/Kconfig

@@ -31,14 +31,25 @@ config MBEDTLS_DEBUG
 	   at runtime in order to enable mbedTLS debug output via the ESP
 	   log mechanism.
 
+config MBEDTLS_UNSAFE_ACCELERATION
+   bool "Allow buggy hardware acceleration features"
+   depends on !FREERTOS_UNICORE
+   default n
+   help
+       A bug currently prevents dual cores & crypto hardware acceleration from being used together.
+
+       Enable this option to allow hardware acceleration anyhow (note that invalid results or crashes may occur.)
+
 config MBEDTLS_HARDWARE_AES
    bool "Enable hardware AES acceleration"
+   depends on MBEDTLS_UNSAFE_ACCELERATION || FREERTOS_UNICORE
    default y
    help
        Enable hardware accelerated AES encryption & decryption.
 
 config MBEDTLS_HARDWARE_MPI
    bool "Enable hardware MPI (bignum) acceleration"
+   depends on MBEDTLS_UNSAFE_ACCELERATION || FREERTOS_UNICORE
    default y
    help
        Enable hardware accelerated multiple precision integer operations.
@@ -60,6 +71,7 @@ config MBEDTLS_MPI_USE_INTERRUPT
 
 config MBEDTLS_HARDWARE_SHA
    bool "Enable hardware SHA acceleration"
+   depends on MBEDTLS_UNSAFE_ACCELERATION || FREERTOS_UNICORE
    default y
    help
        Enable hardware accelerated SHA1, SHA256, SHA384 & SHA512 in mbedTLS.

components/mbedtls/test/test_mbedtls_sha.c

@@ -165,8 +165,14 @@ TEST_CASE("mbedtls SHA self-tests multithreaded", "[mbedtls]")
     xTaskCreate(tskRunSHASelftests, "SHASelftests1", 8192, NULL, 3, NULL);
     xTaskCreate(tskRunSHASelftests, "SHASelftests2", 8192, NULL, 3, NULL);
 
+#ifdef CONFIG_MBEDTLS_HARDWARE_SHA
+    const int TIMEOUT_MS = 12000;
+#else
+    const int TIMEOUT_MS = 20000; // Soft-only SHA may need a little longer
+#endif
+
     for(int i = 0; i < 2; i++) {
-        if(!xSemaphoreTake(done_sem, 12000/portTICK_PERIOD_MS)) {
+        if(!xSemaphoreTake(done_sem, TIMEOUT_MS/portTICK_PERIOD_MS)) {
             TEST_FAIL_MESSAGE("done_sem not released by test task");
         }
     }

components/newlib/locks.c

@@ -41,14 +41,16 @@
 
 static portMUX_TYPE lock_init_spinlock = portMUX_INITIALIZER_UNLOCKED;
 
-/* Initialise the given lock by allocating a new mutex semaphore
+/* Initialize the given lock by allocating a new mutex semaphore
    as the _lock_t value.
+
+   Called by _lock_init*, also called by _lock_acquire* to lazily initialize locks that might have
+   been initialised (to zero only) before the RTOS scheduler started.
 */
 static void IRAM_ATTR lock_init_generic(_lock_t *lock, uint8_t mutex_type) {
     portENTER_CRITICAL(&lock_init_spinlock);
     if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
         /* nothing to do until the scheduler is running */
-        *lock = 0; /* ensure lock is zeroed out, in case it's an automatic variable */
         portEXIT_CRITICAL(&lock_init_spinlock);
         return;
     }
@@ -84,10 +86,12 @@ static void IRAM_ATTR lock_init_generic(_lock_t *lock, uint8_t mutex_type) {
 }
 
 void IRAM_ATTR _lock_init(_lock_t *lock) {
+    *lock = 0; // In case lock's memory is uninitialized
     lock_init_generic(lock, queueQUEUE_TYPE_MUTEX);
 }
 
 void IRAM_ATTR _lock_init_recursive(_lock_t *lock) {
+    *lock = 0; // In case lock's memory is uninitialized
     lock_init_generic(lock, queueQUEUE_TYPE_RECURSIVE_MUTEX);
 }
 
@@ -96,6 +100,10 @@ void IRAM_ATTR _lock_init_recursive(_lock_t *lock) {
    Note that FreeRTOS doesn't account for deleting mutexes while they
    are held, and neither do we... so take care not to delete newlib
    locks while they may be held by other tasks!
+
+   Also, deleting a lock in this way will cause it to be lazily
+   re-initialised if it is used again. Caller has to avoid doing
+   this!
 */
 void IRAM_ATTR _lock_close(_lock_t *lock) {
     portENTER_CRITICAL(&lock_init_spinlock);

components/nvs_flash/include/nvs.h

@@ -42,7 +42,7 @@ typedef uint32_t nvs_handle;
 #define ESP_ERR_NVS_INVALID_STATE       (ESP_ERR_NVS_BASE + 0x0b)  /*!< NVS is in an inconsistent state due to a previous error. Call nvs_flash_init and nvs_open again, then retry. */
 #define ESP_ERR_NVS_INVALID_LENGTH      (ESP_ERR_NVS_BASE + 0x0c)  /*!< String or blob length is not sufficient to store data */
 #define ESP_ERR_NVS_NO_FREE_PAGES       (ESP_ERR_NVS_BASE + 0x0d)  /*!< NVS partition doesn't contain any empty pages. This may happen if NVS partition was truncated. Erase the whole partition and call nvs_flash_init again. */
-#define ESP_ERR_NVS_VALUE_TOO_LONG      (ESP_ERR_NVS_BASE + 0x0c)  /*!< String or blob length is longer than supported by the implementation */
+#define ESP_ERR_NVS_VALUE_TOO_LONG      (ESP_ERR_NVS_BASE + 0x0e)  /*!< String or blob length is longer than supported by the implementation */
 
 /**
  * @brief Mode of opening the non-volatile storage

components/nvs_flash/test_nvs_host/test_nvs.cpp

@@ -522,6 +522,14 @@ TEST_CASE("nvs api tests", "[nvs]")
     char buf[strlen(str) + 1];
     size_t buf_len = sizeof(buf);
 
+    size_t buf_len_needed;
+    TEST_ESP_OK(nvs_get_str(handle_2, "key", NULL, &buf_len_needed));
+    CHECK(buf_len_needed == buf_len);
+    
+    size_t buf_len_short = buf_len - 1;
+    TEST_ESP_ERR(ESP_ERR_NVS_INVALID_LENGTH, nvs_get_str(handle_2, "key", buf, &buf_len_short));
+    CHECK(buf_len_short == buf_len);
+    
     TEST_ESP_OK(nvs_get_str(handle_2, "key", buf, &buf_len));
 
     CHECK(0 == strcmp(buf, str));

components/soc/esp32/rtc_init.c

@@ -45,8 +45,8 @@ void rtc_init(rtc_config_t cfg)
         DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO);
         DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_PRO_ROM_FO);
         //clear sram clock force on
-        DPORT_SET_PERI_REG_BITS(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0, 0, DPORT_SRAM_FO_0_S);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_1);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_1_REG, DPORT_SRAM_FO_1);
         //clear tag clock force on
         DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON);
         DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_PRO_CACHE_TAG_FORCE_ON);

docs/api-guides/general-notes.rst

@@ -82,7 +82,7 @@ If some application code needs to be placed into IRAM, it can be done using ``IR
 
 Here are the cases when parts of application may or should be placed into IRAM.
 
-- ISR handlers must always be placed into IRAM. Furthermore, ISR handlers may only call functions placed into IRAM or functions present in ROM. *Note 1:* all FreeRTOS APIs are currently placed into IRAM, so are safe to call from ISR handlers. *Note 1:* all constant data used by ISR handlers and functions called from ISR handlers (including, but not limited to, ``const char`` arrays), must be placed into DRAM using ``DRAM_ATTR``.
+- Interrupt handlers must be placed into IRAM if ``ESP_INTR_FLAG_IRAM`` is used when registering the interrupt handler. In this case, ISR may only call functions placed into IRAM or functions present in ROM. *Note 1:* all FreeRTOS APIs are currently placed into IRAM, so are safe to call from interrupt handlers. If the ISR is placed into IRAM, all constant data used by the ISR and functions called from ISR (including, but not limited to, ``const char`` arrays), must be placed into DRAM using ``DRAM_ATTR``.
 
 - Some timing critical code may be placed into IRAM to reduce the penalty associated with loading the code from flash. ESP32 reads code and data from flash via a 32 kB cache. In some cases, placing a function into IRAM may reduce delays caused by a cache miss.
 
@@ -103,13 +103,13 @@ DRAM (data RAM)
 
 Non-constant static data and zero-initialized data is placed by the linker into the 256 kB ``0x3FFB0000 — 0x3FFF0000`` region. Note that this region is reduced by 64kB (by shifting start address to ``0x3FFC0000``) if Bluetooth stack is used. Length of this region is also reduced by 16 kB or 32kB if trace memory is used. All space which is left in this region after placing static data there is used for the runtime heap.
 
-Constant data may also be placed into DRAM, for example if it is used in an ISR handler (see notes in IRAM section above). To do that, ``DRAM_ATTR`` define can be used::
+Constant data may also be placed into DRAM, for example if it is used in an ISR (see notes in IRAM section above). To do that, ``DRAM_ATTR`` define can be used::
 
 	DRAM_ATTR const char[] format_string = "%p %x";
 	char buffer[64];
 	sprintf(buffer, format_string, ptr, val);
 
-Needless to say, it is not advised to use ``printf`` and other output functions in ISR handlers. For debugging purposes, use ``ESP_EARLY_LOGx`` macros when logging from ISR handlers. Make sure that both ``TAG`` and format string are placed into ``DRAM`` in that case.
+Needless to say, it is not advised to use ``printf`` and other output functions in ISRs. For debugging purposes, use ``ESP_EARLY_LOGx`` macros when logging from ISRs. Make sure that both ``TAG`` and format string are placed into ``DRAM`` in that case.
 
 DROM (data stored in Flash)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^

docs/security/flash-encryption.rst

@@ -373,7 +373,7 @@ Flash Encryption Algorithm
 
 - AES algorithm is used inverted in flash encryption, so the flash encryption "encrypt" operation is AES decrypt and the "decrypt" operation is AES encrypt. This is for performance reasons and does not alter the effectiveness of the algorithm.
 
-- The main flash encryption key is stored in efuse (BLK2) and by default is protected from further writes or software readout.
+- The main flash encryption key is stored in efuse (BLOCK1) and by default is protected from further writes or software readout.
 
 - Each 32 byte block (two adjacent 16 byte AES blocks) is encrypted with a unique key. The key is derived from the main flash encryption key in efuse, XORed with the offset of this block in the flash (a "key tweak").
 

docs/security/secure-boot.rst

@@ -14,7 +14,7 @@ Background
 
 - Most data is stored in flash. Flash access does not need to be protected from physical access in order for secure boot to function, because critical data is stored (non-software-accessible) in Efuses internal to the chip.
 
-- Efuses are used to store the secure bootloader key (in efuse block 2), and also a single Efuse bit (ABS_DONE_0) is burned (written to 1) to permanently enable secure boot on the chip. For more details about efuse, see the (forthcoming) chapter in the Technical Reference Manual.
+- Efuses are used to store the secure bootloader key (in efuse BLOCK2), and also a single Efuse bit (ABS_DONE_0) is burned (written to 1) to permanently enable secure boot on the chip.  For more details about efuse, see Chapter 11 "eFuse Controller" in the Technical Referecnce Manual.
 
 - To understand the secure boot process, first familiarise yourself with the standard :doc:`ESP-IDF boot process <../api-guides/general-notes>`.
 

examples/get-started/blink/main/blink.c

@@ -40,5 +40,5 @@ void blink_task(void *pvParameter)
 
 void app_main()
 {
-    xTaskCreate(&blink_task, "blink_task", 512, NULL, 5, NULL);
+    xTaskCreate(&blink_task, "blink_task", configMINIMAL_STACK_SIZE, NULL, 5, NULL);
 }

tools/unit-test-app/sdkconfig

@@ -81,8 +81,13 @@ CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_app.csv"
 CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET=0x10000
 CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_app.csv"
 CONFIG_APP_OFFSET=0x10000
+
+#
+# Compiler options
+#
 CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
 # CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
+CONFIG_OPTIMIZATION_ASSERTIONS=y
 
 #
 # Component config
@@ -117,6 +122,7 @@ CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
 CONFIG_MAIN_TASK_STACK_SIZE=4096
+CONFIG_IPC_TASK_STACK_SIZE=1024
 CONFIG_NEWLIB_STDOUT_ADDCR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
 CONFIG_CONSOLE_UART_DEFAULT=y
@@ -245,21 +251,35 @@ CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX=0
 CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
 # CONFIG_LWIP_IP_FRAG is not set
 # CONFIG_LWIP_IP_REASSEMBLY is not set
+
+#
+# TCP
+#
 CONFIG_TCP_MAXRTX=12
 CONFIG_TCP_SYNMAXRTX=6
+CONFIG_TCP_MSS=1436
+CONFIG_TCP_SND_BUF_DEFAULT=5744
+CONFIG_TCP_WND_DEFAULT=5744
+CONFIG_TCP_QUEUE_OOSEQ=y
+CONFIG_TCP_OVERSIZE_MSS=y
+# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
+# CONFIG_TCP_OVERSIZE_DISABLE is not set
 # CONFIG_LWIP_DHCP_DOES_ARP_CHECK is not set
 CONFIG_TCPIP_TASK_STACK_SIZE=2048
 # CONFIG_PPP_SUPPORT is not set
 
+#
+# ICMP
+#
+# CONFIG_LWIP_MULTICAST_PING is not set
+# CONFIG_LWIP_BROADCAST_PING is not set
+
 #
 # mbedTLS
 #
 CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
 # CONFIG_MBEDTLS_DEBUG is not set
-CONFIG_MBEDTLS_HARDWARE_AES=y
-CONFIG_MBEDTLS_HARDWARE_MPI=y
-CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
-CONFIG_MBEDTLS_HARDWARE_SHA=y
+# CONFIG_MBEDTLS_UNSAFE_ACCELERATION is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set