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Merge branch 'feature/support_esp32s3_beta_3' into 'master'

Browse Source 
Support ESP32S3 beta 3 target

Closes IDF-2908

See merge request espressif/esp-idf!12661
This commit is contained in:
Angus Gratton 2021-03-23 10:17:58 +00:00
commit fa2946d651
133 changed files with 58385 additions and 38858 deletions
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8
Kconfig
View File

@ -48,14 +48,14 @@ mainmenu "Espressif IoT Development Framework Configuration"
choice IDF_TARGET_ESP32S3_BETA_VERSION
prompt "ESP32-S3 beta version"
depends on IDF_TARGET_ESP32S3
default IDF_TARGET_ESP32S3_BETA_VERSION_2
default IDF_TARGET_ESP32S3_BETA_VERSION_3
help
Currently ESP32-S3 has several beta versions for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32S3_BETA_VERSION_2
config IDF_TARGET_ESP32S3_BETA_VERSION_3
bool
prompt "ESP32-S3 beta2"
prompt "ESP32-S3 beta3"
endchoice
config IDF_TARGET_ESP32C3
@ -68,8 +68,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
hex
default 0x0000 if IDF_TARGET_ESP32
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0004 if IDF_TARGET_ESP32S3
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0006 if IDF_TARGET_ESP32S3
default 0xFFFF
menu "SDK tool configuration"

2
components/bootloader_support/include/esp_app_format.h
View File

@ -22,8 +22,8 @@
typedef enum {
ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */
ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */
ESP_CHIP_ID_ESP32S3 = 0x0004, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0006, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

5
components/bootloader_support/src/bootloader_console_loader.c
View File

@ -27,6 +27,11 @@
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_persist.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h"
#include "esp32s3/rom/usb/usb_dc.h"
#include "esp32s3/rom/usb/cdc_acm.h"
#include "esp32s3/rom/usb/usb_persist.h"
#endif
#ifdef CONFIG_ESP_CONSOLE_USB_CDC

3
components/bootloader_support/src/bootloader_flash_config_esp32s3.c
View File

@ -32,7 +32,8 @@
void bootloader_flash_update_id()
{
g_rom_flashchip.device_id = bootloader_read_flash_id();
esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
chip->device_id = bootloader_read_flash_id();
}
void IRAM_ATTR bootloader_flash_cs_timing_config()

2
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -290,7 +290,9 @@ static void bootloader_check_wdt_reset(void)
static void bootloader_super_wdt_auto_feed(void)
{
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
}
esp_err_t bootloader_init(void)

2
components/bootloader_support/src/flash_partitions.c
View File

@ -19,6 +19,8 @@
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#else
#include "esp32/rom/spi_flash.h"
#endif

3
components/driver/i2c.c
View File

@ -13,6 +13,7 @@
// limitations under the License.
#include <string.h>
#include <stdio.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@ -779,7 +780,7 @@ esp_err_t i2c_get_data_timing(i2c_port_t i2c_num, int *sample_time, int *hold_ti
esp_err_t i2c_set_timeout(i2c_port_t i2c_num, int timeout)
{
I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
I2C_CHECK((timeout <= I2C_TIME_OUT_REG_V) && (timeout > 0), I2C_TIMEING_VAL_ERR_STR, ESP_ERR_INVALID_ARG);
I2C_CHECK((timeout <= I2C_LL_MAX_TIMEOUT) && (timeout > 0), I2C_TIMEING_VAL_ERR_STR, ESP_ERR_INVALID_ARG);
I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
i2c_hal_set_tout(&(i2c_context[i2c_num].hal), timeout);

14
components/esp32s3/clk.c
View File

@ -17,30 +17,22 @@
#include "esp_attr.h"
#include "esp32s3/clk.h"
#include "esp32s3/rom/ets_sys.h"
#include "soc/rtc.h"
#define MHZ (1000000)
// g_ticks_us defined in ROMs for PRO and APP CPU
extern uint32_t g_ticks_per_us_pro;
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us_pro * MHZ;
return ets_get_cpu_frequency() * MHZ;
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us_pro, 80) * MHZ;
return MIN(ets_get_cpu_frequency(), 80) * MHZ;
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
}

3
components/esp32s3/ld/esp32s3.peripherals.ld
View File

@ -31,7 +31,8 @@ PROVIDE ( I2C1 = 0x60027000 );
PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( UART2 = 0x6001e000 );
PROVIDE ( UART2 = 0x6002E000 );
PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM = 0x60041000 );
PROVIDE ( USB0 = 0x60080000 );

5
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -40,7 +40,7 @@ static const char *TAG = "rtc_clk";
#define DELAY_RTC_CLK_SWITCH 5
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
static uint32_t s_cur_pll_freq = RTC_PLL_FREQ_480M;
static uint32_t s_cur_pll_freq;
static void rtc_clk_cpu_freq_to_8m(void);
@ -306,7 +306,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
s_cur_pll_freq = pll_freq;
}

40
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -20,11 +20,11 @@
#include "soc/gpio_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/syscon_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_ulp.h"
#include "soc_log.h"
#define RTC_CNTL_MEM_FORCE_PU (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
static char *TAG = "rtcinit";
@ -46,15 +46,22 @@ void rtc_init(rtc_config_t cfg)
rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
// set bt timer
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
// set rtc peri timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
// set digital wrap timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
// set rtc memory timer
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
/* Reset RTC bias to default value (needed if waking up from deep sleep) */
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
@ -63,10 +70,6 @@ void rtc_init(rtc_config_t cfg)
if (cfg.clkctl_init) {
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
//clear rom clock force on
REG_SET_FIELD(SYSTEM_ROM_CTRL_0_REG, SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON, 0);
//clear sram clock force on
REG_SET_FIELD(SYSTEM_SRAM_CTRL_0_REG, SYSTEM_SRAM_CLKGATE_FORCE_ON, 0);
//clear tag clock force on
CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
@ -88,6 +91,9 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
//cancel bbpll force pu if setting no force power up
if (!cfg.bbpll_fpu) {
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
@ -103,9 +109,7 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
//combine two rtc memory options
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO);
if (cfg.rtc_dboost_fpd) {
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
@ -113,11 +117,6 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
}
//cancel digital pu force
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
/* If this mask is enabled, all soc memories cannot enter power down mode */
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
@ -128,12 +127,19 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
//cancel digital PADS force no iso
if (cfg.cpu_waiti_clk_gate) {
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
} else {
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
}

37
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@ -27,6 +27,8 @@
#include "soc/rtc.h"
#include "regi2c_ctrl.h"
#define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
/**
* Configure whether certain peripherals are powered up in sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -35,7 +37,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
@ -47,16 +48,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
if (cfg.sram_fpu) {
REG_SET_FIELD(SYSTEM_SRAM_CTRL_2_REG, SYSTEM_SRAM_POWER_UP, SYSTEM_SRAM_POWER_UP);
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
} else {
REG_SET_FIELD(SYSTEM_SRAM_CTRL_2_REG, SYSTEM_SRAM_POWER_UP, 0);
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0);
}
if (cfg.rom_ram_fpu) {
SET_PERI_REG_MASK(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_DRAM0_POWER_UP);
REG_SET_FIELD(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_POWER_UP, SYSTEM_ROM_IRAM0_POWER_UP);
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP);
} else {
CLEAR_PERI_REG_MASK(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_DRAM0_POWER_UP);
REG_SET_FIELD(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_POWER_UP, 0);
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0);
}
}
@ -74,22 +73,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
}
if (cfg.rtc_fastmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
}
if (cfg.rtc_slowmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
}
@ -105,6 +96,22 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
if (cfg.bt_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
}
if (cfg.cpu_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
}
if (cfg.dig_peri_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);

8
components/esp_rom/CMakeLists.txt
View File

@ -28,8 +28,7 @@ if(BOOTLOADER_BUILD)
rom_linker_script("spiflash")
elseif(target STREQUAL "esp32s3")
rom_linker_script("newlib-funcs")
rom_linker_script("spiflash")
rom_linker_script("newlib")
elseif(target STREQUAL "esp32c3")
rom_linker_script("newlib")
@ -77,9 +76,8 @@ else() # Regular app build
target_sources(${COMPONENT_LIB} PRIVATE "esp32s2/usb_descriptors.c")
elseif(target STREQUAL "esp32s3")
rom_linker_script("newlib-funcs")
rom_linker_script("newlib-data")
rom_linker_script("spiflash")
rom_linker_script("newlib")
rom_linker_script("version")
if(CONFIG_NEWLIB_NANO_FORMAT)
rom_linker_script("newlib-nano")

8
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View File

@ -32,10 +32,12 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
/* so here we directly assign the symbols with the ROM API address */
PROVIDE ( esp_rom_md5_init = 0x400376a0 );
PROVIDE ( esp_rom_md5_update = 0x400376c0 );
PROVIDE ( esp_rom_md5_final = 0x40037740 );
PROVIDE ( esp_rom_md5_init = 0x40001ac4 );
PROVIDE ( esp_rom_md5_update = 0x40001ad0 );
PROVIDE ( esp_rom_md5_final = 0x40001adc );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );

4273
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
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File diff suppressed because it is too large Load Diff

200
components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld
View File

@ -1,99 +1,105 @@
/**
* Unlike other ROM functions which declare weak symbols using PROVIDE,
* these libgcc functions are exported using assignment, which declare strong symbols.
/* ROM function interface esp32s3.rom.libgcc.ld for esp32s3
*
* Note: These ROM functions are always linked instead of the ones provided by libgcc.a.
*
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
__absvdi2 = 0x40037f14;
__absvsi2 = 0x40037f00;
__adddf3 = 0x4003bd5c;
__addsf3 = 0x4003b9f0;
__addvdi3 = 0x4003c488;
__addvsi3 = 0x4003c464;
__ashldi3 = 0x40055928;
__ashrdi3 = 0x40055940;
__bswapdi2 = 0x40039054;
__bswapsi2 = 0x4003902c;
__clear_cache = 0x40037ef8;
__clrsbdi2 = 0x400390c8;
__clrsbsi2 = 0x400390b0;
__clzdi2 = 0x40055bbc;
__clzsi2 = 0x400558f8;
__cmpdi2 = 0x40037eb8;
__ctzdi2 = 0x40055bd0;
__ctzsi2 = 0x40055900;
__divdc3 = 0x40038b74;
__divdf3 = 0x4003c120;
__divdi3 = 0x40055bf0;
__divsc3 = 0x400388d4;
__divsf3 = 0x40055974;
__divsi3 = 0x400558c8;
__eqdf2 = 0x40037d40;
__eqsf2 = 0x40037a0c;
__extendsfdf2 = 0x4003c400;
__ffsdi2 = 0x40055b98;
__ffssi2 = 0x40055914;
__fixdfdi = 0x4003c290;
__fixdfsi = 0x4003c244;
__fixsfdi = 0x4003bc18;
__fixsfsi = 0x4003bbd8;
__fixunsdfsi = 0x4003c2fc;
__fixunssfdi = 0x4003bcd0;
__fixunssfsi = 0x4003bc78;
__floatdidf = 0x40055af4;
__floatdisf = 0x40055a2c;
__floatsidf = 0x40055ab0;
__floatsisf = 0x400559dc;
__floatundidf = 0x40055ae4;
__floatundisf = 0x40055a1c;
__floatunsidf = 0x40055aa4;
__floatunsisf = 0x400559d0;
__gcc_bcmp = 0x40039100;
__gedf2 = 0x40037e00;
__gesf2 = 0x40037aa4;
__gtdf2 = 0x40037d74;
__gtsf2 = 0x40037a38;
__ledf2 = 0x40037d9c;
__lesf2 = 0x40037a58;
__lshrdi3 = 0x4005595c;
__ltdf2 = 0x40037e28;
__ltsf2 = 0x40037ac4;
__moddi3 = 0x40055eb8;
__modsi3 = 0x400558d0;
__muldc3 = 0x4003829c;
__muldf3 = 0x40037c24;
__muldi3 = 0x40055b68;
__mulsc3 = 0x40037fd8;
__mulsf3 = 0x40037960;
__mulsi3 = 0x400558c0;
__mulvdi3 = 0x4003c548;
__mulvsi3 = 0x4003c530;
__nedf2 = 0x40037d40;
__negdf2 = 0x40037b38;
__negdi2 = 0x40055b80;
__negsf2 = 0x4003b9c8;
__negvdi2 = 0x4003c664;
__negvsi2 = 0x4003c644;
__nesf2 = 0x40037a0c;
__nsau_data = 0x3ff07430;
__paritysi2 = 0x4003c730;
__popcountdi2 = 0x4003c6d8;
__popcountsi2 = 0x4003c6a0;
__popcount_tab = 0x3ff07430;
__powidf2 = 0x40037f74;
__powisf2 = 0x40037f34;
__subdf3 = 0x4003beb0;
__subsf3 = 0x4003bad8;
__subvdi3 = 0x4003c4ec;
__subvsi3 = 0x4003c4c8;
__truncdfsf2 = 0x4003c35c;
__ucmpdi2 = 0x40037ed8;
__udivdi3 = 0x40056160;
__udivmoddi4 = 0x40039140;
__udivsi3 = 0x400558d8;
__udiv_w_sdiv = 0x40039138;
__umoddi3 = 0x400563e4;
__umodsi3 = 0x400558e0;
__umulsidi3 = 0x400558e8;
__unorddf2 = 0x40037e8c;
__unordsf2 = 0x40037b10;
/***************************************
Group libgcc
***************************************/
/* Functions */
__absvdi2 = 0x40001fd4;
__absvsi2 = 0x40001fe0;
__adddf3 = 0x40001fec;
__addsf3 = 0x40001ff8;
__addvdi3 = 0x40002004;
__addvsi3 = 0x40002010;
__ashldi3 = 0x4000201c;
__ashrdi3 = 0x40002028;
__bswapdi2 = 0x40002034;
__bswapsi2 = 0x40002040;
__clear_cache = 0x4000204c;
__clrsbdi2 = 0x40002058;
__clrsbsi2 = 0x40002064;
__clzdi2 = 0x40002070;
__clzsi2 = 0x4000207c;
__cmpdi2 = 0x40002088;
__ctzdi2 = 0x40002094;
__ctzsi2 = 0x400020a0;
__divdc3 = 0x400020ac;
__divdf3 = 0x400020b8;
__divdi3 = 0x400020c4;
__divsc3 = 0x400020d0;
__divsf3 = 0x400020dc;
__divsi3 = 0x400020e8;
__eqdf2 = 0x400020f4;
__eqsf2 = 0x40002100;
__extendsfdf2 = 0x4000210c;
__ffsdi2 = 0x40002118;
__ffssi2 = 0x40002124;
__fixdfdi = 0x40002130;
__fixdfsi = 0x4000213c;
__fixsfdi = 0x40002148;
__fixsfsi = 0x40002154;
__fixunsdfsi = 0x40002160;
__fixunssfdi = 0x4000216c;
__fixunssfsi = 0x40002178;
__floatdidf = 0x40002184;
__floatdisf = 0x40002190;
__floatsidf = 0x4000219c;
__floatsisf = 0x400021a8;
__floatundidf = 0x400021b4;
__floatundisf = 0x400021c0;
__floatunsidf = 0x400021cc;
__floatunsisf = 0x400021d8;
__gcc_bcmp = 0x400021e4;
__gedf2 = 0x400021f0;
__gesf2 = 0x400021fc;
__gtdf2 = 0x40002208;
__gtsf2 = 0x40002214;
__ledf2 = 0x40002220;
__lesf2 = 0x4000222c;
__lshrdi3 = 0x40002238;
__ltdf2 = 0x40002244;
__ltsf2 = 0x40002250;
__moddi3 = 0x4000225c;
__modsi3 = 0x40002268;
__muldc3 = 0x40002274;
__muldf3 = 0x40002280;
__muldi3 = 0x4000228c;
__mulsc3 = 0x40002298;
__mulsf3 = 0x400022a4;
__mulsi3 = 0x400022b0;
__mulvdi3 = 0x400022bc;
__mulvsi3 = 0x400022c8;
__nedf2 = 0x400022d4;
__negdf2 = 0x400022e0;
__negdi2 = 0x400022ec;
__negsf2 = 0x400022f8;
__negvdi2 = 0x40002304;
__negvsi2 = 0x40002310;
__nesf2 = 0x4000231c;
__paritysi2 = 0x40002328;
__popcountdi2 = 0x40002334;
__popcountsi2 = 0x40002340;
__powidf2 = 0x4000234c;
__powisf2 = 0x40002358;
__subdf3 = 0x40002364;
__subsf3 = 0x40002370;
__subvdi3 = 0x4000237c;
__subvsi3 = 0x40002388;
__truncdfsf2 = 0x40002394;
__ucmpdi2 = 0x400023a0;
__udivdi3 = 0x400023ac;
__udivmoddi4 = 0x400023b8;
__udivsi3 = 0x400023c4;
__udiv_w_sdiv = 0x400023d0;
__umoddi3 = 0x400023dc;
__umodsi3 = 0x400023e8;
__unorddf2 = 0x400023f4;
__unordsf2 = 0x40002400;

19
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-data.ld
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@ -1,19 +0,0 @@
/**
* These are the .bss/.data symbols used by newlib functions present in ESP32S3 ROM.
* See also esp32s3.rom.newlib-funcs.ld for the list of general newlib functions.
*
* Unlike other ROM functions which declare weak symbols using PROVIDE,
* newlib related functions are exported using assignment, which declare strong symbols.
*
* Note: These ROM data are always linked instead of the ones provided by libc.a.
*/
_ctype_ = 0x3ff0732c;
__default_global_locale = 0x3ff071c0;
_global_impure_ptr = 0x3fcefcdc;
__global_locale_ptr = 0x3fcefccc;
_PathLocale = 0x3fcefcd0;
__sf_fake_stderr = 0x3ff0c524;
__sf_fake_stdin = 0x3ff0c564;
__sf_fake_stdout = 0x3ff0c544;
__sinit_recursive_mutex = 0x3fcefcd4;
__sfp_recursive_mutex = 0x3fcefcd8;

129
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-funcs.ld
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@ -1,129 +0,0 @@
/**
* These are the newlib functions present in ESP32S3 ROM.
* See also esp32s3.rom.newlib-data.ld for the list of .data/.bss symbols used by these functions,
* See also esp32s3.rom.newlib-nano.ld for "nano" versions of printf/scanf family of functions.
*
* Unlike other ROM functions which declare weak symbols using PROVIDE,
* newlib related functions are exported using assignment, which declare strong symbols.
*
* Note: These ROM functions are always linked instead of the ones provided by libc.a.
*/
abs = 0x40032344;
__ascii_mbtowc = 0x40039ec4;
__ascii_wctomb = 0x40033cb0;
__assert = 0x40054a5c;
__assert_func = 0x40054a30;
atoi = 0x40032984;
_atoi_r = 0x40032994;
atol = 0x400329ac;
_atol_r = 0x400329bc;
bzero = 0x40039d84;
_cleanup_r = 0x40054a6c;
creat = 0x40039d48;
div = 0x4003234c;
fclose = 0x40054e9c;
_fclose_r = 0x40054da4;
fflush = 0x40033fd8;
_fflush_r = 0x40033f50;
__fp_unlock_all = 0x40054cd4;
__fputwc = 0x40033b2c;
fputwc = 0x40033c40;
_fputwc_r = 0x40033bc0;
_fwalk = 0x40056670;
_fwalk_reent = 0x400566b0;
isalnum = 0x40039d94;
isalpha = 0x40039da4;
isascii = 0x4005546c;
_isatty_r = 0x40039d5c;
isblank = 0x40039db4;
iscntrl = 0x40039dd4;
isdigit = 0x40039dec;
isgraph = 0x40039e24;
islower = 0x40039e04;
isprint = 0x40039e3c;
ispunct = 0x40039e50;
isspace = 0x40039e68;
isupper = 0x40039e80;
__itoa = 0x40032938;
itoa = 0x40032974;
labs = 0x40032370;
ldiv = 0x40032378;
__locale_ctype_ptr = 0x40034050;
__locale_ctype_ptr_l = 0x40034048;
__locale_mb_cur_max = 0x40034030;
longjmp = 0x400322d0;
_mbtowc_r = 0x40039e9c;
memccpy = 0x40039ee8;
memchr = 0x40039f5c;
memcmp = 0x40055480;
memcpy = 0x40055528;
memmove = 0x40055620;
memrchr = 0x40039ff8;
memset = 0x40055710;
qsort = 0x4003239c;
rand_r = 0x4003a170;
__sclose = 0x40054d90;
__seofread = 0x40054d1c;
setjmp = 0x4003226c;
setlocale = 0x40034068;
_setlocale_r = 0x40033ffc;
__sflush_r = 0x40033dc8;
__sfmoreglue = 0x40054ab4;
__sfp = 0x40054bdc;
__sfp_lock_acquire = 0x40054c8c;
__sfp_lock_release = 0x40054c98;
__sfvwrite_r = 0x40033674;
__sinit = 0x40054af4;
__sinit_lock_acquire = 0x40054ca4;
__sinit_lock_release = 0x40054cb0;
__smakebuf_r = 0x40033d28;
srand = 0x4003a094;
__sread = 0x40054cec;
__sseek = 0x40054d5c;
strcasecmp = 0x4003a1bc;
strcasestr = 0x4003a850;
strcat = 0x4003aba8;
strchr = 0x4003abec;
strcmp = 0x4003acd8;
strcoll = 0x4003adfc;
strcpy = 0x4003ae10;
strcspn = 0x4005575c;
strdup = 0x4003aea0;
_strdup_r = 0x4003aeb4;
strlcat = 0x4003aed4;
strlcpy = 0x40055798;
strlen = 0x4003af3c;
strlwr = 0x4003afa0;
strncasecmp = 0x4003afd0;
strncat = 0x4003b028;
strncmp = 0x4003b088;
strncpy = 0x4003b178;
strndup = 0x4003b254;
_strndup_r = 0x4003b268;
strnlen = 0x400557d8;
strrchr = 0x4003b2b8;
strsep = 0x4003b2e4;
strspn = 0x4005580c;
strstr = 0x4003b674;
__strtok_r = 0x40055848;
strtok_r = 0x400558a4;
strtol = 0x40032b14;
strtol_l = 0x40032afc;
_strtol_r = 0x40032ad8;
strtoul = 0x40032c84;
strtoul_l = 0x40032c6c;
_strtoul_r = 0x40032c48;
strupr = 0x4003b8bc;
__swbuf = 0x40033a34;
__swbuf_r = 0x4003396c;
__swhatbuf_r = 0x40033cd4;
__swrite = 0x40054d24;
__swsetup_r = 0x40033a48;
toascii = 0x400558b8;
tolower = 0x4003b990;
toupper = 0x4003b9ac;
__utoa = 0x400321f4;
utoa = 0x4003225c;
wcrtomb = 0x40033618;
_wcrtomb_r = 0x400335c0;
_wctomb_r = 0x40033c88;

47
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld
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@ -1,28 +1,27 @@
/**
* These are the printf/scanf related newlib functions present in ESP32S3 ROM.
* These functions are compiled with newlib "nano" format option.
* As such, they don't support 64-bit integer formats.
* Floating point formats are supported by setting _printf_float and
* _scanf_float entries in syscall table. This is done automatically by startup code.
/* ROM function interface esp32s3.rom.newlib-nano.ld for esp32s3
*
* See also esp32s3.rom.newlib-data.ld for the list of .data/.bss symbols used by newlib functions.
* See also esp32s3.rom.newlib-funcs.ld for the list of general newlib functions.
*
* Unlike other ROM functions which declare weak symbols using PROVIDE,
* newlib related functions are exported using assignment, which declare strong symbols.
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
*
* Note: These ROM functions are always linked instead of the ones provided by libc.a.
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_printf_common = 0x40033114;
_printf_i = 0x40033214;
__sfputs_r = 0x40032d44;
fiprintf = 0x40032cdc;
_fiprintf_r = 0x40032cac;
__fp_lock_all = 0x40054cbc;
fprintf = 0x40032cdc;
_fprintf_r = 0x40032cac;
__sprint_r = 0x40032d90;
vfiprintf = 0x400330f4;
_vfiprintf_r = 0x40032df8;
vfprintf = 0x400330f4;
_vfprintf_r = 0x40032df8;
/***************************************
Group newlib_nano_format
***************************************/
/* Functions */
__sprint_r = 0x400013f8;
_fiprintf_r = 0x40001404;
_fprintf_r = 0x40001410;
_printf_common = 0x4000141c;
_printf_i = 0x40001428;
_vfiprintf_r = 0x40001434;
_vfprintf_r = 0x40001440;
fiprintf = 0x4000144c;
fprintf = 0x40001458;
printf = 0x40001464;
vfiprintf = 0x40001470;
vfprintf = 0x4000147c;

94
components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld Normal file
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@ -0,0 +1,94 @@
/* ROM function interface esp32s3.rom.newlib.ld for esp32s3
*
*
* Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40001068;
memset = 0x40001074;
memcpy = 0x40001080;
memmove = 0x4000108c;
memcmp = 0x40001098;
strcpy = 0x400010a4;
strncpy = 0x400010b0;
strcmp = 0x400010bc;
strncmp = 0x400010c8;
strlen = 0x400010d4;
strstr = 0x400010e0;
bzero = 0x400010ec;
_isatty_r = 0x400010f8;
sbrk = 0x40001104;
isalnum = 0x40001110;
isalpha = 0x4000111c;
isascii = 0x40001128;
isblank = 0x40001134;
iscntrl = 0x40001140;
isdigit = 0x4000114c;
islower = 0x40001158;
isgraph = 0x40001164;
isprint = 0x40001170;
ispunct = 0x4000117c;
isspace = 0x40001188;
isupper = 0x40001194;
toupper = 0x400011a0;
tolower = 0x400011ac;
toascii = 0x400011b8;
memccpy = 0x400011c4;
memchr = 0x400011d0;
memrchr = 0x400011dc;
strcasecmp = 0x400011e8;
strcasestr = 0x400011f4;
strcat = 0x40001200;
strdup = 0x4000120c;
strchr = 0x40001218;
strcspn = 0x40001224;
strcoll = 0x40001230;
strlcat = 0x4000123c;
strlcpy = 0x40001248;
strlwr = 0x40001254;
strncasecmp = 0x40001260;
strncat = 0x4000126c;
strndup = 0x40001278;
strnlen = 0x40001284;
strrchr = 0x40001290;
strsep = 0x4000129c;
strspn = 0x400012a8;
strtok_r = 0x400012b4;
strupr = 0x400012c0;
longjmp = 0x400012cc;
setjmp = 0x400012d8;
abs = 0x400012e4;
div = 0x400012f0;
labs = 0x400012fc;
ldiv = 0x40001308;
qsort = 0x40001314;
rand_r = 0x40001320;
rand = 0x4000132c;
srand = 0x40001338;
utoa = 0x40001344;
itoa = 0x40001350;
atoi = 0x4000135c;
atol = 0x40001368;
strtol = 0x40001374;
strtoul = 0x40001380;
PROVIDE( fflush = 0x4000138c );
PROVIDE( _fflush_r = 0x40001398 );
PROVIDE( _fwalk = 0x400013a4 );
PROVIDE( _fwalk_reent = 0x400013b0 );
PROVIDE( __smakebuf_r = 0x400013bc );
PROVIDE( __swhatbuf_r = 0x400013c8 );
PROVIDE( __swbuf_r = 0x400013d4 );
__swbuf = 0x400013e0;
PROVIDE( __swsetup_r = 0x400013ec );
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fceffe0;
_global_impure_ptr = 0x3fceffdc;

25
components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld
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@ -1,25 +0,0 @@
/**
* SPI flash driver function, compatibility names.
*/
PROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus);
PROVIDE ( g_ticks_per_us_pro = g_ticks_per_us );
PROVIDE ( g_rom_flashchip = SPI_flashchip_data );
PROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data );
PROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg );
PROVIDE ( esp_rom_spiflash_read_status = SPI_read_status );
PROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high );
PROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read );
PROVIDE ( esp_rom_spiflash_write = SPIWrite );
PROVIDE ( esp_rom_spiflash_read = SPIRead );
PROVIDE ( esp_rom_spiflash_write_encrypted_disable = SPI_Write_Encrypt_Disable );
PROVIDE ( esp_rom_spiflash_write_encrypted_enable = SPI_Write_Encrypt_Enable );
PROVIDE ( esp_rom_spiflash_config_clk = SPIClkConfig );
PROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO );
PROVIDE ( esp_rom_spiflash_unlock = SPIUnlock );
PROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector );
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
PROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle );
PROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig );
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
PROVIDE ( esp_rom_spiflash_write_encrypted = SPI_Encrypt_Write );

8
components/esp_rom/esp32s3/ld/esp32s3.rom.version.ld Normal file
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@ -0,0 +1,8 @@
/* ROM version variables for esp32s3
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x40000570;
_rom_eco_version = 0x40000574;

43
components/esp_rom/include/esp32s3/rom/libc_stubs.h
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@ -39,23 +39,24 @@ extern "C" {
* to actual implementations of corresponding syscalls.
*
*/
struct syscall_stub_table {
struct _reent *(*__getreent)(void);
void *(*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void *);
void *(*_realloc_r)(struct _reent *r, void *, size_t);
void *(*_calloc_r)(struct _reent *r, size_t, size_t);
struct syscall_stub_table
{
struct _reent* (*__getreent)(void);
void* (*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void*);
void* (*_realloc_r)(struct _reent *r, void*, size_t);
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
void (*_abort)(void);
int (*_system_r)(struct _reent *r, const char *);
int (*_rename_r)(struct _reent *r, const char *, const char *);
int (*_system_r)(struct _reent *r, const char*);
int (*_rename_r)(struct _reent *r, const char*, const char*);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r);
int (*_unlink_r)(struct _reent *r, const char *);
int (*_link_r)(struct _reent *r, const char *, const char *);
int (*_stat_r)(struct _reent *r, const char *, struct stat *);
int (*_unlink_r)(struct _reent *r, const char*);
int (*_link_r)(struct _reent *r, const char*, const char*);
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
int (*_fstat_r)(struct _reent *r, int, struct stat *);
void *(*_sbrk_r)(struct _reent *r, ptrdiff_t);
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
int (*_getpid_r)(struct _reent *r);
int (*_kill_r)(struct _reent *r, int, int);
void (*_exit_r)(struct _reent *r, int);
@ -64,6 +65,18 @@ struct syscall_stub_table {
int (*_write_r)(struct _reent *r, int, const void *, int);
int (*_lseek_r)(struct _reent *r, int, int, int);
int (*_read_r)(struct _reent *r, int, void *, int);
#ifdef _RETARGETABLE_LOCKING
void (*_retarget_lock_init)(_LOCK_T *lock);
void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
void (*_retarget_lock_close)(_LOCK_T lock);
void (*_retarget_lock_close_recursive)(_LOCK_T lock);
void (*_retarget_lock_acquire)(_LOCK_T lock);
void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
int (*_retarget_lock_try_acquire)(_LOCK_T lock);
int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
void (*_retarget_lock_release)(_LOCK_T lock);
void (*_retarget_lock_release_recursive)(_LOCK_T lock);
#else
void (*_lock_init)(_lock_t *lock);
void (*_lock_init_recursive)(_lock_t *lock);
void (*_lock_close)(_lock_t *lock);
@ -74,8 +87,12 @@ struct syscall_stub_table {
int (*_lock_try_acquire_recursive)(_lock_t *lock);
void (*_lock_release)(_lock_t *lock);
void (*_lock_release_recursive)(_lock_t *lock);
int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap);
#endif
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn));
void (*__sinit) (struct _reent *r);
void (*_cleanup_r) (struct _reent* r);
};
extern struct syscall_stub_table *syscall_table_ptr;

84
components/esp_rom/include/esp32s3/rom/rom_layout.h Normal file
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@ -0,0 +1,84 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SUPPORT_WIFI 1
#define SUPPORT_BTDM 1
/* Structure and functions for returning ROM global layout
*
* This is for address symbols defined in the linker script, which may change during ECOs.
*/
typedef struct {
void *dram0_stack_shared_mem_start;
void *dram0_rtos_reserved_start;
void *stack_sentry;
void *stack;
void *stack_sentry_app;
void *stack_app;
/* BTDM data */
void *data_start_btdm;
void *data_end_btdm;
void *bss_start_btdm;
void *bss_end_btdm;
void *data_start_btdm_rom;
void *data_end_btdm_rom;
void *data_start_interface_btdm;
void *data_end_interface_btdm;
void *bss_start_interface_btdm;
void *bss_end_interface_btdm;
/* Other DRAM ranges */
#if SUPPORT_BTDM || SUPPORT_WIFI
void *dram_start_phyrom;
void *dram_end_phyrom;
#endif
#if SUPPORT_WIFI
void *dram_start_coexist;
void *dram_end_coexist;
void *dram_start_net80211;
void *dram_end_net80211;
void *dram_start_pp;
void *dram_end_pp;
void *data_start_interface_coexist;
void *data_end_interface_coexist;
void *bss_start_interface_coexist;
void *bss_end_interface_coexist;
void *data_start_interface_net80211;
void *data_end_interface_net80211;
void *bss_start_interface_net80211;
void *bss_end_interface_net80211;
void *data_start_interface_pp;
void *data_end_interface_pp;
void *bss_start_interface_pp;
void *bss_end_interface_pp;
#endif
void *dram_start_usbdev_rom;
void *dram_end_usbdev_rom;
void *dram_start_uart_rom;
void *dram_end_uart_rom;
} ets_rom_layout_t;
extern const ets_rom_layout_t * const ets_rom_layout_p;
#ifdef __cplusplus
}
#endif

43
components/esp_rom/include/esp32s3/rom/spi_flash.h
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@ -148,6 +148,7 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
@ -548,14 +549,42 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
*
*/
extern esp_rom_spiflash_chip_t g_rom_flashchip;
typedef void (* spi_flash_func_t)(void);
typedef SpiFlashOpResult (* spi_flash_op_t)(void);
typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
/**
* @}
*/
typedef struct {
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
/* Defined in the interfaces file, default value is rom_default_spiflash_legacy_flash_func */
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
#ifdef __cplusplus
}

262
components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h Normal file
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@ -0,0 +1,262 @@
/*******************************************************************************
*
* Copyright(c) 2015,2016 Intel Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void cdc_acm_device;
extern cdc_acm_device *uart_acm_dev;
#define ACM_BYTES_PER_TX 64
//ACM statuses are negative to distinguish from USB_DC_* status codes
#define ACM_STATUS_LINESTATE_CHANGED -1
#define ACM_STATUS_LINECODING_CHANGED -2
#define ACM_STATUS_TX -3
#define ACM_STATUS_RX -4
typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status);
/**
* @brief Get amount of received characters in buffer
*
* @returns character count
*/
int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev);
/*
* @brief Poll the device for input.
*
* @return -ENOTSUP Since underlying USB device controller always uses
* interrupts, polled mode UART APIs are not implemented for the UART interface
* exported by CDC ACM driver. Apps should use fifo_read API instead.
*/
int cdc_acm_poll_in(cdc_acm_device *dev, unsigned char *c);
/*
* @brief Output a character in polled mode.
*
* The UART poll method for USB UART is simulated by waiting till
* we get the next BULK In upcall from the USB device controller or 100 ms.
*
* @return the same character which is sent
*/
unsigned char cdc_acm_poll_out(cdc_acm_device *dev, unsigned char c);
/**
* @brief Fill FIFO with data
*
* @param dev CDC ACM device struct.
* @param tx_data Data to transmit.
* @param len Number of bytes to send.
*
* @return Number of bytes sent.
*/
int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len);
/**
* @brief Read data from FIFO
*
* @param dev CDC ACM device struct.
* @param rx_data Pointer to data container.
* @param size Container size.
*
* @return Number of bytes read.
*/
int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size);
/**
* @brief Enable TX interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A.
*/
void cdc_acm_irq_tx_enable(cdc_acm_device *dev);
/**
* @brief Disable TX interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A.
*/
void cdc_acm_irq_tx_disable(cdc_acm_device *dev);
/**
* @brief Check if Tx IRQ has been raised
*
* @param dev CDC ACM device struct.
*
* @return 1 if a Tx IRQ is pending, 0 otherwise.
*/
int cdc_acm_irq_tx_ready(cdc_acm_device *dev);
/**
* @brief Enable RX interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A
*/
void cdc_acm_irq_rx_enable(cdc_acm_device *dev);
/**
* @brief Disable RX interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A.
*/
void cdc_acm_irq_rx_disable(cdc_acm_device *dev);
/**
* @brief Enable line state interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A.
*/
void cdc_acm_irq_state_enable(cdc_acm_device *dev);
/**
* @brief Disable line state interrupt
*
* @param dev CDC ACM device struct.
*
* @return N/A.
*/
void cdc_acm_irq_state_disable(cdc_acm_device *dev);
/**
* @brief Check if Rx IRQ has been raised
*
* @param dev CDC ACM device struct.
*
* @return 1 if an IRQ is ready, 0 otherwise.
*/
int cdc_acm_irq_rx_ready(cdc_acm_device *dev);
/**
* @brief Check if Tx or Rx IRQ is pending
*
* @param dev CDC ACM device struct.
*
* @return 1 if a Tx or Rx IRQ is pending, 0 otherwise.
*/
int cdc_acm_irq_is_pending(cdc_acm_device *dev);
/**
* @brief Set the callback function pointer for IRQ.
*
* @param dev CDC ACM device struct.
* @param cb Callback function pointer.
*
* @return N/A
*/
void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb);
/**
* @brief Manipulate line control for UART.
*
* @param dev CDC ACM device struct
* @param ctrl The line control to be manipulated
* @param val Value to set the line control
*
* @return 0 if successful, failed otherwise.
*/
int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val);
/**
* @brief Manipulate line control for UART.
*
* @param dev CDC ACM device struct
* @param ctrl The line control to be manipulated
* @param val Value to set the line control
*
* @return 0 if successful, failed otherwise.
*/
int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val);
/**
* @brief Initialize UART channel
*
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* @param mem_chunk Memory chunk to use for internal use
* @param mem_chunk_size Size of the memory chunk in bytes
*
* @return dev or NULL
*/
cdc_acm_device *cdc_acm_init(void *mem_chunk, int mem_chunk_size);
/** Common line controls for UART.*/
#define LINE_CTRL_BAUD_RATE (1 << 0)
#define LINE_CTRL_RTS (1 << 1)
#define LINE_CTRL_DTR (1 << 2)
#define LINE_CTRL_DCD (1 << 3)
#define LINE_CTRL_DSR (1 << 4)
/* Common communication errors for UART.*/
/** @brief Overrun error */
#define UART_ERROR_OVERRUN (1 << 0)
/** @brief Parity error */
#define UART_ERROR_PARITY (1 << 1)
/** @brief Framing error */
#define UART_ERROR_FRAMING (1 << 2)
/**
* @brief Break interrupt error:
*
* A break interrupt was received. This happens when the serial input is
* held at a logic '0' state for longer than the sum of start time + data bits
* + parity + stop bits.
*/
#define UART_ERROR_BREAK (1 << 3)
#ifdef __cplusplus
}
#endif

30
components/esp_rom/include/esp32s3/rom/usb/chip_usb_dw_wrapper.h Normal file
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@ -0,0 +1,30 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
int chip_usb_dw_init(void);
int chip_usb_dw_did_persist(void);
void chip_usb_dw_prepare_persist(void);
uint32_t chip_usb_get_persist_flags(void);
void chip_usb_set_persist_flags(uint32_t flags);
#ifdef __cplusplus
}
#endif

180
components/esp_rom/include/esp32s3/rom/usb/cpio.h Normal file
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@ -0,0 +1,180 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* Archive to parse cpio data in the newc and crc formats. Generate a cpio archive like that by e.g.
* find . | cpio -o -H newc > archive.cpio
*/
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define CPIO_MODE_FILETYPE_MASK 0xF000
#define CPIO_MODE_FILETYPE_SOCKET 0xC000
#define CPIO_MODE_FILETYPE_SYMLINK 0xA000
#define CPIO_MODE_FILETYPE_REGULAR 0x8000
#define CPIO_MODE_FILETYPE_BLOCKDEV 0x6000
#define CPIO_MODE_FILETYPE_DIR 0x4000
#define CPIO_MODE_FILETYPE_CHARDEV 0x2000
#define CPIO_MODE_FILETYPE_FIFO 0x1000
#define CPIO_MODE_SUID 0x0800
#define CPIO_MODE_SGID 0x0400
#define CPIO_MODE_STICKY 0x0200
typedef struct {
size_t filesize;
char *name;
uint32_t mode;
uint32_t check;
} cpio_file_t;
typedef enum {
CPIO_RET_MORE = 0,
CPIO_RET_DONE,
CPIO_RET_ERR
} cpio_ret_t;
typedef struct cpio_handle_data_t cpio_handle_data_t;
typedef cpio_handle_data_t *cpio_handle_t;
typedef enum {
CPIO_RSN_FILE_ALL = 0,
CPIO_RSN_FILE_INITIAL,
CPIO_RSN_FILE_MORE,
CPIO_RSN_FILE_END
} cpio_callback_reason_t;
/**
* Callback for cpio file data.
*
* This callback will be called by the library to indicate data for a file is available.
*
* For files in the cpio archive that fit entirely in the internal buffer, or when no internal
* buffer is available, are entirely contained in the buffer fed to cpio_feed(), this callback
* is only called once, with reason=CPIO_RNS_FILE_ALL. fileinfo will contain the information
* for that specific file (name, size, ...), buff_offset will be 0, buff_len is the file
* size and buff contains all the information for the file.
*
* For files that do not fit in the buffer, this callback will be called multiple times.
* The initial time with reason=CPIO_RSN_FILE_INITIAL, when more data is available with
* CPIO_RSN_FILE_MORE and finally with CPIO_RSN_FILE_END. For these calls, fileinfo
* will again contain file information. buff will be the information contained in the
* file at offset buff_offset, and the lenght of this buffer will be in buff_len.
*
* The library guarantees to feed all file data to the callback consequitively, so
* within the same file, the buff_offset from a call will always be (buff_offset+buff_len)
* from the call before that. If cpio_start is
*
* The library also guarantees every file in the cpio archive will either generate a single
* callback call with CPIO_RSN_ALL, or multiple with in sequence CPIO_RSN_FILE_INITIAL, 0 or
* more CPIO_RSN_FILE_MORE and finally a CPIO_RSN_FILE_END.
*
* When a non-zero buffer size is passed to cpio_start, the library guarantees that all callback
* calls with a reason of CPIO_RSN_FILE_INITIAL and CPIO_RSN_FILE_MORE will have a buffer
* filled with exactly this amount of bytes.
*
*/
typedef void (*cpio_callback_t)(cpio_callback_reason_t reason, cpio_file_t *fileinfo, size_t buff_offset, size_t buff_len, char *buff, void *arg);
/**
* @brief Initialize a cpio handle.
*
* Call this to start parsing a cpio archive. You can set the callback that handles the
* files/data here.
*
* @param callback The callback that will handle the data of the files inside the cpio archive
*
* @param cbarg User-supplied argument. The callback will be called with this as an argument.
*
* @param buflen Length of internal buffer used.
* If this is zero, the callback will be called with data that lives in the data buffer
* supplied to the cpio library by whomever called cpio_feed(). Because this library has
* no power over that buffer, the callback can be passed as little as 1 and as many as
* INT_MAX bytes at a time.
* If this is non-zero, the library will allocate an internal buffer of this size. All
* cpio_feed()-calls will be rebuffered, and the callback is guaranteed to only be called
* with this many bytes in the buffer, given there's enough data in the file to fill it.
*
* @param memchunk Chunk of memory to allocate everything (handle, I/O buffer, filename buffer) in. Minimum size
* (estimate) is 160+buflen+sizeof(largest filename/path).
* @param memchunklen Size of the mem chunk
*
* @return
* - Success: A pointer to a cpio handle
* - Error: NULL
*
*/
cpio_handle_t cpio_start(cpio_callback_t callback, void *cbarg, size_t buflen, void *memchunk, int memchunklen);
/**
* @brief Feed data from a cpio archive into the library
*
* This routine is used to feed consecutive data of the cpio archive into the library. While processing,
* the library can call the callback function one or more times if needed.
*
* @param cpio Handle obtained by calling cpio_start()
*
* @param buffer Pointer to buffer containing cpio archive data
*
* @param len Length of the buffer, in bytes
*
* @return
* - CPIO_RET_MORE: CPIO archive isn't done yet, please feed more data.
* - CPIO_RET_DONE: CPUI archive is finished.
* - CPIO_RET_ERR: Invalid CPIO archive data; decoding aborted.
*
*/
cpio_ret_t cpio_feed(cpio_handle_t cpio, char *buffer, int len);
/**
* @brief Indicate there is no more cpio data to be fed into the archive
*
* This call is to be called when the source data is exhausted. Normally, the library can find the end of the
* cpio archive by looking for the end marker,
*
* @param timer_conf Pointer of LEDC timer configure struct
*
*
* @return
* - CPIO_RET_DONE on success
* - CPIO_RET_ERR when cpio archive is invalid
*
*/
cpio_ret_t cpio_done(cpio_handle_t cpio);
/**
* @brief Free the memory allocated for a cpio handle.
*
* @param cpio Handle obtained by calling cpio_start()
*
* @return
* - CPIO_RET_DONE on success
*
*/
cpio_ret_t cpio_destroy(cpio_handle_t cpio);
#ifdef __cplusplus
}
#endif

174
components/esp_rom/include/esp32s3/rom/usb/usb_cdc.h Normal file
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@ -0,0 +1,174 @@
/* usb_cdc.h - USB CDC-ACM and CDC-ECM public header */
/*
* Copyright (c) 2017 PHYTEC Messtechnik GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB Communications Device Class (CDC) public header
*
* Header follows the Class Definitions for
* Communications Devices Specification (CDC120-20101103-track.pdf),
* PSTN Devices Specification (PSTN120.pdf) and
* Ethernet Control Model Devices Specification (ECM120.pdf).
* Header is limited to ACM and ECM Subclasses.
*/
#pragma once
#include <stdint.h>
#include <sys/cdefs.h>
#ifdef __cplusplus
extern "C" {
#endif
/** CDC Specification release number in BCD format */
#define CDC_SRN_1_20 0x0120
/** Communications Class Subclass Codes */
#define ACM_SUBCLASS 0x02
#define ECM_SUBCLASS 0x06
#define EEM_SUBCLASS 0x0c
/** Communications Class Protocol Codes */
#define AT_CMD_V250_PROTOCOL 0x01
#define EEM_PROTOCOL 0x07
/**
* @brief Data Class Interface Codes
* @note CDC120-20101103-track.pdf, 4.5, Table 6
*/
#define DATA_INTERFACE_CLASS 0x0A
/**
* @brief Values for the bDescriptorType Field
* @note CDC120-20101103-track.pdf, 5.2.3, Table 12
*/
#define CS_INTERFACE 0x24
#define CS_ENDPOINT 0x25
/**
* @brief bDescriptor SubType for Communications
* Class Functional Descriptors
* @note CDC120-20101103-track.pdf, 5.2.3, Table 13
*/
#define HEADER_FUNC_DESC 0x00
#define CALL_MANAGEMENT_FUNC_DESC 0x01
#define ACM_FUNC_DESC 0x02
#define UNION_FUNC_DESC 0x06
#define ETHERNET_FUNC_DESC 0x0F
/**
* @brief PSTN Subclass Specific Requests
* for ACM devices
* @note PSTN120.pdf, 6.3, Table 13
*/
#define CDC_SEND_ENC_CMD 0x00
#define CDC_GET_ENC_RSP 0x01
#define SET_LINE_CODING 0x20
#define GET_LINE_CODING 0x21
#define SET_CONTROL_LINE_STATE 0x22
/** Control Signal Bitmap Values for SetControlLineState */
#define SET_CONTROL_LINE_STATE_RTS 0x02
#define SET_CONTROL_LINE_STATE_DTR 0x01
/** UART State Bitmap Values */
#define SERIAL_STATE_OVERRUN 0x40
#define SERIAL_STATE_PARITY 0x20
#define SERIAL_STATE_FRAMING 0x10
#define SERIAL_STATE_RING 0x08
#define SERIAL_STATE_BREAK 0x04
#define SERIAL_STATE_TX_CARRIER 0x02
#define SERIAL_STATE_RX_CARRIER 0x01
/**
* @brief Class-Specific Request Codes for Ethernet subclass
* @note ECM120.pdf, 6.2, Table 6
*/
#define SET_ETHERNET_MULTICAST_FILTERS 0x40
#define SET_ETHERNET_PM_FILTER 0x41
#define GET_ETHERNET_PM_FILTER 0x42
#define SET_ETHERNET_PACKET_FILTER 0x43
#define GET_ETHERNET_STATISTIC 0x44
/** Ethernet Packet Filter Bitmap */
#define PACKET_TYPE_MULTICAST 0x10
#define PACKET_TYPE_BROADCAST 0x08
#define PACKET_TYPE_DIRECTED 0x04
#define PACKET_TYPE_ALL_MULTICAST 0x02
#define PACKET_TYPE_PROMISCUOUS 0x01
/** Header Functional Descriptor */
struct cdc_header_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint16_t bcdCDC;
} __packed;
/** Union Interface Functional Descriptor */
struct cdc_union_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bControlInterface;
uint8_t bSubordinateInterface0;
} __packed;
/** Call Management Functional Descriptor */
struct cdc_cm_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
uint8_t bDataInterface;
} __packed;
/** Abstract Control Management Functional Descriptor */
struct cdc_acm_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
} __packed;
/** Data structure for GET_LINE_CODING / SET_LINE_CODING class requests */
struct cdc_acm_line_coding {
uint32_t dwDTERate;
uint8_t bCharFormat;
uint8_t bParityType;
uint8_t bDataBits;
} __packed;
/** Data structure for the notification about SerialState */
struct cdc_acm_notification {
uint8_t bmRequestType;
uint8_t bNotificationType;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
uint16_t data;
} __packed;
/** Ethernet Networking Functional Descriptor */
struct cdc_ecm_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t iMACAddress;
uint32_t bmEthernetStatistics;
uint16_t wMaxSegmentSize;
uint16_t wNumberMCFilters;
uint8_t bNumberPowerFilters;
} __packed;
#ifdef __cplusplus
}
#endif

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/***************************************************************************
*
*
* Copyright(c) 2015,2016 Intel Corporation.
* Copyright(c) 2017 PHYTEC Messtechnik GmbH
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/**
* @file
* @brief useful constants and macros for the USB application
*
* This file contains useful constants and macros for the USB applications.
*/
#pragma once
#include <stdint.h>
#include <sys/cdefs.h>
#ifdef __cplusplus
extern "C" {
#endif
#define BCD(x) ((((x) / 10) << 4) | ((x) / 10))
/* Descriptor size in bytes */
#define USB_DEVICE_DESC_SIZE 18
#define USB_CONFIGURATION_DESC_SIZE 9
#define USB_INTERFACE_DESC_SIZE 9
#define USB_ENDPOINT_DESC_SIZE 7
#define USB_STRING_DESC_SIZE 4
#define USB_HID_DESC_SIZE 9
#define USB_DFU_DESC_SIZE 9
#define USB_DEVICE_QUAL_DESC_SIZE 10
#define USB_INTERFACE_ASSOC_DESC_SIZE 8
/* Descriptor type */
#define USB_DEVICE_DESC 0x01
#define USB_CONFIGURATION_DESC 0x02
#define USB_STRING_DESC 0x03
#define USB_INTERFACE_DESC 0x04
#define USB_ENDPOINT_DESC 0x05
#define USB_DEVICE_QUAL_DESC 0x06
#define USB_INTERFACE_ASSOC_DESC 0x0B
#define USB_DEVICE_CAPABILITY_DESC 0x10
#define USB_HID_DESC 0x21
#define USB_HID_REPORT_DESC 0x22
#define USB_DFU_FUNCTIONAL_DESC 0x21
#define USB_ASSOCIATION_DESC 0x0B
#define USB_BINARY_OBJECT_STORE_DESC 0x0F
/* Useful define */
#define USB_1_1 0x0110
#define USB_2_0 0x0200
/* Set USB version to 2.1 so that the host will request the BOS descriptor */
#define USB_2_1 0x0210
#define BCDDEVICE_RELNUM (BCD(KERNEL_VERSION_MAJOR) << 8 | \
BCD(KERNEL_VERSION_MINOR))
/* 100mA max power, per 2mA units */
/* USB 1.1 spec indicates 100mA(max) per unit load, up to 5 loads */
#define MAX_LOW_POWER 0x32
#define MAX_HIGH_POWER 0xFA
/* bmAttributes:
* D7:Reserved, always 1,
* D6:Self-Powered -> 1,
* D5:Remote Wakeup -> 0,
* D4...0:Reserved -> 0
*/
#define USB_CONFIGURATION_ATTRIBUTES 0xC0
/* Classes */
#define COMMUNICATION_DEVICE_CLASS 0x02
#define COMMUNICATION_DEVICE_CLASS_DATA 0x0A
#define HID_CLASS 0x03
#define MASS_STORAGE_CLASS 0x08
#define WIRELESS_DEVICE_CLASS 0xE0
#define MISC_CLASS 0xEF
#define CUSTOM_CLASS 0xFF
#define DFU_DEVICE_CLASS 0xFE
/* Sub-classes */
#define CDC_NCM_SUBCLASS 0x0d
#define BOOT_INTERFACE_SUBCLASS 0x01
#define SCSI_TRANSPARENT_SUBCLASS 0x06
#define DFU_INTERFACE_SUBCLASS 0x01
#define RF_SUBCLASS 0x01
#define CUSTOM_SUBCLASS 0xFF
#define COMMON_SUBCLASS 0x02
/* Misc subclasses */
#define MISC_RNDIS_SUBCLASS 0x04
#define CDC_ABSTRACT_CONTROL_MODEL 0x02
/* Protocols */
#define V25TER_PROTOCOL 0x01
#define MOUSE_PROTOCOL 0x02
#define BULK_ONLY_PROTOCOL 0x50
#define DFU_RUNTIME_PROTOCOL 0x01
#define DFU_MODE_PROTOCOL 0x02
#define BLUETOOTH_PROTOCOL 0x01
/* CDC ACM protocols */
#define ACM_VENDOR_PROTOCOL 0xFF
/* Misc protocols */
#define MISC_ETHERNET_PROTOCOL 0x01
#define IAD_PROTOCOL 0x01
/** Standard Device Descriptor */
struct usb_device_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} __packed;
/** Unicode (UTF16LE) String Descriptor */
struct usb_string_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bString;
} __packed;
/** Association Descriptor */
struct usb_association_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bFirstInterface;
uint8_t bInterfaceCount;
uint8_t bFunctionClass;
uint8_t bFunctionSubClass;
uint8_t bFunctionProtocol;
uint8_t iFunction;
} __packed;
/** Standard Configuration Descriptor */
struct usb_cfg_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
} __packed;
/** Standard Interface Descriptor */
struct usb_if_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} __packed;
/** Standard Endpoint Descriptor */
struct usb_ep_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
} __packed;
struct string_descriptor_zero {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wBcdLang[];
} __packed;
struct string_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bString[];
} __packed;
#define ROM_MAX_CFG_DESC_CNT 1
struct rom_usb_descriptors {
const struct usb_device_descriptor *device_descr;
const void *config_descr[ROM_MAX_CFG_DESC_CNT];
int string_count; // including string_descriptor_zero
const struct string_descriptor_zero *string0_descr;
const struct string_descriptor *string_descrs[];
};
/* Descriptors defined in the ROM */
extern struct usb_device_descriptor general_device_descr;
extern const void* acm_config_descr;
extern const void* dfu_config_descr;
extern const struct string_descriptor str_manu_descr;
extern const struct string_descriptor str_prod_descr;
extern const struct string_descriptor_zero string0_descr;
extern const struct rom_usb_descriptors acm_usb_descriptors;
extern const struct rom_usb_descriptors dfu_usb_descriptors;
extern const struct rom_usb_descriptors *rom_usb_curr_desc;
#ifdef __cplusplus
}
#endif

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/* usb_dc.h - USB device controller driver interface */
/*
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB device controller APIs
*
* This file contains the USB device controller APIs. All device controller
* drivers should implement the APIs described in this file.
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* USB endpoint direction and number.
*/
#define USB_EP_DIR_MASK 0x80
#define USB_EP_DIR_IN 0x80
#define USB_EP_DIR_OUT 0x00
/**
* USB Driver Status Codes
*/
enum usb_dc_status_code {
USB_DC_ERROR, /* USB error reported by the controller */
USB_DC_RESET, /* USB reset */
/* USB connection established, hardware enumeration is completed */
USB_DC_CONNECTED,
USB_DC_CONFIGURED, /* USB configuration done */
USB_DC_DISCONNECTED, /* USB connection lost */
USB_DC_SUSPEND, /* USB connection suspended by the HOST */
USB_DC_RESUME, /* USB connection resumed by the HOST */
USB_DC_INTERFACE, /* USB interface selected */
USB_DC_SET_HALT, /* Set Feature ENDPOINT_HALT received */
USB_DC_CLEAR_HALT, /* Clear Feature ENDPOINT_HALT received */
USB_DC_UNKNOWN /* Initial USB connection status */
};
/**
* USB Endpoint Callback Status Codes
*/
enum usb_dc_ep_cb_status_code {
USB_DC_EP_SETUP, /* SETUP received */
/* Out transaction on this EP, data is available for read */
USB_DC_EP_DATA_OUT,
USB_DC_EP_DATA_IN, /* In transaction done on this EP */
};
/**
* USB Endpoint type
*/
enum usb_dc_ep_type {
USB_DC_EP_CONTROL = 0, /* Control type endpoint */
USB_DC_EP_ISOCHRONOUS, /* Isochronous type endpoint */
USB_DC_EP_BULK, /* Bulk type endpoint */
USB_DC_EP_INTERRUPT /* Interrupt type endpoint */
};
/**
* USB Endpoint Configuration.
*/
struct usb_dc_ep_cfg_data {
/** The number associated with the EP in the device
* configuration structure
* IN EP = 0x80 | \<endpoint number\>
* OUT EP = 0x00 | \<endpoint number\>
*/
uint8_t ep_addr;
uint16_t ep_mps; /** Endpoint max packet size */
enum usb_dc_ep_type ep_type; /** Endpoint type */
};
/**
* Callback function signature for the USB Endpoint status
*/
typedef void (*usb_dc_ep_callback)(uint8_t ep,
enum usb_dc_ep_cb_status_code cb_status);
/**
* Callback function signature for the device
*/
typedef void (*usb_dc_status_callback)(enum usb_dc_status_code cb_status,
uint8_t *param);
/**
* @brief attach USB for device connection
*
* Function to attach USB for device connection. Upon success, the USB PLL
* is enabled, and the USB device is now capable of transmitting and receiving
* on the USB bus and of generating interrupts.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_attach(void);
/**
* @brief detach the USB device
*
* Function to detach the USB device. Upon success, the USB hardware PLL
* is powered down and USB communication is disabled.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_detach(void);
/**
* @brief reset the USB device
*
* This function returns the USB device and firmware back to it's initial state.
* N.B. the USB PLL is handled by the usb_detach function
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_reset(void);
/**
* @brief set USB device address
*
* @param[in] addr device address
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_set_address(const uint8_t addr);
/**
* @brief set USB device controller status callback
*
* Function to set USB device controller status callback. The registered
* callback is used to report changes in the status of the device controller.
*
* @param[in] cb callback function
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_set_status_callback(const usb_dc_status_callback cb);
/**
* @brief check endpoint capabilities
*
* Function to check capabilities of an endpoint. usb_dc_ep_cfg_data structure
* provides the endpoint configuration parameters: endpoint address,
* endpoint maximum packet size and endpoint type.
* The driver should check endpoint capabilities and return 0 if the
* endpoint configuration is possible.
*
* @param[in] cfg Endpoint config
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data *const cfg);
/**
* @brief configure endpoint
*
* Function to configure an endpoint. usb_dc_ep_cfg_data structure provides
* the endpoint configuration parameters: endpoint address, endpoint maximum
* packet size and endpoint type.
*
* @param[in] cfg Endpoint config
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg);
/**
* @brief set stall condition for the selected endpoint
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_set_stall(const uint8_t ep);
/**
* @brief clear stall condition for the selected endpoint
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_clear_stall(const uint8_t ep);
/**
* @brief check if selected endpoint is stalled
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[out] stalled Endpoint stall status
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled);
/**
* @brief halt the selected endpoint
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_halt(const uint8_t ep);
/**
* @brief enable the selected endpoint
*
* Function to enable the selected endpoint. Upon success interrupts are
* enabled for the corresponding endpoint and the endpoint is ready for
* transmitting/receiving data.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_enable(const uint8_t ep);
/**
* @brief disable the selected endpoint
*
* Function to disable the selected endpoint. Upon success interrupts are
* disabled for the corresponding endpoint and the endpoint is no longer able
* for transmitting/receiving data.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_disable(const uint8_t ep);
/**
* @brief flush the selected endpoint
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_flush(const uint8_t ep);
/**
* @brief write data to the specified endpoint
*
* This function is called to write data to the specified endpoint. The supplied
* usb_ep_callback function will be called when data is transmitted out.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data pointer to data to write
* @param[in] data_len length of data requested to write. This may
* be zero for a zero length status packet.
* @param[out] ret_bytes bytes scheduled for transmission. This value
* may be NULL if the application expects all
* bytes to be written
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
const uint32_t data_len, uint32_t *const ret_bytes);
/**
* @brief Indicate if the write to an IN endpoint (using usb_dc_ep_write) would block
* to wait until the endpoint has enoug space
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 when writable, 0 when not, negative errno code on fail.
*/
int usb_dc_ep_write_would_block(const uint8_t ep);
/**
* @brief read data from the specified endpoint
*
* This function is called by the Endpoint handler function, after an OUT
* interrupt has been received for that EP. The application must only call this
* function through the supplied usb_ep_callback function. This function clears
* the ENDPOINT NAK, if all data in the endpoint FIFO has been read,
* so as to accept more data from host.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data pointer to data buffer to write to
* @param[in] max_data_len max length of data to read
* @param[out] read_bytes Number of bytes read. If data is NULL and
* max_data_len is 0 the number of bytes
* available for read should be returned.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_read(const uint8_t ep, uint8_t *const data,
const uint32_t max_data_len, uint32_t *const read_bytes);
/**
* @brief set callback function for the specified endpoint
*
* Function to set callback function for notification of data received and
* available to application or transmit done on the selected endpoint,
* NULL if callback not required by application code.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] cb callback function
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb);
/**
* @brief read data from the specified endpoint
*
* This is similar to usb_dc_ep_read, the difference being that, it doesn't
* clear the endpoint NAKs so that the consumer is not bogged down by further
* upcalls till he is done with the processing of the data. The caller should
* reactivate ep by invoking usb_dc_ep_read_continue() do so.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data pointer to data buffer to write to
* @param[in] max_data_len max length of data to read
* @param[out] read_bytes Number of bytes read. If data is NULL and
* max_data_len is 0 the number of bytes
* available for read should be returned.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
uint32_t *read_bytes);
/**
* @brief Continue reading data from the endpoint
*
* Clear the endpoint NAK and enable the endpoint to accept more data
* from the host. Usually called after usb_dc_ep_read_wait() when the consumer
* is fine to accept more data. Thus these calls together acts as flow control
* mechanism.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_dc_ep_read_continue(uint8_t ep);
/**
* @brief Get endpoint max packet size
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return enpoint max packet size (mps)
*/
int usb_dc_ep_mps(uint8_t ep);
//Hack - fake interrupts by pollinfg
void usb_dc_check_poll_for_interrupts(void);
//Prepare for USB persist. You should reboot after this.
int usb_dc_prepare_persist(void);
void usb_dw_isr_handler(void);
int usb_dc_ep_write_would_block(const uint8_t ep);
#ifdef __cplusplus
}
#endif

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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define USB_DESCRIPTOR_TYPE_ACM 0
#define USB_DESCRIPTOR_TYPE_DFU 1
void usb_set_current_descriptor(int descriptor_type);
bool usb_get_descriptor(uint16_t type_index, uint16_t lang_id,
int32_t *len, uint8_t **data);
#ifdef __cplusplus
}
#endif

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/*
* LPCUSB, an USB device driver for LPC microcontrollers
* Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)
* Copyright (c) 2016 Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* @brief USB device core layer APIs and structures
*
* This file contains the USB device core layer APIs and structures.
*/
#pragma once
#include <stddef.h>
#include <sys/cdefs.h>
#include "usb_dc.h"
#ifdef __cplusplus
extern "C" {
#endif
/*************************************************************************
* USB configuration
**************************************************************************/
#define MAX_PACKET_SIZE0 64 /**< maximum packet size for EP 0 */
//Note: for FS this should be 8, 16, 32, 64 bytes. HS can go up to 512.
/*************************************************************************
* USB application interface
**************************************************************************/
/** setup packet definitions */
struct usb_setup_packet {
uint8_t bmRequestType; /**< characteristics of the specific request */
uint8_t bRequest; /**< specific request */
uint16_t wValue; /**< request specific parameter */
uint16_t wIndex; /**< request specific parameter */
uint16_t wLength; /**< length of data transferred in data phase */
} __packed;
_Static_assert(sizeof(struct usb_setup_packet) == 8, "USB setup packet struct size error");
/**
* Callback function signature for the device
*/
typedef void (*usb_status_callback)(enum usb_dc_status_code status_code,
uint8_t *param);
/**
* Callback function signature for the USB Endpoint status
*/
typedef void (*usb_ep_callback)(uint8_t ep,
enum usb_dc_ep_cb_status_code cb_status);
/**
* Function which handles Class specific requests corresponding to an
* interface number specified in the device descriptor table
*/
typedef int (*usb_request_handler) (struct usb_setup_packet *detup,
int32_t *transfer_len, uint8_t **payload_data);
/**
* Function for interface runtime configuration
*/
typedef void (*usb_interface_config)(uint8_t bInterfaceNumber);
/*
* USB Endpoint Configuration
*/
struct usb_ep_cfg_data {
/**
* Callback function for notification of data received and
* available to application or transmit done, NULL if callback
* not required by application code
*/
usb_ep_callback ep_cb;
/**
* The number associated with the EP in the device configuration
* structure
* IN EP = 0x80 | \<endpoint number\>
* OUT EP = 0x00 | \<endpoint number\>
*/
uint8_t ep_addr;
};
/**
* USB Interface Configuration
*/
struct usb_interface_cfg_data {
/** Handler for USB Class specific Control (EP 0) communications */
usb_request_handler class_handler;
/** Handler for USB Vendor specific commands */
usb_request_handler vendor_handler;
/**
* The custom request handler gets a first chance at handling
* the request before it is handed over to the 'chapter 9' request
* handler
*/
usb_request_handler custom_handler;
/**
* This data area, allocated by the application, is used to store
* Class specific command data and must be large enough to store the
* largest payload associated with the largest supported Class'
* command set. This data area may be used for USB IN or OUT
* communications
*/
uint8_t *payload_data;
/**
* This data area, allocated by the application, is used to store
* Vendor specific payload
*/
uint8_t *vendor_data;
};
/*
* @brief USB device configuration
*
* The Application instantiates this with given parameters added
* using the "usb_set_config" function. Once this function is called
* changes to this structure will result in undefined behaviour. This structure
* may only be updated after calls to usb_deconfig
*/
struct usb_cfg_data {
/**
* USB device description, see
* http://www.beyondlogic.org/usbnutshell/usb5.shtml#DeviceDescriptors
*/
const uint8_t *usb_device_description;
/** Pointer to interface descriptor */
const void *interface_descriptor;
/** Function for interface runtime configuration */
usb_interface_config interface_config;
/** Callback to be notified on USB connection status change */
usb_status_callback cb_usb_status;
/** USB interface (Class) handler and storage space */
struct usb_interface_cfg_data interface;
/** Number of individual endpoints in the device configuration */
uint8_t num_endpoints;
/**
* Pointer to an array of endpoint structs of length equal to the
* number of EP associated with the device description,
* not including control endpoints
*/
struct usb_ep_cfg_data *endpoint;
};
/*
* @brief configure USB controller
*
* Function to configure USB controller.
* Configuration parameters must be valid or an error is returned
*
* @param[in] config Pointer to configuration structure
*
* @return 0 on success, negative errno code on fail
*/
int usb_set_config(struct usb_cfg_data *config);
/*
* @brief return the USB device to it's initial state
*
* @return 0 on success, negative errno code on fail
*/
int usb_deconfig(void);
/*
* @brief enable USB for host/device connection
*
* Function to enable USB for host/device connection.
* Upon success, the USB module is no longer clock gated in hardware,
* it is now capable of transmitting and receiving on the USB bus and
* of generating interrupts.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_enable(struct usb_cfg_data *config);
/*
* @brief disable the USB device.
*
* Function to disable the USB device.
* Upon success, the specified USB interface is clock gated in hardware,
* it is no longer capable of generating interrupts.
*
* @return 0 on success, negative errno code on fail
*/
int usb_disable(void);
/*
* @brief Check if a write to an in ep would block until there is enough space
* in the fifo
*
* @param[in] ep Endpoint address corresponding to the one listed in the
* device configuration table
*
* @return 0 if free to write, 1 if a write would block, negative errno code on fail
*/
int usb_write_would_block(uint8_t ep);
/*
* @brief write data to the specified endpoint
*
* Function to write data to the specified endpoint. The supplied
* usb_ep_callback will be called when transmission is done.
*
* @param[in] ep Endpoint address corresponding to the one listed in the
* device configuration table
* @param[in] data Pointer to data to write
* @param[in] data_len Length of data requested to write. This may be zero for
* a zero length status packet.
* @param[out] bytes_ret Bytes written to the EP FIFO. This value may be NULL if
* the application expects all bytes to be written
*
* @return 0 on success, negative errno code on fail
*/
int usb_write(uint8_t ep, const uint8_t *data, uint32_t data_len,
uint32_t *bytes_ret);
/*
* @brief read data from the specified endpoint
*
* This function is called by the Endpoint handler function, after an
* OUT interrupt has been received for that EP. The application must
* only call this function through the supplied usb_ep_callback function.
*
* @param[in] ep Endpoint address corresponding to the one listed in
* the device configuration table
* @param[in] data Pointer to data buffer to write to
* @param[in] max_data_len Max length of data to read
* @param[out] ret_bytes Number of bytes read. If data is NULL and
* max_data_len is 0 the number of bytes available
* for read is returned.
*
* @return 0 on success, negative errno code on fail
*/
int usb_read(uint8_t ep, uint8_t *data, uint32_t max_data_len,
uint32_t *ret_bytes);
/*
* @brief set STALL condition on the specified endpoint
*
* This function is called by USB device class handler code to set stall
* conditionin on endpoint.
*
* @param[in] ep Endpoint address corresponding to the one listed in
* the device configuration table
*
* @return 0 on success, negative errno code on fail
*/
int usb_ep_set_stall(uint8_t ep);
/*
* @brief clears STALL condition on the specified endpoint
*
* This function is called by USB device class handler code to clear stall
* conditionin on endpoint.
*
* @param[in] ep Endpoint address corresponding to the one listed in
* the device configuration table
*
* @return 0 on success, negative errno code on fail
*/
int usb_ep_clear_stall(uint8_t ep);
/**
* @brief read data from the specified endpoint
*
* This is similar to usb_ep_read, the difference being that, it doesn't
* clear the endpoint NAKs so that the consumer is not bogged down by further
* upcalls till he is done with the processing of the data. The caller should
* reactivate ep by invoking usb_ep_read_continue() do so.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data pointer to data buffer to write to
* @param[in] max_data_len max length of data to read
* @param[out] read_bytes Number of bytes read. If data is NULL and
* max_data_len is 0 the number of bytes
* available for read should be returned.
*
* @return 0 on success, negative errno code on fail.
*/
int usb_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
uint32_t *read_bytes);
/**
* @brief Continue reading data from the endpoint
*
* Clear the endpoint NAK and enable the endpoint to accept more data
* from the host. Usually called after usb_ep_read_wait() when the consumer
* is fine to accept more data. Thus these calls together acts as flow control
* mechanism.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
int usb_ep_read_continue(uint8_t ep);
/**
* Callback function signature for transfer completion.
*/
typedef void (*usb_transfer_callback)(uint8_t ep, int tsize, void *priv);
/* USB transfer flags */
#define USB_TRANS_READ BIT(0) /** Read transfer flag */
#define USB_TRANS_WRITE BIT(1) /** Write transfer flag */
#define USB_TRANS_NO_ZLP BIT(2) /** No zero-length packet flag */
/**
* @brief Transfer management endpoint callback
*
* If a USB class driver wants to use high-level transfer functions, driver
* needs to register this callback as usb endpoint callback.
*/
void usb_transfer_ep_callback(uint8_t ep, enum usb_dc_ep_cb_status_code);
/**
* @brief Start a transfer
*
* Start a usb transfer to/from the data buffer. This function is asynchronous
* and can be executed in IRQ context. The provided callback will be called
* on transfer completion (or error) in thread context.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data Pointer to data buffer to write-to/read-from
* @param[in] dlen Size of data buffer
* @param[in] flags Transfer flags (USB_TRANS_READ, USB_TRANS_WRITE...)
* @param[in] cb Function called on transfer completion/failure
* @param[in] priv Data passed back to the transfer completion callback
*
* @return 0 on success, negative errno code on fail.
*/
int usb_transfer(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags,
usb_transfer_callback cb, void *priv);
/**
* @brief Start a transfer and block-wait for completion
*
* Synchronous version of usb_transfer, wait for transfer completion before
* returning.
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
* @param[in] data Pointer to data buffer to write-to/read-from
* @param[in] dlen Size of data buffer
* @param[in] flags Transfer flags
*
* @return number of bytes transferred on success, negative errno code on fail.
*/
int usb_transfer_sync(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags);
/**
* @brief Cancel any ongoing transfer on the specified endpoint
*
* @param[in] ep Endpoint address corresponding to the one
* listed in the device configuration table
*
* @return 0 on success, negative errno code on fail.
*/
void usb_cancel_transfer(uint8_t ep);
void usb_dev_resume(int configuration);
int usb_dev_get_configuration(void);
#ifdef __cplusplus
}
#endif

147
components/esp_rom/include/esp32s3/rom/usb/usb_dfu.h Normal file
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@ -0,0 +1,147 @@
/***************************************************************************
*
* Copyright(c) 2015,2016 Intel Corporation.
* Copyright(c) 2017 PHYTEC Messtechnik GmbH
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/**
* @file
* @brief USB Device Firmware Upgrade (DFU) public header
*
* Header follows the Device Class Specification for
* Device Firmware Upgrade Version 1.1
*/
#pragma once
#include <stdint.h>
#include <stddef.h>
#include "usb_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DFU Class Subclass */
#define DFU_SUBCLASS 0x01
/** DFU Class runtime Protocol */
#define DFU_RT_PROTOCOL 0x01
/** DFU Class DFU mode Protocol */
#define DFU_MODE_PROTOCOL 0x02
/**
* @brief DFU Class Specific Requests
*/
#define DFU_DETACH 0x00
#define DFU_DNLOAD 0x01
#define DFU_UPLOAD 0x02
#define DFU_GETSTATUS 0x03
#define DFU_CLRSTATUS 0x04
#define DFU_GETSTATE 0x05
#define DFU_ABORT 0x06
/** DFU FUNCTIONAL descriptor type */
#define DFU_FUNC_DESC 0x21
/** DFU attributes DFU Functional Descriptor */
#define DFU_ATTR_WILL_DETACH 0x08
#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04
#define DFU_ATTR_CAN_UPLOAD 0x02
#define DFU_ATTR_CAN_DNLOAD 0x01
/** DFU Specification release */
#define DFU_VERSION 0x0110
/** Run-Time Functional Descriptor */
struct dfu_runtime_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bmAttributes;
uint16_t wDetachTimeOut;
uint16_t wTransferSize;
uint16_t bcdDFUVersion;
} __packed;
/** bStatus values for the DFU_GETSTATUS response */
enum dfu_status {
statusOK,
errTARGET,
errFILE,
errWRITE,
errERASE,
errCHECK_ERASED,
errPROG,
errVERIFY,
errADDRESS,
errNOTDONE,
errFIRMWARE,
errVENDOR,
errUSB,
errPOR,
errUNKNOWN,
errSTALLEDPKT
};
/** bState values for the DFU_GETSTATUS response */
enum dfu_state {
appIDLE,
appDETACH,
dfuIDLE,
dfuDNLOAD_SYNC,
dfuDNBUSY,
dfuDNLOAD_IDLE,
dfuMANIFEST_SYNC,
dfuMANIFEST,
dfuMANIFEST_WAIT_RST,
dfuUPLOAD_IDLE,
dfuERROR,
};
/*
These callbacks are made public so the ACM driver can call them to handle the switch to DFU.
*/
int dfu_class_handle_req(struct usb_setup_packet *pSetup,
int32_t *data_len, uint8_t **data);
void dfu_status_cb(enum usb_dc_status_code status, uint8_t *param);
int usb_dfu_init(void);
int dfu_custom_handle_req(struct usb_setup_packet *pSetup,
int32_t *data_len, uint8_t **data);
typedef void(*usb_dfu_detach_routine_t)(int delay);
void usb_dfu_set_detach_cb(usb_dfu_detach_routine_t cb);
#ifdef __cplusplus
}
#endif

40
components/esp_rom/include/esp32s3/rom/usb/usb_os_glue.h Normal file
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@ -0,0 +1,40 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void(*usb_osglue_intdisena_routine_t)(void);
typedef int(*usb_osglue_wait_routine_t)(int delay_us);
typedef struct {
/* Disable USB interrupt */
usb_osglue_intdisena_routine_t int_dis_proc;
/* Enable USB interrupt */
usb_osglue_intdisena_routine_t int_ena_proc;
/* Wait for a set amount of uS. Return the amount actually waited. If delay_us is 0, just yield.*/
usb_osglue_wait_routine_t wait_proc;
} usb_osglue_data_t;
extern usb_osglue_data_t s_usb_osglue;
#ifdef __cplusplus
}
#endif

50
components/esp_rom/include/esp32s3/rom/usb/usb_persist.h Normal file
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@ -0,0 +1,50 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
// USB persistence flags.
//This bit indicates persistence has been enabled, that is, the USB initialization routines should not
//reset the USB device as the device still is initialized and the host detected it with the same cdcacm/dfu
//descriptor as the ROM uses; we can just re-initialize the software side and have at 'er.
#define USBDC_PERSIST_ENA (1<<31)
//This bit indicates to the ROM that we rebooted because of a request to go into DFU mode; the ROM should
//honour this request.
#define USBDC_BOOT_DFU (1<<30)
//This being non-0 indicates a memory location where a 'testament' is stored, aka a piece of text that should be output
//after a reboot. Can contain core dump info or something.
#define USBDC_TESTAMENT_LOC_MASK 0x7FFFF //bits 19-0; this is added to a base address of 0x3FF80000.
//The testament is a FIFO. The ROM will output all data between textstart and textend; if textend is lower than textstart it will
//output everything from textstart to memend, then memstart to textend.
typedef struct {
char *memstart; //start of memory region
char *memend; //end of memory region
char *textstart; //start of text to output
char *textend;
} usbdc_testament_t;
#ifdef __cplusplus
}
#endif

2
components/esp_system/Kconfig
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@ -194,7 +194,7 @@ menu "ESP System Settings"
bool "USB CDC"
# The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
# && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
depends on IDF_TARGET_ESP32S2 && !USB_ENABLED
depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !USB_ENABLED
config ESP_CONSOLE_UART_CUSTOM
bool "Custom UART"
config ESP_CONSOLE_NONE

3
components/esp_system/port/soc/esp32s3/CMakeLists.txt
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@ -13,6 +13,9 @@ set(srcs "dport_panic_highint_hdl.S"
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})
target_sources(${COMPONENT_LIB} PRIVATE ${srcs})
if(CONFIG_ESP_CONSOLE_USB_CDC)
target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/usb_console.c")
endif()
#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
#linker will ignore panic_highint_hdl.S as it has no other files depending on any

426
components/esp_system/port/soc/esp32s3/usb_console.c Normal file
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@ -0,0 +1,426 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <sys/param.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp_system.h"
#include "esp_intr_alloc.h"
#include "esp_private/usb_console.h"
#include "soc/periph_defs.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/usb_struct.h"
#include "soc/usb_reg.h"
#include "soc/spinlock.h"
#include "hal/soc_hal.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp32s3/rom/usb/usb_dc.h"
#include "esp32s3/rom/usb/cdc_acm.h"
#include "esp32s3/rom/usb/usb_dfu.h"
#include "esp32s3/rom/usb/usb_device.h"
#include "esp32s3/rom/usb/usb_os_glue.h"
#include "esp32s3/rom/usb/usb_persist.h"
#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h"
#define CDC_WORK_BUF_SIZE (ESP_ROM_CDC_ACM_WORK_BUF_MIN + CONFIG_ESP_CONSOLE_USB_CDC_RX_BUF_SIZE)
typedef enum {
REBOOT_NONE,
REBOOT_NORMAL,
REBOOT_BOOTLOADER,
REBOOT_BOOTLOADER_DFU,
} reboot_type_t;
static reboot_type_t s_queue_reboot = REBOOT_NONE;
static int s_prev_rts_state;
static intr_handle_t s_usb_int_handle;
static cdc_acm_device *s_cdc_acm_device;
static char s_usb_tx_buf[ACM_BYTES_PER_TX];
static size_t s_usb_tx_buf_pos;
static uint8_t cdcmem[CDC_WORK_BUF_SIZE];
static esp_usb_console_cb_t s_rx_cb;
static esp_usb_console_cb_t s_tx_cb;
static void *s_cb_arg;
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
static spinlock_t s_write_lock = SPINLOCK_INITIALIZER;
void esp_usb_console_write_char(char c);
#define ISR_FLAG ESP_INTR_FLAG_IRAM
#else
#define ISR_FLAG 0
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Optional write lock routines; used only if esp_rom_printf output via CDC is enabled */
static inline void write_lock_acquire(void);
static inline void write_lock_release(void);
/* The two functions below need to be revisited in the multicore case TODO ESP32-S3 IDF-2048*/
_Static_assert(SOC_CPU_CORES_NUM == 1, "usb_osglue_*_int is not multicore capable");
/* Called by ROM to disable the interrupts
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_osglue_dis_int(void)
{
if (s_usb_int_handle) {
esp_intr_disable(s_usb_int_handle);
}
}
/* Called by ROM to enable the interrupts
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_osglue_ena_int(void)
{
if (s_usb_int_handle) {
esp_intr_enable(s_usb_int_handle);
}
}
/* Delay function called by ROM USB driver.
* Non-static to allow placement into IRAM by ldgen.
*/
int esp_usb_console_osglue_wait_proc(int delay_us)
{
if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING ||
!xPortCanYield()) {
esp_rom_delay_us(delay_us);
return delay_us;
}
if (delay_us == 0) {
/* We should effectively yield */
vPortYield();
return 1;
} else {
/* Just delay */
int ticks = MAX(delay_us / (portTICK_PERIOD_MS * 1000), 1);
vTaskDelay(ticks);
return ticks * portTICK_PERIOD_MS * 1000;
}
}
/* Called by ROM CDC ACM driver from interrupt context./
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_cdc_acm_cb(cdc_acm_device *dev, int status)
{
if (status == USB_DC_RESET || status == USB_DC_CONNECTED) {
s_prev_rts_state = 0;
} else if (status == ACM_STATUS_LINESTATE_CHANGED) {
uint32_t rts, dtr;
cdc_acm_line_ctrl_get(dev, LINE_CTRL_RTS, &rts);
cdc_acm_line_ctrl_get(dev, LINE_CTRL_DTR, &dtr);
if (!rts && s_prev_rts_state) {
if (dtr) {
s_queue_reboot = REBOOT_BOOTLOADER;
} else {
s_queue_reboot = REBOOT_NORMAL;
}
}
s_prev_rts_state = rts;
} else if (status == ACM_STATUS_RX && s_rx_cb) {
(*s_rx_cb)(s_cb_arg);
} else if (status == ACM_STATUS_TX && s_tx_cb) {
(*s_tx_cb)(s_cb_arg);
}
}
/* Non-static to allow placement into IRAM by ldgen. */
void esp_usb_console_dfu_detach_cb(int timeout)
{
s_queue_reboot = REBOOT_BOOTLOADER_DFU;
}
/* USB interrupt handler, forward the call to the ROM driver.
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_interrupt(void *arg)
{
usb_dc_check_poll_for_interrupts();
/* Restart can be requested from esp_usb_console_cdc_acm_cb or esp_usb_console_dfu_detach_cb */
if (s_queue_reboot != REBOOT_NONE) {
esp_restart();
}
}
/* Call the USB interrupt handler while any interrupts are pending,
* but not more than a few times.
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_poll_interrupts(void)
{
const int max_poll_count = 10;
for (int i = 0; (USB0.gintsts & USB0.gintmsk) != 0 && i < max_poll_count; i++) {
usb_dc_check_poll_for_interrupts();
}
}
/* This function gets registered as a restart handler.
* Prepares USB peripheral for restart and sets up persistence.
* Non-static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_before_restart(void)
{
esp_usb_console_poll_interrupts();
usb_dc_prepare_persist();
if (s_queue_reboot == REBOOT_BOOTLOADER) {
chip_usb_set_persist_flags(USBDC_PERSIST_ENA);
REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT);
} else if (s_queue_reboot == REBOOT_BOOTLOADER_DFU) {
chip_usb_set_persist_flags(USBDC_BOOT_DFU);
REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT);
} else {
chip_usb_set_persist_flags(USBDC_PERSIST_ENA);
esp_usb_console_poll_interrupts();
}
}
/* Reset some static state in ROM, which survives when going from the
* 2nd stage bootloader into the app. This cleans some variables which
* indicates that the driver is already initialized, allowing us to
* initialize it again, in the app.
*/
static void esp_usb_console_rom_cleanup(void)
{
/* TODO ESP32-S3 IDF-2987 */
// extern char rom_usb_dev, rom_usb_dev_end;
// extern char rom_usb_dw_ctrl, rom_usb_dw_ctrl_end;
// uart_acm_dev = NULL;
// memset((void *) &rom_usb_dev, 0, &rom_usb_dev_end - &rom_usb_dev);
// memset((void *) &rom_usb_dw_ctrl, 0, &rom_usb_dw_ctrl_end - &rom_usb_dw_ctrl);
}
esp_err_t esp_usb_console_init(void)
{
esp_err_t err;
err = esp_register_shutdown_handler(esp_usb_console_before_restart);
if (err != ESP_OK) {
return err;
}
esp_usb_console_rom_cleanup();
/* Install OS hooks */
s_usb_osglue.int_dis_proc = esp_usb_console_osglue_dis_int;
s_usb_osglue.int_ena_proc = esp_usb_console_osglue_ena_int;
s_usb_osglue.wait_proc = esp_usb_console_osglue_wait_proc;
/* Install interrupt.
* In case of ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
* Note that this the interrupt handler has to be placed into IRAM because
* the interrupt handler can also be called in polling mode, when
* interrupts are disabled, and a write to USB is performed with cache disabled.
* Since the handler function is in IRAM, we can register the interrupt as IRAM capable.
* It is not because we actually need the interrupt to work with cache disabled!
*/
err = esp_intr_alloc(ETS_USB_INTR_SOURCE, ISR_FLAG | ESP_INTR_FLAG_INTRDISABLED,
esp_usb_console_interrupt, NULL, &s_usb_int_handle);
if (err != ESP_OK) {
esp_unregister_shutdown_handler(esp_usb_console_before_restart);
return err;
}
/* Initialize USB / CDC */
s_cdc_acm_device = cdc_acm_init(cdcmem, CDC_WORK_BUF_SIZE);
usb_dc_check_poll_for_interrupts();
/* Set callback for handling DTR/RTS lines and TX/RX events */
cdc_acm_irq_callback_set(s_cdc_acm_device, esp_usb_console_cdc_acm_cb);
cdc_acm_irq_state_enable(s_cdc_acm_device);
/* Set callback for handling DFU detach */
usb_dfu_set_detach_cb(esp_usb_console_dfu_detach_cb);
/* Enable interrupts on USB peripheral side */
USB0.gahbcfg |= USB_GLBLLNTRMSK_M;
/* Enable the interrupt handler */
esp_intr_enable(s_usb_int_handle);
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Install esp_rom_printf handler */
ets_install_putc1(&esp_usb_console_write_char);
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
return ESP_OK;
}
/* Non-static to allow placement into IRAM by ldgen.
* Must be called with the write lock held.
*/
ssize_t esp_usb_console_flush_internal(size_t last_write_size)
{
if (s_usb_tx_buf_pos == 0) {
return 0;
}
assert(s_usb_tx_buf_pos >= last_write_size);
ssize_t ret;
size_t tx_buf_pos_before = s_usb_tx_buf_pos - last_write_size;
int sent = cdc_acm_fifo_fill(s_cdc_acm_device, (const uint8_t*) s_usb_tx_buf, s_usb_tx_buf_pos);
if (sent == last_write_size) {
/* everything was sent */
ret = last_write_size;
s_usb_tx_buf_pos = 0;
} else if (sent == 0) {
/* nothing was sent, roll back to the original state */
ret = 0;
s_usb_tx_buf_pos = tx_buf_pos_before;
} else {
/* Some data was sent, but not all of the buffer.
* We can still tell the caller that all the new data
* was "sent" since it is in the buffer now.
*/
ret = last_write_size;
memmove(s_usb_tx_buf, s_usb_tx_buf + sent, s_usb_tx_buf_pos - sent);
s_usb_tx_buf_pos = s_usb_tx_buf_pos - sent;
}
return ret;
}
ssize_t esp_usb_console_flush(void)
{
if (s_cdc_acm_device == NULL) {
return -1;
}
write_lock_acquire();
int ret = esp_usb_console_flush_internal(0);
write_lock_release();
return ret;
}
ssize_t esp_usb_console_write_buf(const char* buf, size_t size)
{
if (s_cdc_acm_device == NULL) {
return -1;
}
if (size == 0) {
return 0;
}
write_lock_acquire();
ssize_t tx_buf_available = ACM_BYTES_PER_TX - s_usb_tx_buf_pos;
ssize_t will_write = MIN(size, tx_buf_available);
memcpy(s_usb_tx_buf + s_usb_tx_buf_pos, buf, will_write);
s_usb_tx_buf_pos += will_write;
ssize_t ret;
if (s_usb_tx_buf_pos == ACM_BYTES_PER_TX || buf[size - 1] == '\n') {
/* Buffer is full, or a newline is found.
* For binary streams, we probably shouldn't do line buffering,
* but text streams are likely going to be the most common case.
*/
ret = esp_usb_console_flush_internal(will_write);
} else {
/* nothing sent out yet, but all the new data is in the buffer now */
ret = will_write;
}
write_lock_release();
return ret;
}
ssize_t esp_usb_console_read_buf(char *buf, size_t buf_size)
{
if (s_cdc_acm_device == NULL) {
return -1;
}
if (!esp_usb_console_read_available()) {
return 0;
}
int bytes_read = cdc_acm_fifo_read(s_cdc_acm_device, (uint8_t*) buf, buf_size);
return bytes_read;
}
esp_err_t esp_usb_console_set_cb(esp_usb_console_cb_t rx_cb, esp_usb_console_cb_t tx_cb, void *arg)
{
if (s_cdc_acm_device == NULL) {
return ESP_ERR_INVALID_STATE;
}
s_rx_cb = rx_cb;
if (s_rx_cb) {
cdc_acm_irq_rx_enable(s_cdc_acm_device);
} else {
cdc_acm_irq_rx_disable(s_cdc_acm_device);
}
s_tx_cb = tx_cb;
if (s_tx_cb) {
cdc_acm_irq_tx_enable(s_cdc_acm_device);
} else {
cdc_acm_irq_tx_disable(s_cdc_acm_device);
}
s_cb_arg = arg;
return ESP_OK;
}
bool esp_usb_console_read_available(void)
{
if (s_cdc_acm_device == NULL) {
return false;
}
return cdc_acm_rx_fifo_cnt(s_cdc_acm_device) > 0;
}
bool esp_usb_console_write_available(void)
{
if (s_cdc_acm_device == NULL) {
return false;
}
return cdc_acm_irq_tx_ready(s_cdc_acm_device) != 0;
}
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Used as an output function by esp_rom_printf.
* The LF->CRLF replacement logic replicates the one in esp_rom_uart_putc.
* Not static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_write_char(char c)
{
char cr = '\r';
char lf = '\n';
if (c == lf) {
esp_usb_console_write_buf(&cr, 1);
esp_usb_console_write_buf(&lf, 1);
} else if (c == '\r') {
} else {
esp_usb_console_write_buf(&c, 1);
}
}
static inline void write_lock_acquire(void)
{
spinlock_acquire(&s_write_lock, SPINLOCK_WAIT_FOREVER);
}
static inline void write_lock_release(void)
{
spinlock_release(&s_write_lock);
}
#else // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
static inline void write_lock_acquire(void)
{
}
static inline void write_lock_release(void)
{
}
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF

9
components/esp_wifi/CMakeLists.txt
View File

@ -8,6 +8,15 @@ else()
set(ldfragments "linker.lf")
endif()
# remove these when wifi support is ready on esp32-s3
if(${idf_target} STREQUAL "esp32s3")
idf_component_register(INCLUDE_DIRS "include"
REQUIRES esp_event
PRIV_REQUIRES wpa_supplicant nvs_flash esp_netif)
return()
endif()
if(IDF_TARGET_ESP32)
# dport workaround headers are in esp32 component
set(extra_priv_requires esp32)

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit 0ba556f042bd428e62e96891601b1940bc1c0972
Subproject commit 16703d0be03e1477741a856e2dcdc4896fca9267

4
components/esptool_py/project_include.cmake
View File

@ -6,8 +6,8 @@ idf_build_get_property(python PYTHON)
set(chip_model ${target})
if(target STREQUAL "esp32s3")
if(CONFIG_IDF_TARGET_ESP32S3_BETA_VERSION_2)
set(chip_model "esp32s3beta2")
if(CONFIG_IDF_TARGET_ESP32S3_BETA_VERSION_3)
set(chip_model "esp32s3beta3")
endif()
endif()

3
components/hal/esp32/include/hal/i2c_ll.h
View File

@ -88,6 +88,9 @@ typedef struct {
#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_FULL_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
// I2C source clock frequency
#define I2C_LL_CLK_SRC_FREQ(src_clk) (80*1000*1000)
// I2C max timeout value
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V
/**
* @brief Calculate I2C bus frequency
*

2
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@ -95,6 +95,8 @@ typedef struct {
#define I2C_LL_CLK_SRC_FREQ(src_clk) (((src_clk) == I2C_SCLK_RTC) ? 20*1000*1000 : 40*1000*1000); // Another clock is XTAL clock
// delay time after rtc_clk swiching on
#define DELAY_RTC_CLK_SWITCH (5)
// I2C max timeout value
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V
/**
* @brief Calculate I2C bus frequency

2
components/hal/esp32s2/include/hal/i2c_ll.h
View File

@ -89,6 +89,8 @@ typedef struct {
#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
// I2C source clock
#define I2C_LL_CLK_SRC_FREQ(src_clk) (((src_clk) == I2C_SCLK_REF_TICK) ? 1000*1000 : 80*1000*1000); // Another clock is APB clock
// I2C max timeout value
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V
/**
* @brief Calculate I2C bus frequency
*

124
components/hal/esp32s3/include/hal/gdma_ll.h
View File

@ -50,11 +50,11 @@ extern "C" {
*/
static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].mem_trans_en = enable;
dev->in[channel].conf0.mem_trans_en = enable;
if (enable) {
// to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value
dev->peri_sel[channel].peri_in_sel = 0;
dev->peri_sel[channel].peri_out_sel = 0;
dev->in[channel].peri_sel.sel = 0;
dev->out[channel].peri_sel.sel = 0;
}
}
@ -63,7 +63,7 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo
*/
static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->int_st[channel].val;
return dev->in[channel].int_st.val;
}
/**
@ -72,9 +72,9 @@ static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t ch
static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->int_ena[channel].val |= mask;
dev->in[channel].int_ena.val |= mask;
} else {
dev->int_ena[channel].val &= ~mask;
dev->in[channel].int_ena.val &= ~mask;
}
}
@ -83,7 +83,7 @@ static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->int_clr[channel].val = mask;
dev->in[channel].int_clr.val = mask;
}
/**
@ -100,7 +100,7 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
*/
static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf1[channel].check_owner = enable;
dev->in[channel].conf1.in_check_owner = enable;
}
/**
@ -108,7 +108,7 @@ static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].in_data_burst_en = enable;
dev->in[channel].conf0.in_data_burst_en = enable;
}
/**
@ -116,7 +116,7 @@ static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].indscr_burst_en = enable;
dev->in[channel].conf0.indscr_burst_en = enable;
}
/**
@ -124,8 +124,8 @@ static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->conf0[channel].in_rst = 1;
dev->conf0[channel].in_rst = 0;
dev->in[channel].conf0.in_rst = 1;
dev->in[channel].conf0.in_rst = 0;
}
/**
@ -134,7 +134,7 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->conf1[channel].in_ext_mem_bk_size = size_index;
dev->in[channel].conf1.in_ext_mem_bk_size = size_index;
}
/**
@ -142,7 +142,7 @@ static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, uint32_t water_mark)
{
dev->conf1[channel].infifo_full_thrs = water_mark;
dev->in[channel].conf1.dma_infifo_full_thrs = water_mark;
}
/**
@ -151,7 +151,7 @@ static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel,
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->infifo_status[channel].val & (1 << 2 * (fifo_level - 1));
return dev->in[channel].infifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@ -160,7 +160,7 @@ static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->infifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
return dev->in[channel].infifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@ -171,11 +171,11 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->infifo_status[channel].infifo_cnt_l1;
return dev->in[channel].infifo_status.infifo_cnt_l1;
case 2:
return dev->infifo_status[channel].infifo_cnt_l2;
return dev->in[channel].infifo_status.infifo_cnt_l2;
case 3:
return dev->infifo_status[channel].infifo_cnt_l3;
return dev->in[channel].infifo_status.infifo_cnt_l3;
}
}
@ -184,8 +184,8 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
{
dev->in_pop[channel].infifo_pop = 1;
return dev->in_pop[channel].infifo_rdata;
dev->in[channel].pop.infifo_pop = 1;
return dev->in[channel].pop.infifo_rdata;
}
/**
@ -193,7 +193,7 @@ static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->in_link[channel].addr = addr;
dev->in[channel].link.addr = addr;
}
/**
@ -201,7 +201,7 @@ static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].start = 1;
dev->in[channel].link.start = 1;
}
/**
@ -209,7 +209,7 @@ static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].stop = 1;
dev->in[channel].link.stop = 1;
}
/**
@ -217,7 +217,7 @@ static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].restart = 1;
dev->in[channel].link.restart = 1;
}
/**
@ -225,7 +225,7 @@ static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in_link[channel].auto_ret = enable;
dev->in[channel].link.auto_ret = enable;
}
/**
@ -233,7 +233,7 @@ static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t chann
*/
static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_link[channel].park;
return dev->in[channel].link.park;
}
/**
@ -241,7 +241,7 @@ static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_suc_eof_des_addr[channel];
return dev->in[channel].suc_eof_des_addr;
}
/**
@ -249,7 +249,7 @@ static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uin
*/
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_err_eof_des_addr[channel];
return dev->in[channel].err_eof_des_addr;
}
/**
@ -257,7 +257,7 @@ static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint3
*/
static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_dscr[channel];
return dev->in[channel].dscr;
}
/**
@ -265,7 +265,7 @@ static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->wight[channel].rx_weight = weight;
dev->in[channel].wight.rx_weight = weight;
}
/**
@ -273,15 +273,15 @@ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->pri[channel].rx_pri = prio;
dev->in[channel].pri.rx_pri = prio;
}
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
{
dev->peri_sel[channel].peri_in_sel = periph_id;
dev->in[channel].peri_sel.sel = periph_id;
}
/**
@ -292,7 +292,7 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->in[channel].sram_size.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}
@ -303,7 +303,7 @@ static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t c
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf1[channel].check_owner = enable;
dev->out[channel].conf1.out_check_owner = enable;
}
/**
@ -311,7 +311,7 @@ static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].out_data_burst_en = enable;
dev->out[channel].conf0.out_data_burst_en = enable;
}
/**
@ -319,7 +319,7 @@ static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].outdscr_burst_en = enable;
dev->out[channel].conf0.outdscr_burst_en = enable;
}
/**
@ -327,7 +327,7 @@ static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
{
dev->conf0[channel].out_eof_mode = mode;
dev->out[channel].conf0.out_eof_mode = mode;
}
/**
@ -335,7 +335,7 @@ static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].out_auto_wrback = enable;
dev->out[channel].conf0.out_auto_wrback = enable;
}
/**
@ -343,8 +343,8 @@ static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t c
*/
static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->conf0[channel].out_rst = 1;
dev->conf0[channel].out_rst = 0;
dev->out[channel].conf0.out_rst = 1;
dev->out[channel].conf0.out_rst = 0;
}
/**
@ -353,7 +353,7 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->conf1[channel].out_ext_mem_bk_size = size_index;
dev->out[channel].conf1.out_ext_mem_bk_size = size_index;
}
/**
@ -362,7 +362,7 @@ static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->outfifo_status[channel].val & (1 << 2 * (fifo_level - 1));
return dev->out[channel].outfifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@ -371,7 +371,7 @@ static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->outfifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
return dev->out[channel].outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@ -382,11 +382,11 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->outfifo_status[channel].outfifo_cnt_l1;
return dev->out[channel].outfifo_status.outfifo_cnt_l1;
case 2:
return dev->outfifo_status[channel].outfifo_cnt_l2;
return dev->out[channel].outfifo_status.outfifo_cnt_l2;
case 3:
return dev->outfifo_status[channel].outfifo_cnt_l3;
return dev->out[channel].outfifo_status.outfifo_cnt_l3;
}
}
@ -395,8 +395,8 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
{
dev->out_push[channel].outfifo_wdata = data;
dev->out_push[channel].outfifo_push = 1;
dev->out[channel].push.outfifo_wdata = data;
dev->out[channel].push.outfifo_push = 1;
}
/**
@ -404,7 +404,7 @@ static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint3
*/
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->out_link[channel].addr = addr;
dev->out[channel].link.addr = addr;
}
/**
@ -412,7 +412,7 @@ static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].start = 1;
dev->out[channel].link.start = 1;
}
/**
@ -420,7 +420,7 @@ static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].stop = 1;
dev->out[channel].link.stop = 1;
}
/**
@ -428,7 +428,7 @@ static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].restart = 1;
dev->out[channel].link.restart = 1;
}
/**
@ -436,7 +436,7 @@ static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_link[channel].park;
return dev->out[channel].link.park;
}
/**
@ -444,7 +444,7 @@ static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_eof_des_addr[channel];
return dev->out[channel].eof_des_addr;
}
/**
@ -452,7 +452,7 @@ static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t ch
*/
static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_dscr[channel];
return dev->out[channel].dscr;
}
/**
@ -460,7 +460,7 @@ static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->wight[channel].tx_weight = weight;
dev->out[channel].wight.tx_weight = weight;
}
/**
@ -468,15 +468,15 @@ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->pri[channel].tx_pri = prio;
dev->out[channel].pri.tx_pri = prio;
}
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
{
dev->peri_sel[channel].peri_out_sel = periph_id;
dev->out[channel].peri_sel.sel = periph_id;
}
/**
@ -487,7 +487,7 @@ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->out[channel].sram_size.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}

14
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@ -90,6 +90,8 @@ typedef struct {
#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
// I2C source clock
#define I2C_LL_CLK_SRC_FREQ(src_clk) (((src_clk) == I2C_SCLK_RTC) ? 8*1000*1000 : 40*1000*1000); // Another clock is XTAL clock
// I2C max timeout value
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_VALUE_V
/**
* @brief Calculate I2C bus frequency
@ -159,7 +161,7 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
//hold
hw->scl_start_hold.time = bus_cfg->hold - 1;
hw->scl_stop_hold.time = bus_cfg->hold;
hw->timeout.time_out_value = bus_cfg->tout;
hw->timeout.tout = bus_cfg->tout;
hw->timeout.time_out_en = 1;
}
@ -280,7 +282,7 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
*/
static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
{
hw->timeout.time_out_value = tout;
hw->timeout.tout = tout;
}
/**
@ -449,7 +451,7 @@ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
*/
static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw)
{
return hw->status_reg.bus_busy;
return hw->sr.bus_busy;
}
/**
@ -473,7 +475,7 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
{
return hw->status_reg.rx_fifo_cnt;
return hw->sr.rx_fifo_cnt;
}
/**
@ -485,7 +487,7 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
{
return SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt;
}
/**
@ -497,7 +499,7 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw)
{
return hw->timeout.time_out_value;
return hw->timeout.tout;
}
/**

8
components/hal/esp32s3/include/hal/rmt_ll.h
View File

@ -88,16 +88,16 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].mem_rd_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 0;
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].apb_mem_rst = 0;
dev->tx_conf[channel].mem_rst = 1;
dev->tx_conf[channel].mem_rst = 0;
}
static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->rx_conf[channel].conf1.mem_wr_rst = 1;
dev->rx_conf[channel].conf1.mem_wr_rst = 0;
dev->rx_conf[channel].conf1.apb_mem_rst = 1;
dev->rx_conf[channel].conf1.apb_mem_rst = 0;
dev->rx_conf[channel].conf1.mem_rst = 1;
dev->rx_conf[channel].conf1.mem_rst = 0;
}
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)

6
components/hal/esp32s3/include/hal/touch_sensor_ll.h
View File

@ -745,9 +745,9 @@ static inline void touch_ll_filter_get_debounce(uint32_t *dbc_cnt)
static inline void touch_ll_filter_set_noise_thres(uint32_t noise_thr)
{
RTCCNTL.touch_filter_ctrl.touch_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.config2 = noise_thr;
RTCCNTL.touch_filter_ctrl.config1 = 0xF;
RTCCNTL.touch_filter_ctrl.config3 = 2;
RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit = 0xF;
RTCCNTL.touch_filter_ctrl.touch_hysteresis = 2;
}
/**

4
components/newlib/locks.c
View File

@ -387,13 +387,13 @@ void esp_newlib_locks_init(void)
__env_lock_object = (_lock_t) &s_common_mutex;
extern _lock_t __tz_lock_object;
__tz_lock_object = (_lock_t) &s_common_recursive_mutex;
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
#elif defined(CONFIG_IDF_TARGET_ESP32S2)
/* Newlib 3.0.0 is used in ROM, the following lock symbols are defined: */
extern _lock_t __sinit_recursive_mutex;
__sinit_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
extern _lock_t __sfp_recursive_mutex;
__sfp_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
#elif defined(CONFIG_IDF_TARGET_ESP32C3)
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
/* Newlib 3.3.0 is used in ROM, built with _RETARGETABLE_LOCKING.
* No access to lock variables for the purpose of ECO forward compatibility,
* however we have an API to initialize lock variables used in the ROM.

3
components/newlib/newlib_init.c
View File

@ -22,6 +22,7 @@
#include <sys/signal.h>
#include <sys/unistd.h>
#include <sys/reent.h>
#include <assert.h>
#include "esp_newlib.h"
#include "esp_attr.h"
#include "sdkconfig.h"
@ -111,7 +112,7 @@ static struct syscall_stub_table s_stub_table = {
._printf_float = NULL,
._scanf_float = NULL,
#endif
#ifdef CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
/* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM
assertion failures (as function names & source file names will be similar)
*/

941
components/soc/esp32s3/include/soc/apb_ctrl_reg.h
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File diff suppressed because it is too large Load Diff

146
components/soc/esp32s3/include/soc/apb_ctrl_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
@ -56,10 +54,10 @@ typedef volatile struct {
};
uint32_t val;
} clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
union {
struct {
uint32_t peri_io_swap: 8;
@ -76,7 +74,7 @@ typedef volatile struct {
} ext_mem_pms_lock;
union {
struct {
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
uint32_t reserved1: 31;
};
uint32_t val;
@ -109,34 +107,34 @@ typedef volatile struct {
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
union {
struct {
uint32_t flash_ace0_size: 16;
uint32_t flash_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size: 16;
uint32_t flash_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size: 16;
uint32_t flash_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size: 16;
uint32_t flash_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
@ -169,34 +167,34 @@ typedef volatile struct {
};
uint32_t val;
} sram_ace3_attr;
uint32_t sram_ace0_addr; /**/
uint32_t sram_ace1_addr; /**/
uint32_t sram_ace2_addr; /**/
uint32_t sram_ace3_addr; /**/
uint32_t sram_ace0_addr; /**/
uint32_t sram_ace1_addr; /**/
uint32_t sram_ace2_addr; /**/
uint32_t sram_ace3_addr; /**/
union {
struct {
uint32_t sram_ace0_size: 16;
uint32_t sram_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace0_size;
union {
struct {
uint32_t sram_ace1_size: 16;
uint32_t sram_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace1_size;
union {
struct {
uint32_t sram_ace2_size: 16;
uint32_t sram_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace2_size;
union {
struct {
uint32_t sram_ace3_size: 16;
uint32_t sram_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
@ -210,7 +208,7 @@ typedef volatile struct {
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
uint32_t spi_mem_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
@ -240,31 +238,85 @@ typedef volatile struct {
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t reserved6: 26;
uint32_t freq_mem_force_pu: 1;
uint32_t freq_mem_force_pd: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t ecc_err: 8; /*This bits show the error times of MSPI ECC read.*/
uint32_t ecc_err_clr: 1; /*Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/
uint32_t ecc_err_int_num: 8; /*Set the error times of MSPI ECC read to generate MSPI interrupt.*/
uint32_t ecc_err_int_en: 1; /*Set this bit to enable MSPI interrupt when the error times of MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t reserved0: 18; /*reserved*/
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} spi_mem_ecc_ctrl;
uint32_t spi_mem_ecc_err_aadr; /*This bits show the latest MSPI ECC error address.*/
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_a4;
union {
struct {
uint32_t rom_clkgate_force_on: 3;
uint32_t sram_clkgate_force_on:11;
uint32_t reserved14: 18;
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down: 3;
uint32_t sram_power_down:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up: 3;
uint32_t sram_power_up:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_up;
union {
struct {
uint32_t retention_cpu_link_addr:27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t retention_tag_link_addr:27;
uint32_t reserved27: 5;
};
uint32_t val;
} retention_ctrl1;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_icache_size: 8;
uint32_t reserved12: 1;
uint32_t ret_icache_vld_size: 8;
uint32_t reserved21: 1;
uint32_t ret_icache_start_point: 8;
uint32_t reserved30: 1;
uint32_t ret_icache_enable: 1;
};
uint32_t val;
} retention_ctrl2;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_dcache_size: 9;
uint32_t ret_dcache_vld_size: 9;
uint32_t ret_dcache_start_point: 9;
uint32_t ret_dcache_enable: 1;
};
uint32_t val;
} retention_ctrl3;
uint32_t retention_ctrl4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
@ -470,11 +522,11 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /*Version control*/
uint32_t date; /*Version control*/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_CTRL_STRUCT_H_ */

1060
components/soc/esp32s3/include/soc/apb_saradc_reg.h
View File

File diff suppressed because it is too large Load Diff

301
components/soc/esp32s3/include/soc/apb_saradc_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,170 +11,130 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
uint32_t reserved29: 1;
uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
uint32_t start_force : 1;
uint32_t start : 1;
uint32_t reserved2 : 1;
uint32_t work_mode : 2; /* 0: single mode, 1: double mode, 2: alternate mode*/
uint32_t sar_sel : 1; /* 0: SAR1, 1: SAR2, only work for single SAR mode*/
uint32_t sar_clk_gated : 1;
uint32_t sar_clk_div : 8; /*SAR clock divider*/
uint32_t sar1_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel : 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s : 1; /*1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/
uint32_t reserved29 : 1;
uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target: 12; /*to set saradc timer target*/
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
uint32_t reserved25: 7;
uint32_t meas_num_limit : 1;
uint32_t max_meas_num : 8; /*max conversion number*/
uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/
uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/
uint32_t timer_sel : 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target : 12; /*to set saradc timer target*/
uint32_t timer_en : 1; /*to enable saradc timer trigger*/
uint32_t reserved25 : 7;
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t reserved0: 26;
uint32_t filter_factor1: 3;
uint32_t filter_factor0: 3;
uint32_t reserved0 : 26;
uint32_t filter_factor1 : 3;
uint32_t filter_factor0 : 3;
};
uint32_t val;
} filter_ctrl1;
union {
struct {
uint32_t xpd_wait: 8;
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t reserved24: 8;
uint32_t xpd_wait : 8;
uint32_t rstb_wait : 8;
uint32_t standby_wait : 8;
uint32_t reserved24 : 8;
};
uint32_t val;
} fsm_wait;
uint32_t sar1_status; /**/
uint32_t sar2_status; /**/
uint32_t sar1_status;
uint32_t sar2_status;
union {
struct {
uint32_t sar1_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
uint32_t sar1_patt_tab : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t reserved24 : 8;
};
uint32_t val;
} sar1_patt_tab1;
} sar1_patt_tab[4];
union {
struct {
uint32_t sar1_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
uint32_t sar2_patt_tab : 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t reserved24 : 8;
};
uint32_t val;
} sar1_patt_tab2;
} sar2_patt_tab[4];
union {
struct {
uint32_t sar1_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar1_patt_tab3;
union {
struct {
uint32_t sar1_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar1_patt_tab4;
union {
struct {
uint32_t sar2_patt_tab1: 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab1;
union {
struct {
uint32_t sar2_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab2;
union {
struct {
uint32_t sar2_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab3;
union {
struct {
uint32_t sar2_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab4;
union {
struct {
uint32_t reserved0: 2;
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13: 19;
uint32_t reserved0 : 2;
uint32_t adc_arb_apb_force : 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force : 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force : 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force : 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority : 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority : 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority : 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority : 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13 : 19;
};
uint32_t val;
} apb_adc_arb_ctrl;
union {
struct {
uint32_t reserved0: 14;
uint32_t filter_channel1: 5;
uint32_t filter_channel0: 5; /*apb_adc1_filter_factor*/
uint32_t reserved24: 7;
uint32_t filter_reset: 1; /*enable apb_adc1_filter*/
uint32_t reserved0 : 14;
uint32_t filter_channel1 : 5;
uint32_t filter_channel0 : 5; /*apb_adc1_filter_factor*/
uint32_t reserved24 : 7;
uint32_t filter_reset : 1; /*enable apb_adc1_filter*/
};
uint32_t val;
} filter_ctrl0;
union {
struct {
uint32_t adc1_data: 17;
uint32_t reserved17: 15;
uint32_t adc1_data : 17;
uint32_t reserved17 : 15;
};
uint32_t val;
} apb_saradc1_data_status;
union {
struct {
uint32_t thres0_channel: 5;
uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/
uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/
uint32_t thres0_channel : 5;
uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/
uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31 : 1;
};
uint32_t val;
} thres0_ctrl;
union {
struct {
uint32_t thres1_channel: 5;
uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/
uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31: 1;
uint32_t thres1_channel : 5;
uint32_t thres1_high : 13; /*saradc1's thres0 monitor thres*/
uint32_t thres1_low : 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31 : 1;
};
uint32_t val;
} thres1_ctrl;
@ -183,111 +143,92 @@ typedef volatile struct {
uint32_t reserved_54;
union {
struct {
uint32_t reserved0: 27;
uint32_t thres_all_en: 1;
uint32_t thres3_en: 1;
uint32_t thres2_en: 1;
uint32_t thres1_en: 1;
uint32_t thres0_en: 1;
uint32_t reserved0 : 27;
uint32_t thres_all_en : 1;
uint32_t thres3_en : 1;
uint32_t thres2_en : 1;
uint32_t thres1_en : 1;
uint32_t thres0_en : 1;
};
uint32_t val;
} thres_ctrl;
union {
struct {
uint32_t reserved0: 26;
uint32_t thres1_low: 1;
uint32_t thres0_low: 1;
uint32_t thres1_high: 1;
uint32_t thres0_high: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
uint32_t reserved0 : 26;
uint32_t thres1_low : 1;
uint32_t thres0_low : 1;
uint32_t thres1_high : 1;
uint32_t thres0_high : 1;
uint32_t adc2_done : 1;
uint32_t adc1_done : 1;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t reserved0: 26;
uint32_t thres1_low: 1;
uint32_t thres0_low: 1;
uint32_t thres1_high: 1;
uint32_t thres0_high: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
uint32_t reserved0 : 26;
uint32_t thres1_low : 1;
uint32_t thres0_low : 1;
uint32_t thres1_high : 1;
uint32_t thres0_high : 1;
uint32_t adc2_done : 1;
uint32_t adc1_done : 1;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t reserved0: 26;
uint32_t thres1_low: 1;
uint32_t thres0_low: 1;
uint32_t thres1_high: 1;
uint32_t thres0_high: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
uint32_t reserved0 : 26;
uint32_t thres1_low : 1;
uint32_t thres0_low : 1;
uint32_t thres1_high : 1;
uint32_t thres0_high : 1;
uint32_t adc2_done : 1;
uint32_t adc1_done : 1;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t reserved0: 26;
uint32_t thres1_low: 1;
uint32_t thres0_low: 1;
uint32_t thres1_high: 1;
uint32_t thres0_high: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
uint32_t reserved0 : 26;
uint32_t thres1_low : 1;
uint32_t thres0_low : 1;
uint32_t thres1_high : 1;
uint32_t thres0_high : 1;
uint32_t adc2_done : 1;
uint32_t adc1_done : 1;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
uint32_t reserved16: 14;
uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
uint32_t apb_adc_eof_num : 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
uint32_t reserved16 : 14;
uint32_t apb_adc_reset_fsm : 1; /*reset_apb_adc_state*/
uint32_t apb_adc_trans : 1; /*enable apb_adc use spi_dma*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1;
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
uint32_t clkm_div_num : 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b : 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a : 6; /*Fractional clock divider denominator value*/
uint32_t clk_en : 1;
uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23 : 9;
};
uint32_t val;
} apb_adc_clkm_conf;
uint32_t reserved_74;
union {
struct {
uint32_t dac_timer_target: 12; /*dac_timer target*/
uint32_t dac_timer_en: 1; /*enable read dac data*/
uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
uint32_t apb_dac_trans: 1; /*enable dma_dac*/
uint32_t dac_reset_fifo: 1;
uint32_t apb_dac_rst: 1;
uint32_t dac_clk_fo: 1;
uint32_t dac_clk_gate_en: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} apb_dac_ctrl;
union {
struct {
uint32_t adc2_data: 17;
uint32_t reserved17: 15;
uint32_t adc2_data : 17;
uint32_t reserved17 : 15;
};
uint32_t val;
} apb_saradc2_data_status;
union {
struct {
uint32_t dac_clk_div: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} apb_dac_clk_ctrl;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
@ -511,11 +452,13 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /**/
uint32_t apb_ctrl_date;
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_STRUCT_H_ */

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components/soc/esp32s3/include/soc/cpu.h Normal file
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@ -0,0 +1,131 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "xtensa/corebits.h"
/* C macros for xtensa special register read/write/exchange */
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
return sp;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/**
* @brief Configure memory region protection
*
* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect) / sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/**
* @brief Stall CPU using RTC controller
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
*/
void esp_cpu_stall(int cpu_id);
/**
* @brief Un-stall CPU using RTC controller
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Reset CPU using RTC controller
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
*/
void esp_cpu_reset(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address
*
* The address of the current instruction is not stored as an exact uint32_t
* representation in PC register. This function will convert the value stored in
* the PC register to a uint32_t address.
*
* @param pc_raw The PC as stored in register format.
*
* @return Address in uint32_t format
*/
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
{
if (pc & 0x80000000) {
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
pc = (pc & 0x3fffffff) | 0x40000000;
}
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
return pc - 3;
}
typedef uint32_t esp_cpu_ccount_t;
static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
{
uint32_t result;
RSR(CCOUNT, result);
return result;
}

1867
components/soc/esp32s3/include/soc/efuse_reg.h
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components/soc/esp32s3/include/soc/efuse_struct.h
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@ -11,116 +11,303 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
uint32_t reserved_20;
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t pgm_data0;
uint32_t pgm_data1;
uint32_t pgm_data2;
uint32_t pgm_data3;
uint32_t pgm_data4;
uint32_t pgm_data5;
uint32_t pgm_data6;
uint32_t pgm_data7;
uint32_t pgm_check_value0;
uint32_t pgm_check_value1;
uint32_t pgm_check_value2;
uint32_t rd_wr_dis;
union {
struct {
uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/
uint32_t reg_dis_rtc_ram_boot : 1; /*Set this bit to disable boot from RTC RAM.*/
uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/
uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/
uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/
uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/
uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/
uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/
uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/
uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/
uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/
uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/
uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/
uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/
uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/
uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/
};
uint32_t val;
} rd_repeat_data0;
union {
struct {
uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/
uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/
uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/
uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/
uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/
uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/
uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/
uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/
uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/
uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/
uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/
uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/
uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/
uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/
uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/
};
uint32_t val;
} rd_repeat_data1;
union {
struct {
uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/
uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/
uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/
uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/
uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/
uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/
uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/
uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/
uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/
uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/
uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/
};
uint32_t val;
} rd_repeat_data2;
union {
struct {
uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_legacy_spi_boot : 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
uint32_t reg_uart_print_channel : 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
uint32_t reg_dis_usb_download_mode : 1; /*Set this bit to disable UART download mode through USB.*/
uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/
uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/
uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/
uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t reg_powerglitch_en : 1; /*Set this bit to enable power glitch function.*/
uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/
};
uint32_t val;
} rd_repeat_data3;
union {
struct {
uint32_t reg_rpt4_reserved2 : 24; /*Reserved (used for four backups method).*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} rd_repeat_data4;
uint32_t rd_mac_spi_sys_0;
union {
struct {
uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/
uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/
};
uint32_t val;
} rd_mac_spi_sys_1;
uint32_t rd_mac_spi_sys_2;
union {
struct {
uint32_t reg_spi_pad_conf_2 : 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t reg_sys_data_part0_0 : 14; /*Stores the fist 14 bits of the zeroth part of system data.*/
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4;
uint32_t rd_mac_spi_sys_5;
uint32_t rd_sys_part1_data0;
uint32_t rd_sys_part1_data1;
uint32_t rd_sys_part1_data2;
uint32_t rd_sys_part1_data3;
uint32_t rd_sys_part1_data4;
uint32_t rd_sys_part1_data5;
uint32_t rd_sys_part1_data6;
uint32_t rd_sys_part1_data7;
uint32_t rd_usr_data0;
uint32_t rd_usr_data1;
uint32_t rd_usr_data2;
uint32_t rd_usr_data3;
uint32_t rd_usr_data4;
uint32_t rd_usr_data5;
uint32_t rd_usr_data6;
uint32_t rd_usr_data7;
uint32_t rd_key0_data0;
uint32_t rd_key0_data1;
uint32_t rd_key0_data2;
uint32_t rd_key0_data3;
uint32_t rd_key0_data4;
uint32_t rd_key0_data5;
uint32_t rd_key0_data6;
uint32_t rd_key0_data7;
uint32_t rd_key1_data0;
uint32_t rd_key1_data1;
uint32_t rd_key1_data2;
uint32_t rd_key1_data3;
uint32_t rd_key1_data4;
uint32_t rd_key1_data5;
uint32_t rd_key1_data6;
uint32_t rd_key1_data7;
uint32_t rd_key2_data0;
uint32_t rd_key2_data1;
uint32_t rd_key2_data2;
uint32_t rd_key2_data3;
uint32_t rd_key2_data4;
uint32_t rd_key2_data5;
uint32_t rd_key2_data6;
uint32_t rd_key2_data7;
uint32_t rd_key3_data0;
uint32_t rd_key3_data1;
uint32_t rd_key3_data2;
uint32_t rd_key3_data3;
uint32_t rd_key3_data4;
uint32_t rd_key3_data5;
uint32_t rd_key3_data6;
uint32_t rd_key3_data7;
uint32_t rd_key4_data0;
uint32_t rd_key4_data1;
uint32_t rd_key4_data2;
uint32_t rd_key4_data3;
uint32_t rd_key4_data4;
uint32_t rd_key4_data5;
uint32_t rd_key4_data6;
uint32_t rd_key4_data7;
uint32_t rd_key5_data0;
uint32_t rd_key5_data1;
uint32_t rd_key5_data2;
uint32_t rd_key5_data3;
uint32_t rd_key5_data4;
uint32_t rd_key5_data5;
uint32_t rd_key5_data6;
uint32_t rd_key5_data7;
uint32_t rd_sys_part2_data0;
uint32_t rd_sys_part2_data1;
uint32_t rd_sys_part2_data2;
uint32_t rd_sys_part2_data3;
uint32_t rd_sys_part2_data4;
uint32_t rd_sys_part2_data5;
uint32_t rd_sys_part2_data6;
uint32_t rd_sys_part2_data7;
union {
struct {
uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_rtc_ram_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err0;
union {
struct {
uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err1;
union {
struct {
uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err2;
union {
struct {
uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_legacy_spi_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_uart_print_channel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_powerglitch_en_err : 1;
uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
uint32_t reserved_190;
union {
struct {
uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} rd_repeat_err4;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
@ -248,21 +435,12 @@ typedef volatile struct {
} dac_conf;
union {
struct {
uint32_t thr_a: 8; /*Configures the hold time of read operation.*/
uint32_t trd: 8; /*Configures the length of pulse of read operation.*/
uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/
uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/
uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/
uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/
};
uint32_t val;
} rd_tim_conf;
union {
struct {
uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/
uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/
uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/
};
uint32_t val;
} wr_tim_conf0;
uint32_t wr_tim_conf0;
union {
struct {
uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/
@ -292,3 +470,7 @@ extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EFUSE_STRUCT_H_ */

1303
components/soc/esp32s3/include/soc/extmem_reg.h
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File diff suppressed because it is too large Load Diff

151
components/soc/esp32s3/include/soc/extmem_struct.h
View File

@ -22,28 +22,28 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t dcache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/
uint32_t reserved1: 1; /*Reserved*/
uint32_t dcache_size_mode: 1; /*The bit is used to configure cache memory size.0: 32KB 1: 64KB*/
uint32_t dcache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/
uint32_t reserved4: 28;
uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
uint32_t reserved1 : 1; /*Reserved*/
uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/
uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
uint32_t reserved5 : 27;
};
uint32_t val;
} dcache_ctrl;
union {
struct {
uint32_t dcache_shut_core0_bus: 1; /*The bit is used to disable core0 dbus 0: enable 1: disable*/
uint32_t dcache_shut_core1_bus: 1; /*The bit is used to disable core1 dbus 0: enable 1: disable*/
uint32_t reserved2: 30;
uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/
uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/
uint32_t reserved2 : 30;
};
uint32_t val;
} dcache_ctrl1;
union {
struct {
uint32_t dcache_tag_mem_force_on: 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating 0: open clock gating.*/
uint32_t dcache_tag_mem_force_pd: 1; /*The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 1: power down*/
uint32_t dcache_tag_mem_force_pu: 1; /*The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 1: power up*/
uint32_t reserved3: 29;
uint32_t dcache_tag_mem_force_on : 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/
uint32_t dcache_tag_mem_force_pd : 1; /*The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down*/
uint32_t dcache_tag_mem_force_pu : 1; /*The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up*/
uint32_t reserved3 : 29;
};
uint32_t val;
} dcache_tag_power_ctrl;
@ -59,8 +59,8 @@ typedef volatile struct {
uint32_t dcache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/
union {
struct {
uint32_t dcache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
uint32_t dcache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
uint32_t dcache_prelock_sct1_size:16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
uint32_t dcache_prelock_sct0_size:16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
};
uint32_t val;
} dcache_prelock_sct_size;
@ -76,7 +76,7 @@ typedef volatile struct {
uint32_t dcache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/
union {
struct {
uint32_t dcache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
uint32_t dcache_lock_size:16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -94,7 +94,7 @@ typedef volatile struct {
uint32_t dcache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/
union {
struct {
uint32_t dcache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
uint32_t dcache_sync_size:23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
uint32_t reserved23: 9;
};
uint32_t val;
@ -110,7 +110,7 @@ typedef volatile struct {
uint32_t dcache_occupy_addr; /*The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/
union {
struct {
uint32_t dcache_occupy_size: 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
uint32_t dcache_occupy_size:16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -127,28 +127,29 @@ typedef volatile struct {
uint32_t dcache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/
union {
struct {
uint32_t dcache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
uint32_t dcache_preload_size:16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
uint32_t reserved16: 16;
};
uint32_t val;
} dcache_preload_size;
union {
struct {
uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t reserved9: 23;
uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t dcache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in dcache.*/
uint32_t reserved10: 22;
};
uint32_t val;
} dcache_autoload_ctrl;
uint32_t dcache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
union {
struct {
uint32_t dcache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t dcache_autoload_sct0_size:27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
@ -156,7 +157,7 @@ typedef volatile struct {
uint32_t dcache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
union {
struct {
uint32_t dcache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t dcache_autoload_sct1_size:27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
@ -200,8 +201,8 @@ typedef volatile struct {
uint32_t icache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
union {
struct {
uint32_t icache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
uint32_t icache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
uint32_t icache_prelock_sct1_size:16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
uint32_t icache_prelock_sct0_size:16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
};
uint32_t val;
} icache_prelock_sct_size;
@ -217,7 +218,7 @@ typedef volatile struct {
uint32_t icache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
union {
struct {
uint32_t icache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
uint32_t icache_lock_size:16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -233,7 +234,7 @@ typedef volatile struct {
uint32_t icache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
union {
struct {
uint32_t icache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
uint32_t icache_sync_size:23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
uint32_t reserved23: 9;
};
uint32_t val;
@ -250,36 +251,37 @@ typedef volatile struct {
uint32_t icache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
union {
struct {
uint32_t icache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
uint32_t icache_preload_size:16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
uint32_t reserved16: 16;
};
uint32_t val;
} icache_preload_size;
union {
struct {
uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t reserved9: 23;
uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable 0: disable.*/
uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t icache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in icache.*/
uint32_t reserved10: 22;
};
uint32_t val;
} icache_autoload_ctrl;
uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
union {
struct {
uint32_t icache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t icache_autoload_sct0_size:27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
} icache_autoload_sct0_size;
uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
union {
struct {
uint32_t icache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t icache_autoload_sct1_size:27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
@ -457,7 +459,7 @@ typedef volatile struct {
uint32_t core1_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/
union {
struct {
uint32_t cache_mmu_fault_content: 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
uint32_t cache_mmu_fault_content:16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
uint32_t cache_mmu_fault_code: 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
uint32_t reserved20: 12;
};
@ -483,8 +485,8 @@ typedef volatile struct {
} cache_mmu_power_ctrl;
union {
struct {
uint32_t icache_state: 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
uint32_t dcache_state: 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
uint32_t icache_state:12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
uint32_t dcache_state:12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
uint32_t reserved24: 8;
};
uint32_t val;
@ -515,32 +517,32 @@ typedef volatile struct {
} cache_bridge_arbiter_ctrl;
union {
struct {
uint32_t icache_preload: 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
uint32_t icache_preload: 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
uint32_t icache_preload: 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
uint32_t reserved6: 26;
uint32_t icache_preload_ist : 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
uint32_t icache_preload_iena : 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
uint32_t icache_preload_iclr : 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
uint32_t dcache_preload_ist : 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cache_preload_int_ctrl;
union {
struct {
uint32_t icache_sync: 1; /*The bit is used to indicate the interrupt by icache sync done.*/
uint32_t icache_sync: 1; /*The bit is used to enable the interrupt by icache sync done.*/
uint32_t icache_sync: 1; /*The bit is used to clear the interrupt by icache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to enable the interrupt by dcache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to clear the interrupt by dcache sync done.*/
uint32_t reserved6: 26;
uint32_t icache_sync_ist : 1; /*The bit is used to indicate the interrupt by icache sync done.*/
uint32_t icache_sync_iena : 1; /*The bit is used to enable the interrupt by icache sync done.*/
uint32_t icache_sync_iclr : 1; /*The bit is used to clear the interrupt by icache sync done.*/
uint32_t dcache_sync_ist : 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
uint32_t dcache_sync_iena : 1; /*The bit is used to enable the interrupt by dcache sync done.*/
uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cache_sync_int_ctrl;
union {
struct {
uint32_t cache_mmu_owner: 24; /*The bits are used to specify the owner of MMU.bit0: icache bit1: dcache bit2: dma bit3: reserved.*/
uint32_t reserved24: 8;
uint32_t cache_mmu_owner : 24; /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} cache_mmu_owner;
@ -605,10 +607,23 @@ typedef volatile struct {
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
union {
struct {
uint32_t icache_tag_object: 1; /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
uint32_t dcache_tag_object: 1; /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
uint32_t reserved2: 30; /*Reserved*/
};
uint32_t val;
} cache_tag_object_ctrl;
union {
struct {
uint32_t cache_tag_way_object: 3; /*Set this bits to select which way of the tag-object will be accessed. 0: way0 1: way1 2: way2 3: way3 .. 7: way7.*/
uint32_t reserved3: 29; /*Reserved*/
};
uint32_t val;
} cache_tag_way_object;
uint32_t cache_vaddr; /*Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.*/
uint32_t cache_tag_content; /*This is a constant place where we can write data to or read data from the tag memory on the specified cache.*/
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;

10397
components/soc/esp32s3/include/soc/gdma_reg.h
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645
components/soc/esp32s3/include/soc/gdma_struct.h
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@ -1,4 +1,4 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -13,312 +13,383 @@
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/
uint32_t in_remain_under_1b_l3 : 1; /*reserved*/
uint32_t in_remain_under_2b_l3 : 1; /*reserved*/
uint32_t in_remain_under_3b_l3 : 1; /*reserved*/
uint32_t in_remain_under_4b_l3 : 1; /*reserved*/
uint32_t in_buf_hungry : 1; /*reserved*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} infifo_status;
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} pop;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t suc_eof_des_addr;
uint32_t err_eof_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t rx_weight : 4; /*The weight of Rx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t in_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
} in[5];
struct {
union {
struct {
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_t reserved6 : 26;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
uint32_t out_remain_under_4b_l3 : 1; /*reserved*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status;
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} push;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t eof_des_addr;
uint32_t eof_bfr_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t tx_weight : 4; /*The weight of Tx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
} out[5];
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} conf0[5];
union {
struct {
uint32_t infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved17 : 15; /*reserved*/
};
uint32_t val;
} conf1[5];
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.*/
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.*/
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.*/
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} int_raw[5];
uint32_t reserved_3c;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} int_st[5];
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} int_ena[5];
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} int_clr[5];
union {
struct {
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/
uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/
uint32_t in_remain_under_1b_l3 : 1; /*reserved*/
uint32_t in_remain_under_2b_l3 : 1; /*reserved*/
uint32_t in_remain_under_3b_l3 : 1; /*reserved*/
uint32_t in_remain_under_4b_l3 : 1; /*reserved*/
uint32_t in_buf_hungry : 1; /*reserved*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} infifo_status[5];
union {
struct {
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/
uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
uint32_t out_remain_under_4b_l3 : 1; /*reserved*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status[5];
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} out_push[5];
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} in_pop[5];
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address.*/
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} out_link[5];
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} in_link[5];
union {
struct {
uint32_t inlink_dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} in_state[5];
union {
struct {
uint32_t outlink_dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} out_state[5];
uint32_t out_eof_des_addr[5]; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/
uint32_t in_suc_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/
uint32_t in_err_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/
uint32_t out_eof_bfr_des_addr[5]; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/
union {
struct {
uint32_t ahb_testmode : 3; /*reserved*/
uint32_t reserved3 : 1; /*reserved*/
uint32_t ahb_testaddr : 2; /*reserved*/
uint32_t reserved6 : 26; /*reserved*/
uint32_t ahb_testmode : 3; /*reserved*/
uint32_t reserved3 : 1; /*reserved*/
uint32_t ahb_testaddr : 2; /*reserved*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} ahb_test;
uint32_t in_dscr[5]; /*The address of the current inlink descriptor x.*/
uint32_t in_dscr_bf0[5]; /*The address of the last inlink descriptor x-1.*/
uint32_t in_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor x-2.*/
uint32_t out_dscr[5]; /*The address of the current outlink descriptor y.*/
uint32_t out_dscr_bf0[5]; /*The address of the last outlink descriptor y-1.*/
uint32_t out_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor y-2.*/
union {
struct {
uint32_t reserved0 : 4; /*reserved*/
uint32_t ram_force_pd : 1; /*power down*/
uint32_t ram_force_pu : 1;
uint32_t ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/
uint32_t reserved7 : 25; /*reserved*/
uint32_t reserved0 : 4; /*reserved*/
uint32_t dma_ram_force_pd : 1; /*power down*/
uint32_t dma_ram_force_pu : 1;
uint32_t dma_ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t tx_weight : 4; /*The weight of Tx channel 0.*/
uint32_t rx_weight : 4; /*The weight of Rx channel 0.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} wight[5];
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} pri[5];
union {
struct {
uint32_t ahbm_rst_inter : 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/
uint32_t ahbm_rst_exter : 1; /*Set this bit then clear this bit to reset the external ahb FSM.*/
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
uint32_t clk_en : 1;
uint32_t reserved4 : 28;
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
uint32_t clk_en : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} misc_conf;
union {
struct {
uint32_t peri_in_sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2*/
uint32_t peri_out_sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2*/
uint32_t reserved12 : 20;
};
uint32_t val;
} peri_sel[5];
union {
struct {
uint32_t in_size : 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 0. 0:16 bytes*/
uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes*/
uint32_t reserved10 : 22;
};
uint32_t val;
} sram_size[5];
uint32_t date; /*register version.*/
uint32_t date;
} gdma_dev_t;
_Static_assert(sizeof(gdma_dev_t) == 0x244, "incorrect size of gdma_dev_t.");
extern gdma_dev_t GDMA;
#ifdef __cplusplus
}
#endif

234
components/soc/esp32s3/include/soc/gpio_sd_reg.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,156 +11,162 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V) << (GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/*description: .*/
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V) << (GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
/*description: .*/
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V) << (GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/*description: .*/
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V) << (GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
/*description: .*/
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V) << (GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/*description: .*/
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V) << (GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
/*description: .*/
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V) << (GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/*description: .*/
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V) << (GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
/*description: .*/
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x10)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V) << (GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/*description: .*/
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V) << (GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
/*description: .*/
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x14)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V) << (GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/*description: .*/
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V) << (GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
/*description: .*/
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x18)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V) << (GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/*description: .*/
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V) << (GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
/*description: .*/
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x1C)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V) << (GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/*description: .*/
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V) << (GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
/*description: .*/
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
/*description: .*/
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/*description: .*/
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: */
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
/*description: .*/
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x28)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
/*description: */
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V) << (GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
/*description: .*/
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_REG_H_ */

35
components/soc/esp32s3/include/soc/gpio_sd_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,49 +11,52 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
uint32_t duty : 8;
uint32_t prescale : 8;
uint32_t reserved16 : 16;
};
uint32_t val;
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
uint32_t reserved0 : 31;
uint32_t clk_en : 1;
};
uint32_t val;
} cg;
union {
struct {
uint32_t reserved0: 30;
uint32_t function_clk_en: 1;
uint32_t spi_swap: 1;
uint32_t reserved0 : 30;
uint32_t function_clk_en : 1;
uint32_t spi_swap : 1;
};
uint32_t val;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_STRUCT_H_ */

43
components/soc/esp32s3/include/soc/gpio_sig_map.h
View File

@ -118,7 +118,8 @@
#define BB_DIAG17_IDX 52
#define I2S0I_SD3_IN_IDX 53
#define BB_DIAG18_IDX 53
#define BB_DIAG19_IDX 54
#define CORE1_GPIO_IN7_IDX 54
#define CORE1_GPIO_OUT7_IDX 54
#define USB_EXTPHY_VP_IDX 55
#define USB_EXTPHY_OEN_IDX 55
#define USB_EXTPHY_VM_IDX 56
@ -168,6 +169,10 @@
#define RMT_SIG_OUT2_IDX 83
#define RMT_SIG_IN3_IDX 84
#define RMT_SIG_OUT3_IDX 84
#define USB_JTAG_TCK_IDX 85
#define USB_JTAG_TMS_IDX 86
#define USB_JTAG_TDI_IDX 87
#define USB_JTAG_TDO_IDX 88
#define I2CEXT0_SCL_IN_IDX 89
#define I2CEXT0_SCL_OUT_IDX 89
#define I2CEXT0_SDA_IN_IDX 90
@ -226,6 +231,13 @@
#define SUBSPICS1_OUT_IDX 125
#define FSPIDQS_OUT_IDX 126
#define SPI3_CS2_OUT_IDX 127
#define I2S0O_SD1_OUT_IDX 128
#define CORE1_GPIO_IN0_IDX 129
#define CORE1_GPIO_OUT0_IDX 129
#define CORE1_GPIO_IN1_IDX 130
#define CORE1_GPIO_OUT1_IDX 130
#define CORE1_GPIO_IN2_IDX 131
#define CORE1_GPIO_OUT2_IDX 131
#define LCD_CS_IDX 132
#define CAM_DATA_IN0_IDX 133
#define LCD_DATA_OUT0_IDX 133
@ -367,16 +379,16 @@
#define ANT_SEL5_IDX 205
#define ANT_SEL6_IDX 206
#define ANT_SEL7_IDX 207
#define SIG_IN_FUNC_223_IDX 208
#define SIG_IN_FUNC223_IDX 208
#define SIG_IN_FUNC_224_IDX 209
#define SIG_IN_FUNC224_IDX 209
#define SIG_IN_FUNC_225_IDX 210
#define SIG_IN_FUNC225_IDX 210
#define SIG_IN_FUNC_226_IDX 211
#define SIG_IN_FUNC226_IDX 211
#define SIG_IN_FUNC_227_IDX 212
#define SIG_IN_FUNC227_IDX 212
#define SIG_IN_FUNC_208_IDX 208
#define SIG_IN_FUNC208_IDX 208
#define SIG_IN_FUNC_209_IDX 209
#define SIG_IN_FUNC209_IDX 209
#define SIG_IN_FUNC_210_IDX 210
#define SIG_IN_FUNC210_IDX 210
#define SIG_IN_FUNC_211_IDX 211
#define SIG_IN_FUNC211_IDX 211
#define SIG_IN_FUNC_212_IDX 212
#define SIG_IN_FUNC212_IDX 212
#define SDHOST_CDATA_IN_20_IDX 213
#define SDHOST_CDATA_OUT_20_IDX 213
#define SDHOST_CDATA_IN_21_IDX 214
@ -431,4 +443,13 @@
#define RX_STATUS_IDX 248
#define CLK_GPIO_IDX 249
#define NBT_BLE_IDX 250
#define USB_JTAG_TRST_IDX 251
#define CORE1_GPIO_IN3_IDX 252
#define CORE1_GPIO_OUT3_IDX 252
#define CORE1_GPIO_IN4_IDX 253
#define CORE1_GPIO_OUT4_IDX 253
#define CORE1_GPIO_IN5_IDX 254
#define CORE1_GPIO_OUT5_IDX 254
#define CORE1_GPIO_IN6_IDX 255
#define CORE1_GPIO_OUT6_IDX 255
#define SIG_GPIO_OUT_IDX 256

613
components/soc/esp32s3/include/soc/host_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t reserved_0;
@ -30,8 +31,8 @@ typedef volatile struct {
uint32_t reserved_1c;
union {
struct {
uint32_t func1_mdstat: 1;
uint32_t reserved1: 31;
uint32_t func1_mdstat : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} func2_2;
@ -39,384 +40,384 @@ typedef volatile struct {
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t gpio_status0; /**/
uint32_t gpio_status0;
union {
struct {
uint32_t sdio_int1: 22;
uint32_t reserved22: 10;
uint32_t sdio_int1 : 22;
uint32_t reserved22 : 10;
};
uint32_t val;
} gpio_status1;
uint32_t gpio_in0; /**/
uint32_t gpio_in0;
union {
struct {
uint32_t sdio_in1: 22;
uint32_t reserved22: 10;
uint32_t sdio_in1 : 22;
uint32_t reserved22 : 10;
};
uint32_t val;
} gpio_in1;
union {
struct {
uint32_t token0: 12;
uint32_t rx_pf_valid: 1;
uint32_t reserved13: 3;
uint32_t reg_token1: 12;
uint32_t rx_pf_eof: 4;
uint32_t token0 : 12;
uint32_t rx_pf_valid : 1;
uint32_t reserved13 : 3;
uint32_t reg_token1 : 12;
uint32_t rx_pf_eof : 4;
};
uint32_t val;
} slc0_token_rdata;
uint32_t slc0_pf; /**/
uint32_t slc0_pf;
uint32_t reserved_4c;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit0 : 1;
uint32_t tohost_bit1 : 1;
uint32_t tohost_bit2 : 1;
uint32_t tohost_bit3 : 1;
uint32_t tohost_bit4 : 1;
uint32_t tohost_bit5 : 1;
uint32_t tohost_bit6 : 1;
uint32_t tohost_bit7 : 1;
uint32_t token0_1to0 : 1;
uint32_t token1_1to0 : 1;
uint32_t token0_0to1 : 1;
uint32_t token1_0to1 : 1;
uint32_t rx_sof : 1;
uint32_t rx_eof : 1;
uint32_t rx_start : 1;
uint32_t tx_start : 1;
uint32_t rx_udf : 1;
uint32_t tx_ovf : 1;
uint32_t rx_pf_valid : 1;
uint32_t ext_bit0 : 1;
uint32_t ext_bit1 : 1;
uint32_t ext_bit2 : 1;
uint32_t ext_bit3 : 1;
uint32_t rx_new_packet : 1;
uint32_t rd_retry : 1;
uint32_t gpio_sdio : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_int_raw;
uint32_t reserved_54;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit0 : 1;
uint32_t tohost_bit1 : 1;
uint32_t tohost_bit2 : 1;
uint32_t tohost_bit3 : 1;
uint32_t tohost_bit4 : 1;
uint32_t tohost_bit5 : 1;
uint32_t tohost_bit6 : 1;
uint32_t tohost_bit7 : 1;
uint32_t token0_1to0 : 1;
uint32_t token1_1to0 : 1;
uint32_t token0_0to1 : 1;
uint32_t token1_0to1 : 1;
uint32_t rx_sof : 1;
uint32_t rx_eof : 1;
uint32_t rx_start : 1;
uint32_t tx_start : 1;
uint32_t rx_udf : 1;
uint32_t tx_ovf : 1;
uint32_t rx_pf_valid : 1;
uint32_t ext_bit0 : 1;
uint32_t ext_bit1 : 1;
uint32_t ext_bit2 : 1;
uint32_t ext_bit3 : 1;
uint32_t rx_new_packet : 1;
uint32_t rd_retry : 1;
uint32_t gpio_sdio : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_int_st;
uint32_t reserved_5c;
union {
struct {
uint32_t reg_slc0_len: 20;
uint32_t reg_slc0_len_check: 12;
uint32_t reg_slc0_len : 20;
uint32_t reg_slc0_len_check : 12;
};
uint32_t val;
} pkt_len;
union {
struct {
uint32_t state0: 8;
uint32_t state1: 8;
uint32_t state2: 8;
uint32_t state3: 8;
uint32_t state0 : 8;
uint32_t state1 : 8;
uint32_t state2 : 8;
uint32_t state3 : 8;
};
uint32_t val;
} state_w0;
union {
struct {
uint32_t state4: 8;
uint32_t state5: 8;
uint32_t state6: 8;
uint32_t state7: 8;
uint32_t state4 : 8;
uint32_t state5 : 8;
uint32_t state6 : 8;
uint32_t state7 : 8;
};
uint32_t val;
} state_w1;
union {
struct {
uint32_t conf0: 8;
uint32_t conf1: 8;
uint32_t conf2: 8;
uint32_t conf3: 8;
uint32_t conf0 : 8;
uint32_t conf1 : 8;
uint32_t conf2 : 8;
uint32_t conf3 : 8;
};
uint32_t val;
} conf_w0;
union {
struct {
uint32_t conf4: 8;
uint32_t conf5: 8;
uint32_t conf6: 8;
uint32_t conf7: 8;
uint32_t conf4 : 8;
uint32_t conf5 : 8;
uint32_t conf6 : 8;
uint32_t conf7 : 8;
};
uint32_t val;
} conf_w1;
union {
struct {
uint32_t conf8: 8;
uint32_t conf9: 8;
uint32_t conf10: 8;
uint32_t conf11: 8;
uint32_t conf8 : 8;
uint32_t conf9 : 8;
uint32_t conf10 : 8;
uint32_t conf11 : 8;
};
uint32_t val;
} conf_w2;
union {
struct {
uint32_t conf12: 8;
uint32_t conf13: 8;
uint32_t conf14: 8;
uint32_t conf15: 8;
uint32_t conf12 : 8;
uint32_t conf13 : 8;
uint32_t conf14 : 8;
uint32_t conf15 : 8;
};
uint32_t val;
} conf_w3;
union {
struct {
uint32_t conf16: 8; /*SLC timeout value*/
uint32_t conf17: 8; /*SLC timeout enable*/
uint32_t conf18: 8;
uint32_t conf19: 8; /*Interrupt to target CPU*/
uint32_t conf16 : 8; /*SLC timeout value*/
uint32_t conf17 : 8; /*SLC timeout enable*/
uint32_t conf18 : 8;
uint32_t conf19 : 8; /*Interrupt to target CPU*/
};
uint32_t val;
} conf_w4;
union {
struct {
uint32_t conf20: 8;
uint32_t conf21: 8;
uint32_t conf22: 8;
uint32_t conf23: 8;
uint32_t conf20 : 8;
uint32_t conf21 : 8;
uint32_t conf22 : 8;
uint32_t conf23 : 8;
};
uint32_t val;
} conf_w5;
union {
struct {
uint32_t win_cmd: 16;
uint32_t reserved16: 16;
uint32_t win_cmd : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} win_cmd;
union {
struct {
uint32_t conf24: 8;
uint32_t conf25: 8;
uint32_t conf26: 8;
uint32_t conf27: 8;
uint32_t conf24 : 8;
uint32_t conf25 : 8;
uint32_t conf26 : 8;
uint32_t conf27 : 8;
};
uint32_t val;
} conf_w6;
union {
struct {
uint32_t conf28: 8;
uint32_t conf29: 8;
uint32_t conf30: 8;
uint32_t conf31: 8;
uint32_t conf28 : 8;
uint32_t conf29 : 8;
uint32_t conf30 : 8;
uint32_t conf31 : 8;
};
uint32_t val;
} conf_w7;
union {
struct {
uint32_t reg_slc0_len0: 20;
uint32_t reg_slc0_len0_check: 12;
uint32_t reg_slc0_len0 : 20;
uint32_t reg_slc0_len0_check : 12;
};
uint32_t val;
} pkt_len0;
union {
struct {
uint32_t reg_slc0_len1: 20;
uint32_t reg_slc0_len1_check: 12;
uint32_t reg_slc0_len1 : 20;
uint32_t reg_slc0_len1_check : 12;
};
uint32_t val;
} pkt_len1;
union {
struct {
uint32_t reg_slc0_len2: 20;
uint32_t reg_slc0_len2_check: 12;
uint32_t reg_slc0_len2 : 20;
uint32_t reg_slc0_len2_check : 12;
};
uint32_t val;
} pkt_len2;
union {
struct {
uint32_t conf32: 8;
uint32_t conf33: 8;
uint32_t conf34: 8;
uint32_t conf35: 8;
uint32_t conf32 : 8;
uint32_t conf33 : 8;
uint32_t conf34 : 8;
uint32_t conf35 : 8;
};
uint32_t val;
} conf_w8;
union {
struct {
uint32_t conf36: 8;
uint32_t conf37: 8;
uint32_t conf38: 8;
uint32_t conf39: 8;
uint32_t conf36 : 8;
uint32_t conf37 : 8;
uint32_t conf38 : 8;
uint32_t conf39 : 8;
};
uint32_t val;
} conf_w9;
union {
struct {
uint32_t conf40: 8;
uint32_t conf41: 8;
uint32_t conf42: 8;
uint32_t conf43: 8;
uint32_t conf40 : 8;
uint32_t conf41 : 8;
uint32_t conf42 : 8;
uint32_t conf43 : 8;
};
uint32_t val;
} conf_w10;
union {
struct {
uint32_t conf44: 8;
uint32_t conf45: 8;
uint32_t conf46: 8;
uint32_t conf47: 8;
uint32_t conf44 : 8;
uint32_t conf45 : 8;
uint32_t conf46 : 8;
uint32_t conf47 : 8;
};
uint32_t val;
} conf_w11;
union {
struct {
uint32_t conf48: 8;
uint32_t conf49: 8;
uint32_t conf50: 8;
uint32_t conf51: 8;
uint32_t conf48 : 8;
uint32_t conf49 : 8;
uint32_t conf50 : 8;
uint32_t conf51 : 8;
};
uint32_t val;
} conf_w12;
union {
struct {
uint32_t conf52: 8;
uint32_t conf53: 8;
uint32_t conf54: 8;
uint32_t conf55: 8;
uint32_t conf52 : 8;
uint32_t conf53 : 8;
uint32_t conf54 : 8;
uint32_t conf55 : 8;
};
uint32_t val;
} conf_w13;
union {
struct {
uint32_t conf56: 8;
uint32_t conf57: 8;
uint32_t conf58: 8;
uint32_t conf59: 8;
uint32_t conf56 : 8;
uint32_t conf57 : 8;
uint32_t conf58 : 8;
uint32_t conf59 : 8;
};
uint32_t val;
} conf_w14;
union {
struct {
uint32_t conf60: 8;
uint32_t conf61: 8;
uint32_t conf62: 8;
uint32_t conf63: 8;
uint32_t conf60 : 8;
uint32_t conf61 : 8;
uint32_t conf62 : 8;
uint32_t conf63 : 8;
};
uint32_t val;
} conf_w15;
uint32_t check_sum0; /**/
uint32_t check_sum1; /**/
uint32_t check_sum0;
uint32_t check_sum1;
uint32_t reserved_c4;
union {
struct {
uint32_t token0_wd: 12;
uint32_t reserved12: 4;
uint32_t token1_wd: 12;
uint32_t reserved28: 4;
uint32_t token0_wd : 12;
uint32_t reserved12 : 4;
uint32_t token1_wd : 12;
uint32_t reserved28 : 4;
};
uint32_t val;
} slc0_token_wdata;
uint32_t reserved_cc;
union {
struct {
uint32_t slc0_token0_dec: 1;
uint32_t slc0_token1_dec: 1;
uint32_t slc0_token0_wr: 1;
uint32_t slc0_token1_wr: 1;
uint32_t reserved4: 4;
uint32_t slc0_len_wr: 1;
uint32_t reserved9: 23;
uint32_t slc0_token0_dec : 1;
uint32_t slc0_token1_dec : 1;
uint32_t slc0_token0_wr : 1;
uint32_t slc0_token1_wr : 1;
uint32_t reserved4 : 4;
uint32_t slc0_len_wr : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} token_con;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit0 : 1;
uint32_t tohost_bit1 : 1;
uint32_t tohost_bit2 : 1;
uint32_t tohost_bit3 : 1;
uint32_t tohost_bit4 : 1;
uint32_t tohost_bit5 : 1;
uint32_t tohost_bit6 : 1;
uint32_t tohost_bit7 : 1;
uint32_t token0_1to0 : 1;
uint32_t token1_1to0 : 1;
uint32_t token0_0to1 : 1;
uint32_t token1_0to1 : 1;
uint32_t rx_sof : 1;
uint32_t rx_eof : 1;
uint32_t rx_start : 1;
uint32_t tx_start : 1;
uint32_t rx_udf : 1;
uint32_t tx_ovf : 1;
uint32_t rx_pf_valid : 1;
uint32_t ext_bit0 : 1;
uint32_t ext_bit1 : 1;
uint32_t ext_bit2 : 1;
uint32_t ext_bit3 : 1;
uint32_t rx_new_packet : 1;
uint32_t rd_retry : 1;
uint32_t gpio_sdio : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_int_clr;
uint32_t reserved_d8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit0 : 1;
uint32_t tohost_bit1 : 1;
uint32_t tohost_bit2 : 1;
uint32_t tohost_bit3 : 1;
uint32_t tohost_bit4 : 1;
uint32_t tohost_bit5 : 1;
uint32_t tohost_bit6 : 1;
uint32_t tohost_bit7 : 1;
uint32_t token0_1to0 : 1;
uint32_t token1_1to0 : 1;
uint32_t token0_0to1 : 1;
uint32_t token1_0to1 : 1;
uint32_t rx_sof : 1;
uint32_t rx_eof : 1;
uint32_t rx_start : 1;
uint32_t tx_start : 1;
uint32_t rx_udf : 1;
uint32_t tx_ovf : 1;
uint32_t rx_pf_valid : 1;
uint32_t ext_bit0 : 1;
uint32_t ext_bit1 : 1;
uint32_t ext_bit2 : 1;
uint32_t ext_bit3 : 1;
uint32_t rx_new_packet : 1;
uint32_t rd_retry : 1;
uint32_t gpio_sdio : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_func1_int_ena;
@ -425,96 +426,96 @@ typedef volatile struct {
uint32_t reserved_e8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit0 : 1;
uint32_t tohost_bit1 : 1;
uint32_t tohost_bit2 : 1;
uint32_t tohost_bit3 : 1;
uint32_t tohost_bit4 : 1;
uint32_t tohost_bit5 : 1;
uint32_t tohost_bit6 : 1;
uint32_t tohost_bit7 : 1;
uint32_t token0_1to0 : 1;
uint32_t token1_1to0 : 1;
uint32_t token0_0to1 : 1;
uint32_t token1_0to1 : 1;
uint32_t rx_sof : 1;
uint32_t rx_eof : 1;
uint32_t rx_start : 1;
uint32_t tx_start : 1;
uint32_t rx_udf : 1;
uint32_t tx_ovf : 1;
uint32_t rx_pf_valid : 1;
uint32_t ext_bit0 : 1;
uint32_t ext_bit1 : 1;
uint32_t ext_bit2 : 1;
uint32_t ext_bit3 : 1;
uint32_t rx_new_packet : 1;
uint32_t rd_retry : 1;
uint32_t gpio_sdio : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_int_ena;
uint32_t reserved_f0;
union {
struct {
uint32_t infor: 20;
uint32_t reserved20: 12;
uint32_t infor : 20;
uint32_t reserved20 : 12;
};
uint32_t val;
} slc0_rx_infor;
uint32_t reserved_f8;
uint32_t slc0_len_wd; /**/
uint32_t apbwin_wdata; /**/
uint32_t slc0_len_wd;
uint32_t apbwin_wdata;
union {
struct {
uint32_t addr: 28;
uint32_t wr: 1;
uint32_t start: 1;
uint32_t bus: 1;
uint32_t reserved31: 1;
uint32_t addr : 28;
uint32_t wr : 1;
uint32_t start : 1;
uint32_t bus : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} apbwin_conf;
uint32_t apbwin_rdata; /**/
uint32_t apbwin_rdata;
union {
struct {
uint32_t bit7_clraddr: 9;
uint32_t bit6_clraddr: 9;
uint32_t reserved18: 14;
uint32_t bit7_clraddr : 9;
uint32_t bit6_clraddr : 9;
uint32_t reserved18 : 14;
};
uint32_t val;
} slc0_rdclr;
uint32_t reserved_110;
union {
struct {
uint32_t tohost_bit01: 1;
uint32_t tohost_bit11: 1;
uint32_t tohost_bit21: 1;
uint32_t tohost_bit31: 1;
uint32_t tohost_bit41: 1;
uint32_t tohost_bit51: 1;
uint32_t tohost_bit61: 1;
uint32_t tohost_bit71: 1;
uint32_t token0_1to01: 1;
uint32_t token1_1to01: 1;
uint32_t token0_0to11: 1;
uint32_t token1_0to11: 1;
uint32_t rx_sof1: 1;
uint32_t rx_eof1: 1;
uint32_t rx_start1: 1;
uint32_t tx_start1: 1;
uint32_t rx_udf1: 1;
uint32_t tx_ovf1: 1;
uint32_t rx_pf_valid1: 1;
uint32_t ext_bit01: 1;
uint32_t ext_bit11: 1;
uint32_t ext_bit21: 1;
uint32_t ext_bit31: 1;
uint32_t rx_new_packet1: 1;
uint32_t rd_retry1: 1;
uint32_t gpio_sdio1: 1;
uint32_t reserved26: 6;
uint32_t tohost_bit01 : 1;
uint32_t tohost_bit11 : 1;
uint32_t tohost_bit21 : 1;
uint32_t tohost_bit31 : 1;
uint32_t tohost_bit41 : 1;
uint32_t tohost_bit51 : 1;
uint32_t tohost_bit61 : 1;
uint32_t tohost_bit71 : 1;
uint32_t token0_1to01 : 1;
uint32_t token1_1to01 : 1;
uint32_t token0_0to11 : 1;
uint32_t token1_0to11 : 1;
uint32_t rx_sof1 : 1;
uint32_t rx_eof1 : 1;
uint32_t rx_start1 : 1;
uint32_t tx_start1 : 1;
uint32_t rx_udf1 : 1;
uint32_t tx_ovf1 : 1;
uint32_t rx_pf_valid1 : 1;
uint32_t ext_bit01 : 1;
uint32_t ext_bit11 : 1;
uint32_t ext_bit21 : 1;
uint32_t ext_bit31 : 1;
uint32_t rx_new_packet1 : 1;
uint32_t rd_retry1 : 1;
uint32_t gpio_sdio1 : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} slc0_int_ena1;
@ -542,8 +543,8 @@ typedef volatile struct {
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t date; /**/
uint32_t id; /**/
uint32_t date;
uint32_t id;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
@ -574,31 +575,33 @@ typedef volatile struct {
uint32_t reserved_1ec;
union {
struct {
uint32_t frc_sdio11: 5;
uint32_t frc_sdio20: 5;
uint32_t frc_neg_samp: 5;
uint32_t frc_pos_samp: 5;
uint32_t frc_quick_in: 5;
uint32_t sdio20_int_delay: 1;
uint32_t sdio_pad_pullup: 1;
uint32_t hspeed_con_en: 1;
uint32_t reserved28: 4;
uint32_t frc_sdio11 : 5;
uint32_t frc_sdio20 : 5;
uint32_t frc_neg_samp : 5;
uint32_t frc_pos_samp : 5;
uint32_t frc_quick_in : 5;
uint32_t sdio20_int_delay : 1;
uint32_t sdio_pad_pullup : 1;
uint32_t hspeed_con_en : 1;
uint32_t reserved28 : 4;
};
uint32_t val;
} conf;
union {
struct {
uint32_t sdio20_mode: 5;
uint32_t sdio_neg_samp: 5;
uint32_t sdio_quick_in: 5;
uint32_t reserved15: 17;
uint32_t sdio20_mode : 5;
uint32_t sdio_neg_samp : 5;
uint32_t sdio_quick_in : 5;
uint32_t reserved15 : 17;
};
uint32_t val;
} inf_st;
} host_dev_t;
extern host_dev_t HOST;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_HOST_STRUCT_H_ */

1058
components/soc/esp32s3/include/soc/i2c_reg.h
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File diff suppressed because it is too large Load Diff

359
components/soc/esp32s3/include/soc/i2c_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -22,56 +22,58 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t period: 9;
uint32_t reserved9: 23;
uint32_t period : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1;
uint32_t scl_force_out: 1;
uint32_t sample_scl_level: 1;
uint32_t rx_full_ack_level: 1;
uint32_t ms_mode: 1;
uint32_t trans_start: 1;
uint32_t tx_lsb_first: 1;
uint32_t rx_lsb_first: 1;
uint32_t clk_en: 1;
uint32_t arbitration_en: 1;
uint32_t fsm_rst: 1;
uint32_t conf_upgate: 1;
uint32_t slv_tx_auto_start_en: 1;
uint32_t reserved13: 19;
uint32_t sda_force_out : 1;
uint32_t scl_force_out : 1;
uint32_t sample_scl_level : 1;
uint32_t rx_full_ack_level : 1;
uint32_t ms_mode : 1;
uint32_t trans_start : 1;
uint32_t tx_lsb_first : 1;
uint32_t rx_lsb_first : 1;
uint32_t clk_en : 1;
uint32_t arbitration_en : 1;
uint32_t fsm_rst : 1;
uint32_t conf_upgate : 1;
uint32_t slv_tx_auto_start_en : 1;
uint32_t addr_10bit_rw_check_en : 1;
uint32_t addr_broadcasting_en : 1;
uint32_t reserved15 : 17;
};
uint32_t val;
} ctr;
union {
struct {
uint32_t resp_rec: 1;
uint32_t slave_rw: 1;
uint32_t reserved2: 1;
uint32_t arb_lost: 1;
uint32_t bus_busy: 1;
uint32_t slave_addressed: 1;
uint32_t reserved6: 1;
uint32_t reserved7: 1;
uint32_t rx_fifo_cnt: 6;
uint32_t stretch_cause: 2;
uint32_t reserved16: 2;
uint32_t tx_fifo_cnt: 6;
uint32_t scl_main_state_last: 3;
uint32_t reserved27: 1;
uint32_t scl_state_last: 3;
uint32_t reserved31: 1;
uint32_t resp_rec : 1;
uint32_t slave_rw : 1;
uint32_t reserved2 : 1;
uint32_t arb_lost : 1;
uint32_t bus_busy : 1;
uint32_t slave_addressed : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t rx_fifo_cnt : 6;
uint32_t stretch_cause : 2;
uint32_t reserved16 : 2;
uint32_t tx_fifo_cnt : 6;
uint32_t scl_main_state_last : 3;
uint32_t reserved27 : 1;
uint32_t scl_state_last : 3;
uint32_t reserved31 : 1;
};
uint32_t val;
} status_reg;
} sr;
union {
struct {
uint32_t time_out_value: 5;
uint32_t time_out_en: 1;
uint32_t reserved6: 26;
uint32_t tout : 5;
uint32_t time_out_en : 1;
uint32_t reserved6 : 26;
};
uint32_t val;
} timeout;
@ -85,206 +87,215 @@ typedef volatile struct {
} slave_addr;
union {
struct {
uint32_t rx_fifo_raddr: 5;
uint32_t rx_fifo_waddr: 5;
uint32_t tx_fifo_raddr: 5;
uint32_t tx_fifo_waddr: 5;
uint32_t reserved20: 1;
uint32_t reserved21: 1;
uint32_t slave_rw_point: 8;
uint32_t reserved30: 2;
uint32_t rx_fifo_raddr : 5;
uint32_t rx_fifo_waddr : 5;
uint32_t tx_fifo_raddr : 5;
uint32_t tx_fifo_waddr : 5;
uint32_t reserved20 : 1;
uint32_t reserved21 : 1;
uint32_t slave_rw_point : 8;
uint32_t reserved30 : 2;
};
uint32_t val;
} fifo_st;
union {
struct {
uint32_t rx_fifo_wm_thrhd: 5;
uint32_t tx_fifo_wm_thrhd: 5;
uint32_t nonfifo_en: 1;
uint32_t fifo_addr_cfg_en: 1;
uint32_t rx_fifo_rst: 1;
uint32_t tx_fifo_rst: 1;
uint32_t fifo_prt_en: 1;
uint32_t reserved15: 5;
uint32_t reserved20: 6;
uint32_t reserved26: 1;
uint32_t reserved27: 5;
uint32_t rx_fifo_wm_thrhd : 5;
uint32_t tx_fifo_wm_thrhd : 5;
uint32_t nonfifo_en : 1;
uint32_t fifo_addr_cfg_en : 1;
uint32_t rx_fifo_rst : 1;
uint32_t tx_fifo_rst : 1;
uint32_t fifo_prt_en : 1;
uint32_t reserved15 : 5;
uint32_t reserved20 : 6;
uint32_t reserved26 : 1;
uint32_t reserved27 : 5;
};
uint32_t val;
} fifo_conf;
union {
struct {
uint32_t data;
uint8_t data;
uint8_t reserved[3];
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
uint32_t rx_fifo_wm : 1;
uint32_t tx_fifo_wm : 1;
uint32_t rx_fifo_ovf : 1;
uint32_t end_detect : 1;
uint32_t byte_trans_done : 1;
uint32_t arbitration_lost : 1;
uint32_t mst_tx_fifo_udf : 1;
uint32_t trans_complete : 1;
uint32_t time_out : 1;
uint32_t trans_start : 1;
uint32_t nack : 1;
uint32_t tx_fifo_ovf : 1;
uint32_t rx_fifo_udf : 1;
uint32_t scl_st_to : 1;
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
uint32_t rx_fifo_wm : 1;
uint32_t tx_fifo_wm : 1;
uint32_t rx_fifo_ovf : 1;
uint32_t end_detect : 1;
uint32_t byte_trans_done : 1;
uint32_t arbitration_lost : 1;
uint32_t mst_tx_fifo_udf : 1;
uint32_t trans_complete : 1;
uint32_t time_out : 1;
uint32_t trans_start : 1;
uint32_t nack : 1;
uint32_t tx_fifo_ovf : 1;
uint32_t rx_fifo_udf : 1;
uint32_t scl_st_to : 1;
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
uint32_t rx_fifo_wm : 1;
uint32_t tx_fifo_wm : 1;
uint32_t rx_fifo_ovf : 1;
uint32_t end_detect : 1;
uint32_t byte_trans_done : 1;
uint32_t arbitration_lost : 1;
uint32_t mst_tx_fifo_udf : 1;
uint32_t trans_complete : 1;
uint32_t time_out : 1;
uint32_t trans_start : 1;
uint32_t nack : 1;
uint32_t tx_fifo_ovf : 1;
uint32_t rx_fifo_udf : 1;
uint32_t scl_st_to : 1;
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_fifo_wm: 1;
uint32_t tx_fifo_wm: 1;
uint32_t rx_fifo_ovf: 1;
uint32_t end_detect: 1;
uint32_t byte_trans_done: 1;
uint32_t arbitration_lost: 1;
uint32_t mst_tx_fifo_udf: 1;
uint32_t trans_complete: 1;
uint32_t time_out: 1;
uint32_t trans_start: 1;
uint32_t nack: 1;
uint32_t tx_fifo_ovf: 1;
uint32_t rx_fifo_udf: 1;
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t slave_stretch: 1;
uint32_t reserved17: 15;
uint32_t rx_fifo_wm : 1;
uint32_t tx_fifo_wm : 1;
uint32_t rx_fifo_ovf : 1;
uint32_t end_detect : 1;
uint32_t byte_trans_done : 1;
uint32_t arbitration_lost : 1;
uint32_t mst_tx_fifo_udf : 1;
uint32_t trans_complete : 1;
uint32_t time_out : 1;
uint32_t trans_start : 1;
uint32_t nack : 1;
uint32_t tx_fifo_ovf : 1;
uint32_t rx_fifo_udf : 1;
uint32_t scl_st_to : 1;
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_status;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sda_hold;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sda_sample;
union {
struct {
uint32_t period: 9;
uint32_t scl_wait_high_period: 7;
uint32_t reserved16: 16;
uint32_t period : 9;
uint32_t scl_wait_high_period : 7;
uint32_t reserved16 : 16;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} scl_start_hold;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} scl_rstart_setup;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} scl_stop_hold;
union {
struct {
uint32_t time: 9;
uint32_t reserved9: 23;
uint32_t time : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t scl_thres: 4;
uint32_t sda_thres: 4;
uint32_t scl_en: 1;
uint32_t sda_en: 1;
uint32_t reserved10: 22;
uint32_t scl_thres : 4;
uint32_t sda_thres : 4;
uint32_t scl_en : 1;
uint32_t sda_en : 1;
uint32_t reserved10 : 22;
};
uint32_t val;
} filter_cfg;
union {
struct {
uint32_t sclk_div_num: 8;
uint32_t sclk_div_a: 6;
uint32_t sclk_div_b: 6;
uint32_t sclk_sel: 1;
uint32_t sclk_active: 1;
uint32_t reserved22: 10;
uint32_t sclk_div_num : 8;
uint32_t sclk_div_a : 6;
uint32_t sclk_div_b : 6;
uint32_t sclk_sel : 1;
uint32_t sclk_active : 1;
uint32_t reserved22 : 10;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t command0: 14;
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1;
};
@ -292,34 +303,36 @@ typedef volatile struct {
} command[8];
union {
struct {
uint32_t scl_st_to: 5; /*no more than 23*/
uint32_t reserved5: 27;
uint32_t scl_st_to : 5; /*no more than 23*/
uint32_t reserved5 : 27;
};
uint32_t val;
} scl_st_time_out;
union {
struct {
uint32_t scl_main_st_to: 5; /*no more than 23*/
uint32_t reserved5: 27;
uint32_t scl_main_st_to : 5; /*no more than 23*/
uint32_t reserved5 : 27;
};
uint32_t val;
} scl_main_st_time_out;
union {
struct {
uint32_t scl_rst_slv_en: 1;
uint32_t scl_rst_slv_num: 5;
uint32_t scl_pd_en: 1;
uint32_t sda_pd_en: 1;
uint32_t reserved8: 24;
uint32_t scl_rst_slv_en : 1;
uint32_t scl_rst_slv_num : 5;
uint32_t scl_pd_en : 1;
uint32_t sda_pd_en : 1;
uint32_t reserved8 : 24;
};
uint32_t val;
} scl_sp_conf;
union {
struct {
uint32_t stretch_protect_num: 10;
uint32_t slave_scl_stretch_en: 1;
uint32_t slave_scl_stretch_clr: 1;
uint32_t reserved12: 20;
uint32_t stretch_protect_num : 10;
uint32_t slave_scl_stretch_en : 1;
uint32_t slave_scl_stretch_clr : 1;
uint32_t slave_byte_ack_ctl_en : 1;
uint32_t slave_byte_ack_level : 1;
uint32_t reserved14 : 18;
};
uint32_t val;
} scl_stretch_conf;
@ -351,9 +364,9 @@ typedef volatile struct {
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t date;
uint32_t reserved_fc;
uint32_t txfifo_start_addr; /**/
uint32_t txfifo_start_addr;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
@ -385,12 +398,10 @@ typedef volatile struct {
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t fifo_start_addr; /**/
uint32_t rxfifo_start_addr;
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifdef __cplusplus
}
#endif

1758
components/soc/esp32s3/include/soc/i2s_reg.h
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File diff suppressed because it is too large Load Diff

391
components/soc/esp32s3/include/soc/i2s_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,289 +11,316 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
union {
struct {
uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4: 28; /*Reserve*/
uint32_t rx_done : 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done : 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung : 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung : 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4 : 28; /*Reserve*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4: 28; /*Reserve*/
uint32_t rx_done : 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done : 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung : 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung : 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4 : 28; /*Reserve*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4: 28; /*Reserve*/
uint32_t rx_done : 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/
uint32_t tx_done : 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/
uint32_t rx_hung : 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung : 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t reserved4 : 28; /*Reserve*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/
uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t reserved4: 28; /*Reserve*/
uint32_t rx_done : 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/
uint32_t tx_done : 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/
uint32_t rx_hung : 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung : 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t reserved4 : 28; /*Reserve*/
};
uint32_t val;
} int_clr;
uint32_t reserved_1c;
union {
struct {
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t reserved4: 1; /*Reserved*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t reserved6: 1;
uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
uint32_t rx_sinc_dsr_16_en: 1;
uint32_t reserved23: 9; /*Reserve*/
uint32_t rx_reset : 1; /*Set this bit to reset receiver*/
uint32_t rx_fifo_reset : 1; /*Set this bit to reset Rx AFIFO*/
uint32_t rx_start : 1; /*Set this bit to start receiving data*/
uint32_t rx_slave_mod : 1; /*Set this bit to enable slave receiver mode*/
uint32_t reserved4 : 1; /* Reserved*/
uint32_t rx_mono : 1; /*Set this bit to enable receiver in mono mode*/
uint32_t reserved6 : 1; /*Reserve*/
uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t rx_update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t rx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
uint32_t rx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t rx_stop_mode : 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
uint32_t rx_24_fill_en : 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_t rx_ws_idle_pol : 1; /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */
uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/
uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
uint32_t rx_pdm2pcm_en : 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
uint32_t rx_pdm_sinc_dsr_16_en : 1; /*Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64.*/
uint32_t reserved23 : 9; /*Reserve*/
};
uint32_t val;
} rx_conf;
union {
struct {
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t reserved4: 1; /*Reserved*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t reserved14: 1;
uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/
uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
uint32_t reserved21: 3; /*Reserved*/
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t reserved28: 4; /*Reserved*/
uint32_t tx_reset : 1; /*Set this bit to reset transmitter*/
uint32_t tx_fifo_reset : 1; /*Set this bit to reset Tx AFIFO*/
uint32_t tx_start : 1; /*Set this bit to start transmitting data */
uint32_t tx_slave_mod : 1; /*Set this bit to enable slave transmitter mode */
uint32_t reserved4 : 1; /* Reserved*/
uint32_t tx_mono : 1; /*Set this bit to enable transmitter in mono mode */
uint32_t tx_chan_equal : 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_t tx_big_endian : 1; /*I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_update : 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t reserved14 : 1; /* Reserved*/
uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
uint32_t tx_ws_idle_pol : 1; /*0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. */
uint32_t tx_bit_order : 1; /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/
uint32_t tx_tdm_en : 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
uint32_t tx_pdm_en : 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
uint32_t reserved21 : 3; /*Reserved*/
uint32_t tx_chan_mod : 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t sig_loopback : 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t reserved28 : 4; /*Reserve*/
};
uint32_t val;
} tx_conf;
union {
struct {
uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/
uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t reserved30: 2; /*Reserved*/
uint32_t rx_tdm_ws_width : 7; /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
uint32_t rx_bck_div_num : 6; /*Bit clock configuration bits in receiver mode. */
uint32_t rx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t rx_half_sample_bits : 6; /*I2S Rx half sample bits -1.*/
uint32_t rx_tdm_chan_bits : 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
uint32_t rx_msb_shift : 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t reserved30 : 2; /* Reserved*/
};
uint32_t val;
} rx_conf1;
union {
struct {
uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t reserved30: 2; /*Reserved*/
uint32_t tx_tdm_ws_width : 7; /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
uint32_t tx_bck_div_num : 6; /*Bit clock configuration bits in transmitter mode. */
uint32_t tx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t tx_half_sample_bits : 6; /* I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits : 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
uint32_t tx_msb_shift : 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t tx_bck_no_dly : 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
uint32_t reserved31 : 1; /* Reserved*/
};
uint32_t val;
} tx_conf1;
union {
struct {
uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
uint32_t reserved30: 2; /*Reserved*/
uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/
uint32_t reserved8 : 18; /* Reserved*/
uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */
uint32_t reserved30 : 2; /* Reserved*/
};
uint32_t val;
} rx_clkm_conf;
union {
struct {
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t reserved30: 2; /*Reserved*/
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} tx_clkm_conf;
union {
struct {
uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
uint32_t reserved28: 4; /*Reserved*/
uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32_t val;
} rx_clkm_div_conf;
union {
struct {
uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
uint32_t reserved28: 4; /*Reserved*/
uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32_t val;
} tx_clkm_div_conf;
uint32_t reserved_40;
uint32_t reserved_44;
union {
struct {
uint32_t txhp_bypass: 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
uint32_t tx_sinc_osr2: 4; /*I2S TX PDM OSR2 value*/
uint32_t tx_prescale: 8; /*I2S TX PDM prescale for sigmadelta*/
uint32_t tx_hp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_lp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sinc_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sigmadelta_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sigmadelta_dither2: 1; /*I2S TX PDM sigmadelta dither2 value*/
uint32_t tx_sigmadelta_dither: 1; /*I2S TX PDM sigmadelta dither value*/
uint32_t tx_dac_2out_en: 1; /*I2S TX PDM dac mode enable*/
uint32_t tx_dac_mode_en: 1; /*I2S TX PDM dac 2channel enable*/
uint32_t pcm2pdm_conv_en: 1; /*I2S TX PDM Converter enable*/
uint32_t reserved26: 6; /*Reserved*/
};
uint32_t val;
} tx_pcm2pdm_conf;
union {
struct {
uint32_t tx_pdm_fp: 10; /*I2S TX PDM Fp*/
uint32_t tx_pdm_fs: 10; /*I2S TX PDM Fs*/
uint32_t tx_iir_hp_mult12_5: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
uint32_t tx_iir_hp_mult12_0: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
uint32_t reserved26: 6; /*Reserved*/
};
uint32_t val;
} tx_pcm2pdm_conf1;
uint32_t reserved_48;
uint32_t reserved_4c;
union {
struct {
uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
uint32_t reserved20: 12; /*Reserved*/
uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
uint32_t reserved20: 12; /*Reserved*/
};
uint32_t val;
} rx_tdm_ctrl;
union {
struct {
uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
uint32_t reserved21: 11; /*Reserved*/
uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
uint32_t reserved21: 11; /*Reserved*/
};
uint32_t val;
} tx_tdm_ctrl;
union {
struct {
uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 2;
uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6: 2;
uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved10: 2;
uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved14: 2;
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2;
uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2;
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2; /*Reserved*/
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2; /*Reserved*/
uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2; /*Reserved*/
uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} rx_timing;
union {
struct {
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 14; /*Reserved*/
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2;
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2;
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 2; /*Reserved*/
uint32_t tx_sd1_out_dm: 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6: 10; /*Reserved*/
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2; /*Reserved*/
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2; /*Reserved*/
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2; /*Reserved*/
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} tx_timing;
union {
struct {
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20; /*Reserved*/
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20; /*Reserved*/
};
uint32_t val;
} lc_hung_conf;
union {
struct {
uint32_t rx_eof_num: 12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t reserved12: 20; /*Reserved*/
uint32_t rx_eof_num:12; /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
uint32_t reserved12:20; /*Reserved*/
};
uint32_t val;
} rx_eof_num;
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
} rxeof_num;
uint32_t conf_sigle_data; /*I2S signal data register*/
union {
struct {
uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
uint32_t reserved1: 31; /*Reserved*/
uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
uint32_t reserved1: 31; /*Reserved*/
};
uint32_t val;
} state;
@ -303,16 +330,16 @@ typedef volatile struct {
uint32_t reserved_7c;
union {
struct {
uint32_t date: 28; /*Version control register*/
uint32_t reserved28: 4; /*Reserved*/
uint32_t date: 28; /*I2S version control register*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32_t val;
} date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2S_STRUCT_H_ */

1057
components/soc/esp32s3/include/soc/interrupt_core0_reg.h
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118
components/soc/esp32s3/include/soc/interrupt_core0_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_
#define _SOC_INTERRUPT_CORE0_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
@ -484,39 +482,74 @@ typedef volatile struct {
} core0_apb_adc_int_map;
union {
struct {
uint32_t core0_dma_ch0_int_map: 5;
uint32_t reserved5: 27;
uint32_t core0_dma_in_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch0_int_map;
} core0_dma_in_ch0_int_map;
union {
struct {
uint32_t core0_dma_ch1_int_map: 5;
uint32_t reserved5: 27;
uint32_t core0_dma_in_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch1_int_map;
} core0_dma_in_ch1_int_map;
union {
struct {
uint32_t core0_dma_ch2_int_map: 5;
uint32_t reserved5: 27;
uint32_t core0_dma_in_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch2_int_map;
} core0_dma_in_ch2_int_map;
union {
struct {
uint32_t core0_dma_ch3_int_map: 5;
uint32_t reserved5: 27;
uint32_t core0_dma_in_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch3_int_map;
} core0_dma_in_ch3_int_map;
union {
struct {
uint32_t core0_dma_ch4_int_map: 5;
uint32_t reserved5: 27;
uint32_t core0_dma_in_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch4_int_map;
} core0_dma_in_ch4_int_map;
union {
struct {
uint32_t core0_dma_out_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch0_int_map;
union {
struct {
uint32_t core0_dma_out_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch1_int_map;
union {
struct {
uint32_t core0_dma_out_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch2_int_map;
union {
struct {
uint32_t core0_dma_out_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch3_int_map;
union {
struct {
uint32_t core0_dma_out_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch4_int_map;
union {
struct {
uint32_t core0_rsa_int_map: 5;
@ -636,6 +669,13 @@ typedef volatile struct {
};
uint32_t val;
} core0_core_1_pif_pms_monitor_violate_size_intr_map;
union {
struct {
uint32_t core0_backup_pms_violate_intr_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_backup_pms_violate_intr_map;
union {
struct {
uint32_t core0_cache_core0_acs_int_map: 5;
@ -650,9 +690,31 @@ typedef volatile struct {
};
uint32_t val;
} core0_cache_core1_acs_int_map;
union {
struct {
uint32_t core0_usb_device_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_usb_device_int_map;
union {
struct {
uint32_t core0_peri_backup_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_peri_backup_int_map;
union {
struct {
uint32_t core0_dma_extmem_reject_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_extmem_reject_int_map;
uint32_t core0_intr_status_0; /**/
uint32_t core0_intr_status_1; /**/
uint32_t core0_intr_status_2; /**/
uint32_t core0_intr_status_3; /**/
union {
struct {
uint32_t core0_clk_en: 1;
@ -660,16 +722,6 @@ typedef volatile struct {
};
uint32_t val;
} core0_clock_gate;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
@ -1079,15 +1131,15 @@ typedef volatile struct {
uint32_t reserved_7f8;
union {
struct {
uint32_t core0_interrupt_date: 28;
uint32_t core0_interrupt_date:28;
uint32_t reserved28: 4;
};
uint32_t val;
} core0_interrupt_date;
} interrupt_core0_dev_t;
extern interrupt_core0_dev_t INTERRUPT_CORE0;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_INTERRUPT_CORE0_STRUCT_H_ */

1057
components/soc/esp32s3/include/soc/interrupt_core1_reg.h
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components/soc/esp32s3/include/soc/interrupt_core1_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_
#define _SOC_INTERRUPT_CORE1_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
@ -996,39 +994,74 @@ typedef volatile struct {
} core1_apb_adc_int_map;
union {
struct {
uint32_t core1_dma_ch0_int_map: 5;
uint32_t reserved5: 27;
uint32_t core1_dma_in_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch0_int_map;
} core1_dma_in_ch0_int_map;
union {
struct {
uint32_t core1_dma_ch1_int_map: 5;
uint32_t reserved5: 27;
uint32_t core1_dma_in_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch1_int_map;
} core1_dma_in_ch1_int_map;
union {
struct {
uint32_t core1_dma_ch2_int_map: 5;
uint32_t reserved5: 27;
uint32_t core1_dma_in_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch2_int_map;
} core1_dma_in_ch2_int_map;
union {
struct {
uint32_t core1_dma_ch3_int_map: 5;
uint32_t reserved5: 27;
uint32_t core1_dma_in_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch3_int_map;
} core1_dma_in_ch3_int_map;
union {
struct {
uint32_t core1_dma_ch4_int_map: 5;
uint32_t reserved5: 27;
uint32_t core1_dma_in_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch4_int_map;
} core1_dma_in_ch4_int_map;
union {
struct {
uint32_t core1_dma_out_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch0_int_map;
union {
struct {
uint32_t core1_dma_out_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch1_int_map;
union {
struct {
uint32_t core1_dma_out_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch2_int_map;
union {
struct {
uint32_t core1_dma_out_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch3_int_map;
union {
struct {
uint32_t core1_dma_out_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch4_int_map;
union {
struct {
uint32_t core1_rsa_int_map: 5;
@ -1148,6 +1181,13 @@ typedef volatile struct {
};
uint32_t val;
} core1_core_1_pif_pms_monitor_violate_size_intr_map;
union {
struct {
uint32_t core1_backup_pms_violate_intr_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_backup_pms_violate_intr_map;
union {
struct {
uint32_t core1_cache_core0_acs_int_map: 5;
@ -1162,9 +1202,31 @@ typedef volatile struct {
};
uint32_t val;
} core1_cache_core1_acs_int_map;
union {
struct {
uint32_t core1_usb_device_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_usb_device_int_map;
union {
struct {
uint32_t core1_peri_backup_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_peri_backup_int_map;
union {
struct {
uint32_t core1_dma_extmem_reject_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_extmem_reject_int_map;
uint32_t core1_intr_status_0; /**/
uint32_t core1_intr_status_1; /**/
uint32_t core1_intr_status_2; /**/
uint32_t core1_intr_status_3; /**/
union {
struct {
uint32_t core1_clk_en: 1;
@ -1172,16 +1234,6 @@ typedef volatile struct {
};
uint32_t val;
} core1_clock_gate;
uint32_t reserved_978;
uint32_t reserved_97c;
uint32_t reserved_980;
uint32_t reserved_984;
uint32_t reserved_988;
uint32_t reserved_98c;
uint32_t reserved_990;
uint32_t reserved_994;
uint32_t reserved_998;
uint32_t reserved_99c;
uint32_t reserved_9a0;
uint32_t reserved_9a4;
uint32_t reserved_9a8;
@ -1591,15 +1643,15 @@ typedef volatile struct {
uint32_t reserved_ff8;
union {
struct {
uint32_t core1_interrupt_date: 28;
uint32_t core1_interrupt_date:28;
uint32_t reserved28: 4;
};
uint32_t val;
} core1_interrupt_date;
} interrupt_core1_dev_t;
extern interrupt_core1_dev_t INTERRUPT_CORE1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_INTERRUPT_CORE1_STRUCT_H_ */

1360
components/soc/esp32s3/include/soc/lcd_cam_reg.h
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4703
components/soc/esp32s3/include/soc/mcpwm_reg.h
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555
components/soc/esp32s3/include/soc/mcpwm_struct.h
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@ -13,446 +13,443 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct mcpwm_dev_s {
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t prescale: 8;
uint32_t reserved8: 24;
uint32_t prescale : 8;
uint32_t reserved8 : 24;
};
uint32_t val;
} clk_cfg;
struct {
union {
struct {
uint32_t prescale: 8;
uint32_t period: 16;
uint32_t upmethod: 2; /*0: immediate 1: eqz 2: sync 3: eqz | sync*/
uint32_t reserved26: 6;
uint32_t prescale : 8;
uint32_t period : 16;
uint32_t upmethod : 2; /*0: immediate, 1: eqz, 2: sync, 3: eqz | sync*/
uint32_t reserved26 : 6;
};
uint32_t val;
} period;
union {
struct {
uint32_t start: 3; /*0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop @ next eqz 4: start and stop @ next eqp*/
uint32_t mode: 2; /*0: freeze 1: inc 2: dec 3: up-down*/
uint32_t reserved5: 27;
uint32_t start : 3; /*0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: start and stop @ next eqp,*/
uint32_t mod : 2; /* 0: freeze, 1: inc, 2: dec, 3: up-down*/
uint32_t reserved5 : 27;
};
uint32_t val;
} mode;
union {
struct {
uint32_t in_en: 1;
uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/
uint32_t out_sel: 2;
uint32_t timer_phase: 16;
uint32_t phase_direct : 1;
uint32_t reserved21: 11;
uint32_t in_en : 1;
uint32_t sync_sw : 1; /*write the negate value will trigger a sw sync*/
uint32_t out_sel : 2;
uint32_t phase : 17;
uint32_t reserved21 : 11;
};
uint32_t val;
} sync;
union {
struct {
uint32_t value: 16;
uint32_t direction: 1;
uint32_t reserved17: 15;
uint32_t value : 16;
uint32_t direction : 1;
uint32_t reserved17 : 15;
};
uint32_t val;
} status;
} timer[3];
union {
struct {
uint32_t t0_in_sel: 3;
uint32_t t1_in_sel: 3;
uint32_t t2_in_sel: 3;
uint32_t ext_in0_inv: 1;
uint32_t ext_in1_inv: 1;
uint32_t ext_in2_inv: 1;
uint32_t reserved12: 20;
uint32_t t0_in_sel : 3;
uint32_t t1_in_sel : 3;
uint32_t t2_in_sel : 3;
uint32_t ext_in0_inv : 1;
uint32_t ext_in1_inv : 1;
uint32_t ext_in2_inv : 1;
uint32_t reserved12 : 20;
};
uint32_t val;
} timer_synci_cfg;
union {
struct {
uint32_t operator0_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t operator1_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t operator2_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t reserved6: 26;
uint32_t operator0_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t operator1_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t operator2_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t reserved6 : 26;
};
uint32_t val;
} timer_sel;
struct {
union {
struct {
uint32_t a_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t b_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t a_shdw_full: 1;
uint32_t b_shdw_full: 1;
uint32_t reserved10: 22;
uint32_t a_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t b_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t a_shdw_full : 1;
uint32_t b_shdw_full : 1;
uint32_t reserved10 : 22;
};
uint32_t val;
} cmpr_cfg;
union {
struct {
uint32_t cmpr_val: 16;
uint32_t reserved16: 16;
uint32_t cmpr_val : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} cmpr_value[2];
union {
struct {
uint32_t upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/
uint32_t t0_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
uint32_t t1_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
uint32_t reserved10: 22;
uint32_t upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze*/
uint32_t t0_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/
uint32_t t1_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/
uint32_t reserved10 : 22;
};
uint32_t val;
} gen_cfg0;
union {
struct {
uint32_t cntu_force_upmethod: 6; /*0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: sync bit5: freeze*/
uint32_t a_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t b_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t a_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
uint32_t a_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t b_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
uint32_t b_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t reserved16: 16;
uint32_t cntu_force_upmethod : 6; /*0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: freeze*/
uint32_t a_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t b_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t a_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/
uint32_t a_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t b_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/
uint32_t b_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t reserved16 : 16;
};
uint32_t val;
} gen_force;
union {
struct {
uint32_t utez: 2;
uint32_t utep: 2;
uint32_t utea: 2;
uint32_t uteb: 2;
uint32_t ut0: 2;
uint32_t ut1: 2;
uint32_t dtez: 2;
uint32_t dtep: 2;
uint32_t dtea: 2;
uint32_t dteb: 2;
uint32_t dt0: 2;
uint32_t dt1: 2; /*0: no change 1: low 2: high 3: toggle*/
uint32_t reserved24: 8;
uint32_t utez : 2;
uint32_t utep : 2;
uint32_t utea : 2;
uint32_t uteb : 2;
uint32_t ut0 : 2;
uint32_t ut1 : 2;
uint32_t dtez : 2;
uint32_t dtep : 2;
uint32_t dtea : 2;
uint32_t dteb : 2;
uint32_t dt0 : 2;
uint32_t dt1 : 2; /*0: no change, 1: low, 2: high, 3: toggle*/
uint32_t reserved24 : 8;
};
uint32_t val;
} generator[2];
union {
struct {
uint32_t fed_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t red_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t deb_mode: 1; /*immediate dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
uint32_t a_outswap: 1;
uint32_t b_outswap: 1;
uint32_t red_insel: 1;
uint32_t fed_insel: 1;
uint32_t red_outinvert: 1;
uint32_t fed_outinvert: 1;
uint32_t a_outbypass: 1;
uint32_t b_outbypass: 1;
uint32_t clk_sel: 1;
uint32_t reserved18: 14;
uint32_t fed_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t red_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t deb_mode : 1; /*immediate, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode*/
uint32_t a_outswap : 1;
uint32_t b_outswap : 1;
uint32_t red_insel : 1;
uint32_t fed_insel : 1;
uint32_t red_outinvert : 1;
uint32_t fed_outinvert : 1;
uint32_t a_outbypass : 1;
uint32_t b_outbypass : 1;
uint32_t clk_sel : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} db_cfg;
union {
struct {
uint32_t fed: 16;
uint32_t reserved16: 16;
uint32_t fed : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} db_fed_cfg;
union {
struct {
uint32_t red: 16;
uint32_t reserved16: 16;
uint32_t red : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} db_red_cfg;
union {
struct {
uint32_t en: 1;
uint32_t prescale: 4;
uint32_t duty: 3;
uint32_t oshtwth: 4;
uint32_t out_invert: 1;
uint32_t in_invert: 1;
uint32_t reserved14: 18;
uint32_t en : 1;
uint32_t prescale : 4;
uint32_t duty : 3;
uint32_t oshtwth : 4;
uint32_t out_invert : 1;
uint32_t in_invert : 1;
uint32_t reserved14 : 18;
};
uint32_t val;
} carrier_cfg;
union {
struct {
uint32_t sw_cbc: 1; /*0: disable 1: enable*/
uint32_t f2_cbc: 1; /*0: disable 1: enable*/
uint32_t f1_cbc: 1; /*0: disable 1: enable*/
uint32_t f0_cbc: 1; /*0: disable 1: enable*/
uint32_t sw_ost: 1; /*0: disable 1: enable*/
uint32_t f2_ost: 1; /*0: disable 1: enable*/
uint32_t f1_ost: 1; /*0: disable 1: enable*/
uint32_t f0_ost: 1; /*0: disable 1: enable*/
uint32_t a_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t reserved24: 8;
uint32_t sw_cbc : 1; /*0: disable, 1: enable*/
uint32_t f2_cbc : 1; /*0: disable, 1: enable*/
uint32_t f1_cbc : 1; /*0: disable, 1: enable*/
uint32_t f0_cbc : 1; /*0: disable, 1: enable*/
uint32_t sw_ost : 1; /*0: disable, 1: enable*/
uint32_t f2_ost : 1; /*0: disable, 1: enable*/
uint32_t f1_ost : 1; /*0: disable, 1: enable*/
uint32_t f0_ost : 1; /*0: disable, 1: enable*/
uint32_t a_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t reserved24 : 8;
};
uint32_t val;
} tz_cfg0;
union {
struct {
uint32_t clr_ost: 1; /*a toggle will clear oneshot tripping*/
uint32_t cbcpulse: 2; /*bit0: tez bit1: tep*/
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping*/
uint32_t force_ost: 1; /*a toggle trigger a oneshot tripping*/
uint32_t reserved5: 27;
uint32_t clr_ost : 1; /*a toggle will clear oneshot tripping*/
uint32_t cbcpulse : 2; /*bit0: tez, bit1: tep*/
uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping*/
uint32_t force_ost : 1; /*a toggle trigger a oneshot tripping*/
uint32_t reserved5 : 27;
};
uint32_t val;
} tz_cfg1;
union {
struct {
uint32_t cbc_on: 1;
uint32_t ost_on: 1;
uint32_t reserved2: 30;
uint32_t cbc_on : 1;
uint32_t ost_on : 1;
uint32_t reserved2 : 30;
};
uint32_t val;
} tz_status;
} channel[3];
union {
struct {
uint32_t f0_en: 1;
uint32_t f1_en: 1;
uint32_t f2_en: 1;
uint32_t f0_pole: 1;
uint32_t f1_pole: 1;
uint32_t f2_pole: 1;
uint32_t event_f0: 1;
uint32_t event_f1: 1;
uint32_t event_f2: 1;
uint32_t reserved9: 23;
uint32_t f0_en : 1;
uint32_t f1_en : 1;
uint32_t f2_en : 1;
uint32_t f0_pole : 1;
uint32_t f1_pole : 1;
uint32_t f2_pole : 1;
uint32_t event_f0 : 1;
uint32_t event_f1 : 1;
uint32_t event_f2 : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} fault_detect;
union {
struct {
uint32_t timer_en: 1;
uint32_t synci_en: 1;
uint32_t synci_sel: 3;
uint32_t sync_sw: 1; /*Write 1 will force a timer sync*/
uint32_t reserved6: 26;
uint32_t timer_en : 1;
uint32_t synci_en : 1;
uint32_t synci_sel : 3;
uint32_t sync_sw : 1; /*Write 1 will force a timer sync*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cap_timer_cfg;
uint32_t cap_timer_phase; /**/
uint32_t cap_timer_phase;
union {
struct {
uint32_t en: 1;
uint32_t mode: 2; /*bit0: negedge cap en bit1: posedge cap en*/
uint32_t prescale: 8;
uint32_t in_invert: 1;
uint32_t sw: 1; /*Write 1 will trigger a sw capture*/
uint32_t reserved13: 19;
uint32_t en : 1;
uint32_t mode : 2; /*bit0: negedge cap en, bit1: posedge cap en*/
uint32_t prescale : 8;
uint32_t in_invert : 1;
uint32_t sw : 1; /*Write 1 will trigger a sw capture*/
uint32_t reserved13 : 19;
};
uint32_t val;
} cap_cfg_ch[3];
uint32_t cap_val_ch[3]; /**/
uint32_t cap_val_ch[3];
union {
struct {
uint32_t cap0_edge: 1;
uint32_t cap1_edge: 1;
uint32_t cap2_edge: 1; /*cap trigger's edge 0: posedge 1: negedge*/
uint32_t reserved3: 29;
uint32_t cap0_edge : 1;
uint32_t cap1_edge : 1;
uint32_t cap2_edge : 1; /*cap trigger's edge, 0: posedge, 1: negedge*/
uint32_t reserved3 : 29;
};
uint32_t val;
} cap_status;
union {
struct {
uint32_t global_up_en: 1;
uint32_t global_force_up: 1; /*a toggle will trigger a force update all timers and operators will update their active regs*/
uint32_t op0_up_en: 1;
uint32_t op0_force_up: 1; /*a toggle will trigger a force update*/
uint32_t op1_up_en: 1;
uint32_t op1_force_up: 1; /*a toggle will trigger a force update*/
uint32_t op2_up_en: 1; /*reg update local enable*/
uint32_t op2_force_up: 1; /*a toggle will trigger a force update*/
uint32_t reserved8: 24;
uint32_t global_up_en : 1;
uint32_t global_force_up : 1; /*a toggle will trigger a force update, all timers and operators will update their active regs*/
uint32_t op0_up_en : 1;
uint32_t op0_force_up : 1; /*a toggle will trigger a force update*/
uint32_t op1_up_en : 1;
uint32_t op1_force_up : 1; /*a toggle will trigger a force update*/
uint32_t op2_up_en : 1; /*reg update local enable*/
uint32_t op2_force_up : 1; /*a toggle will trigger a force update*/
uint32_t reserved8 : 24;
};
uint32_t val;
} update_cfg;
union {
struct {
uint32_t timer0_stop: 1;
uint32_t timer1_stop: 1;
uint32_t timer2_stop: 1;
uint32_t timer0_tez: 1;
uint32_t timer1_tez: 1;
uint32_t timer2_tez: 1;
uint32_t timer0_tep: 1;
uint32_t timer1_tep: 1;
uint32_t timer2_tep: 1;
uint32_t fault0: 1;
uint32_t fault1: 1;
uint32_t fault2: 1;
uint32_t fault0_clr: 1;
uint32_t fault1_clr: 1;
uint32_t fault2_clr: 1;
uint32_t cmpr0_tea: 1;
uint32_t cmpr1_tea: 1;
uint32_t cmpr2_tea: 1;
uint32_t cmpr0_teb: 1;
uint32_t cmpr1_teb: 1;
uint32_t cmpr2_teb: 1;
uint32_t tz0_cbc: 1;
uint32_t tz1_cbc: 1;
uint32_t tz2_cbc: 1;
uint32_t tz0_ost: 1;
uint32_t tz1_ost: 1;
uint32_t tz2_ost: 1;
uint32_t cap0: 1;
uint32_t cap1: 1;
uint32_t cap2: 1;
uint32_t reserved30: 2;
uint32_t timer0_stop : 1;
uint32_t timer1_stop : 1;
uint32_t timer2_stop : 1;
uint32_t timer0_tez : 1;
uint32_t timer1_tez : 1;
uint32_t timer2_tez : 1;
uint32_t timer0_tep : 1;
uint32_t timer1_tep : 1;
uint32_t timer2_tep : 1;
uint32_t fault0 : 1;
uint32_t fault1 : 1;
uint32_t fault2 : 1;
uint32_t fault0_clr : 1;
uint32_t fault1_clr : 1;
uint32_t fault2_clr : 1;
uint32_t cmpr0_tea : 1;
uint32_t cmpr1_tea : 1;
uint32_t cmpr2_tea : 1;
uint32_t cmpr0_teb : 1;
uint32_t cmpr1_teb : 1;
uint32_t cmpr2_teb : 1;
uint32_t tz0_cbc : 1;
uint32_t tz1_cbc : 1;
uint32_t tz2_cbc : 1;
uint32_t tz0_ost : 1;
uint32_t tz1_ost : 1;
uint32_t tz2_ost : 1;
uint32_t cap0 : 1;
uint32_t cap1 : 1;
uint32_t cap2 : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t timer0_stop: 1;
uint32_t timer1_stop: 1;
uint32_t timer2_stop: 1;
uint32_t timer0_tez: 1;
uint32_t timer1_tez: 1;
uint32_t timer2_tez: 1;
uint32_t timer0_tep: 1;
uint32_t timer1_tep: 1;
uint32_t timer2_tep: 1;
uint32_t fault0: 1;
uint32_t fault1: 1;
uint32_t fault2: 1;
uint32_t fault0_clr: 1;
uint32_t fault1_clr: 1;
uint32_t fault2_clr: 1;
uint32_t cmpr0_tea: 1;
uint32_t cmpr1_tea: 1;
uint32_t cmpr2_tea: 1;
uint32_t cmpr0_teb: 1;
uint32_t cmpr1_teb: 1;
uint32_t cmpr2_teb: 1;
uint32_t tz0_cbc: 1;
uint32_t tz1_cbc: 1;
uint32_t tz2_cbc: 1;
uint32_t tz0_ost: 1;
uint32_t tz1_ost: 1;
uint32_t tz2_ost: 1;
uint32_t cap0: 1;
uint32_t cap1: 1;
uint32_t cap2: 1;
uint32_t reserved30: 2;
uint32_t timer0_stop : 1;
uint32_t timer1_stop : 1;
uint32_t timer2_stop : 1;
uint32_t timer0_tez : 1;
uint32_t timer1_tez : 1;
uint32_t timer2_tez : 1;
uint32_t timer0_tep : 1;
uint32_t timer1_tep : 1;
uint32_t timer2_tep : 1;
uint32_t fault0 : 1;
uint32_t fault1 : 1;
uint32_t fault2 : 1;
uint32_t fault0_clr : 1;
uint32_t fault1_clr : 1;
uint32_t fault2_clr : 1;
uint32_t cmpr0_tea : 1;
uint32_t cmpr1_tea : 1;
uint32_t cmpr2_tea : 1;
uint32_t cmpr0_teb : 1;
uint32_t cmpr1_teb : 1;
uint32_t cmpr2_teb : 1;
uint32_t tz0_cbc : 1;
uint32_t tz1_cbc : 1;
uint32_t tz2_cbc : 1;
uint32_t tz0_ost : 1;
uint32_t tz1_ost : 1;
uint32_t tz2_ost : 1;
uint32_t cap0 : 1;
uint32_t cap1 : 1;
uint32_t cap2 : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t timer0_stop: 1;
uint32_t timer1_stop: 1;
uint32_t timer2_stop: 1;
uint32_t timer0_tez: 1;
uint32_t timer1_tez: 1;
uint32_t timer2_tez: 1;
uint32_t timer0_tep: 1;
uint32_t timer1_tep: 1;
uint32_t timer2_tep: 1;
uint32_t fault0: 1;
uint32_t fault1: 1;
uint32_t fault2: 1;
uint32_t fault0_clr: 1;
uint32_t fault1_clr: 1;
uint32_t fault2_clr: 1;
uint32_t cmpr0_tea: 1;
uint32_t cmpr1_tea: 1;
uint32_t cmpr2_tea: 1;
uint32_t cmpr0_teb: 1;
uint32_t cmpr1_teb: 1;
uint32_t cmpr2_teb: 1;
uint32_t tz0_cbc: 1;
uint32_t tz1_cbc: 1;
uint32_t tz2_cbc: 1;
uint32_t tz0_ost: 1;
uint32_t tz1_ost: 1;
uint32_t tz2_ost: 1;
uint32_t cap0: 1;
uint32_t cap1: 1;
uint32_t cap2: 1;
uint32_t reserved30: 2;
uint32_t timer0_stop : 1;
uint32_t timer1_stop : 1;
uint32_t timer2_stop : 1;
uint32_t timer0_tez : 1;
uint32_t timer1_tez : 1;
uint32_t timer2_tez : 1;
uint32_t timer0_tep : 1;
uint32_t timer1_tep : 1;
uint32_t timer2_tep : 1;
uint32_t fault0 : 1;
uint32_t fault1 : 1;
uint32_t fault2 : 1;
uint32_t fault0_clr : 1;
uint32_t fault1_clr : 1;
uint32_t fault2_clr : 1;
uint32_t cmpr0_tea : 1;
uint32_t cmpr1_tea : 1;
uint32_t cmpr2_tea : 1;
uint32_t cmpr0_teb : 1;
uint32_t cmpr1_teb : 1;
uint32_t cmpr2_teb : 1;
uint32_t tz0_cbc : 1;
uint32_t tz1_cbc : 1;
uint32_t tz2_cbc : 1;
uint32_t tz0_ost : 1;
uint32_t tz1_ost : 1;
uint32_t tz2_ost : 1;
uint32_t cap0 : 1;
uint32_t cap1 : 1;
uint32_t cap2 : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t timer0_stop: 1;
uint32_t timer1_stop: 1;
uint32_t timer2_stop: 1;
uint32_t timer0_tez: 1;
uint32_t timer1_tez: 1;
uint32_t timer2_tez: 1;
uint32_t timer0_tep: 1;
uint32_t timer1_tep: 1;
uint32_t timer2_tep: 1;
uint32_t fault0: 1;
uint32_t fault1: 1;
uint32_t fault2: 1;
uint32_t fault0_clr: 1;
uint32_t fault1_clr: 1;
uint32_t fault2_clr: 1;
uint32_t cmpr0_tea: 1;
uint32_t cmpr1_tea: 1;
uint32_t cmpr2_tea: 1;
uint32_t cmpr0_teb: 1;
uint32_t cmpr1_teb: 1;
uint32_t cmpr2_teb: 1;
uint32_t tz0_cbc: 1;
uint32_t tz1_cbc: 1;
uint32_t tz2_cbc: 1;
uint32_t tz0_ost: 1;
uint32_t tz1_ost: 1;
uint32_t tz2_ost: 1;
uint32_t cap0: 1;
uint32_t cap1: 1;
uint32_t cap2: 1;
uint32_t reserved30: 2;
uint32_t timer0_stop : 1;
uint32_t timer1_stop : 1;
uint32_t timer2_stop : 1;
uint32_t timer0_tez : 1;
uint32_t timer1_tez : 1;
uint32_t timer2_tez : 1;
uint32_t timer0_tep : 1;
uint32_t timer1_tep : 1;
uint32_t timer2_tep : 1;
uint32_t fault0 : 1;
uint32_t fault1 : 1;
uint32_t fault2 : 1;
uint32_t fault0_clr : 1;
uint32_t fault1_clr : 1;
uint32_t fault2_clr : 1;
uint32_t cmpr0_tea : 1;
uint32_t cmpr1_tea : 1;
uint32_t cmpr2_tea : 1;
uint32_t cmpr0_teb : 1;
uint32_t cmpr1_teb : 1;
uint32_t cmpr2_teb : 1;
uint32_t tz0_cbc : 1;
uint32_t tz1_cbc : 1;
uint32_t tz2_cbc : 1;
uint32_t tz0_ost : 1;
uint32_t tz1_ost : 1;
uint32_t tz2_ost : 1;
uint32_t cap0 : 1;
uint32_t cap1 : 1;
uint32_t cap2 : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
uint32_t en : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} reg_clk;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus
}
#endif

26
components/soc/esp32s3/include/soc/pcnt_caps.h Normal file
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@ -0,0 +1,26 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4)
#ifdef __cplusplus
}
#endif

1364
components/soc/esp32s3/include/soc/pcnt_reg.h
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File diff suppressed because it is too large Load Diff

122
components/soc/esp32s3/include/soc/pcnt_struct.h
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@ -23,111 +23,111 @@ typedef volatile struct {
struct {
union {
struct {
uint32_t filter_thres: 10;
uint32_t filter_en: 1;
uint32_t thr_zero_en: 1;
uint32_t thr_h_lim_en: 1;
uint32_t thr_l_lim_en: 1;
uint32_t thr_thres0_en: 1;
uint32_t thr_thres1_en: 1;
uint32_t ch0_neg_mode: 2;
uint32_t ch0_pos_mode: 2;
uint32_t ch0_hctrl_mode: 2;
uint32_t ch0_lctrl_mode: 2;
uint32_t ch1_neg_mode: 2;
uint32_t ch1_pos_mode: 2;
uint32_t ch1_hctrl_mode: 2;
uint32_t ch1_lctrl_mode: 2;
uint32_t filter_thres : 10;
uint32_t filter_en : 1;
uint32_t thr_zero_en : 1;
uint32_t thr_h_lim_en : 1;
uint32_t thr_l_lim_en : 1;
uint32_t thr_thres0_en : 1;
uint32_t thr_thres1_en : 1;
uint32_t ch0_neg_mode : 2;
uint32_t ch0_pos_mode : 2;
uint32_t ch0_hctrl_mode : 2;
uint32_t ch0_lctrl_mode : 2;
uint32_t ch1_neg_mode : 2;
uint32_t ch1_pos_mode : 2;
uint32_t ch1_hctrl_mode : 2;
uint32_t ch1_lctrl_mode : 2;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0: 16;
uint32_t cnt_thres1: 16;
uint32_t cnt_thres0 : 16;
uint32_t cnt_thres1 : 16;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim: 16;
uint32_t cnt_l_lim: 16;
uint32_t cnt_h_lim : 16;
uint32_t cnt_l_lim : 16;
};
uint32_t val;
} conf2;
} conf_unit[4];
union {
struct {
uint32_t cnt_val: 16;
uint32_t reserved16: 16;
uint32_t cnt_val : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} cnt_unit[4];
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
uint32_t cnt_thr_event_u0 : 1;
uint32_t cnt_thr_event_u1 : 1;
uint32_t cnt_thr_event_u2 : 1;
uint32_t cnt_thr_event_u3 : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
uint32_t cnt_thr_event_u0 : 1;
uint32_t cnt_thr_event_u1 : 1;
uint32_t cnt_thr_event_u2 : 1;
uint32_t cnt_thr_event_u3 : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
uint32_t cnt_thr_event_u0 : 1;
uint32_t cnt_thr_event_u1 : 1;
uint32_t cnt_thr_event_u2 : 1;
uint32_t cnt_thr_event_u3 : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
uint32_t cnt_thr_event_u0 : 1;
uint32_t cnt_thr_event_u1 : 1;
uint32_t cnt_thr_event_u2 : 1;
uint32_t cnt_thr_event_u3 : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t cnt_mode: 2;
uint32_t thres1_lat: 1;
uint32_t thres0_lat: 1;
uint32_t l_lim_lat: 1;
uint32_t h_lim_lat: 1;
uint32_t zero_lat: 1;
uint32_t reserved7: 25;
uint32_t zero_mode : 2;
uint32_t thres1_lat : 1;
uint32_t thres0_lat : 1;
uint32_t l_lim_lat : 1;
uint32_t h_lim_lat : 1;
uint32_t zero_lat : 1;
uint32_t reserved7 : 25;
};
uint32_t val;
} status_unit[4];
union {
struct {
uint32_t cnt_rst_u0: 1;
uint32_t cnt_pause_u0: 1;
uint32_t cnt_rst_u1: 1;
uint32_t cnt_pause_u1: 1;
uint32_t cnt_rst_u2: 1;
uint32_t cnt_pause_u2: 1;
uint32_t cnt_rst_u3: 1;
uint32_t cnt_pause_u3: 1;
uint32_t reserved8: 8;
uint32_t clk_en: 1;
uint32_t reserved17: 15;
uint32_t cnt_rst_u0 : 1;
uint32_t cnt_pause_u0 : 1;
uint32_t cnt_rst_u1 : 1;
uint32_t cnt_pause_u1 : 1;
uint32_t cnt_rst_u2 : 1;
uint32_t cnt_pause_u2 : 1;
uint32_t cnt_rst_u3 : 1;
uint32_t cnt_pause_u3 : 1;
uint32_t reserved8 : 8;
uint32_t clk_en : 1;
uint32_t reserved17 : 15;
};
uint32_t val;
} ctrl;
@ -169,11 +169,9 @@ typedef volatile struct {
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
uint32_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifdef __cplusplus
}
#endif

198
components/soc/esp32s3/include/soc/peri_backup_reg.h Normal file
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@ -0,0 +1,198 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PERI_BACKUP_REG_H_
#define _SOC_PERI_BACKUP_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define PERI_BACKUP_CONFIG_REG (DR_REG_PERI_BACKUP_BASE + 0x0)
/* PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_ENA (BIT(31))
#define PERI_BACKUP_ENA_M (BIT(31))
#define PERI_BACKUP_ENA_V 0x1
#define PERI_BACKUP_ENA_S 31
/* PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_TO_MEM (BIT(30))
#define PERI_BACKUP_TO_MEM_M (BIT(30))
#define PERI_BACKUP_TO_MEM_V 0x1
#define PERI_BACKUP_TO_MEM_S 30
/* PERI_BACKUP_START : WT ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_START (BIT(29))
#define PERI_BACKUP_START_M (BIT(29))
#define PERI_BACKUP_START_V 0x1
#define PERI_BACKUP_START_S 29
/* PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
/*description: .*/
#define PERI_BACKUP_SIZE 0x000003FF
#define PERI_BACKUP_SIZE_M ((PERI_BACKUP_SIZE_V)<<(PERI_BACKUP_SIZE_S))
#define PERI_BACKUP_SIZE_V 0x3FF
#define PERI_BACKUP_SIZE_S 19
/* PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: .*/
#define PERI_BACKUP_TOUT_THRES 0x000003FF
#define PERI_BACKUP_TOUT_THRES_M ((PERI_BACKUP_TOUT_THRES_V)<<(PERI_BACKUP_TOUT_THRES_S))
#define PERI_BACKUP_TOUT_THRES_V 0x3FF
#define PERI_BACKUP_TOUT_THRES_S 9
/* PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
/*description: .*/
#define PERI_BACKUP_BURST_LIMIT 0x0000001F
#define PERI_BACKUP_BURST_LIMIT_M ((PERI_BACKUP_BURST_LIMIT_V)<<(PERI_BACKUP_BURST_LIMIT_S))
#define PERI_BACKUP_BURST_LIMIT_V 0x1F
#define PERI_BACKUP_BURST_LIMIT_S 4
/* PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
#define PERI_BACKUP_ADDR_MAP_MODE_V 0x1
#define PERI_BACKUP_ADDR_MAP_MODE_S 3
/* PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
/*description: .*/
#define PERI_BACKUP_FLOW_ERR 0x00000007
#define PERI_BACKUP_FLOW_ERR_M ((PERI_BACKUP_FLOW_ERR_V)<<(PERI_BACKUP_FLOW_ERR_S))
#define PERI_BACKUP_FLOW_ERR_V 0x7
#define PERI_BACKUP_FLOW_ERR_S 0
#define PERI_BACKUP_APB_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x4)
/* PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define PERI_BACKUP_APB_START_ADDR_M ((PERI_BACKUP_APB_START_ADDR_V)<<(PERI_BACKUP_APB_START_ADDR_S))
#define PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define PERI_BACKUP_APB_START_ADDR_S 0
#define PERI_BACKUP_MEM_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x8)
/* PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_M ((PERI_BACKUP_MEM_START_ADDR_V)<<(PERI_BACKUP_MEM_START_ADDR_S))
#define PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_S 0
#define PERI_BACKUP_REG_MAP0_REG (DR_REG_PERI_BACKUP_BASE + 0xC)
/* PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP0 0xFFFFFFFF
#define PERI_BACKUP_MAP0_M ((PERI_BACKUP_MAP0_V)<<(PERI_BACKUP_MAP0_S))
#define PERI_BACKUP_MAP0_V 0xFFFFFFFF
#define PERI_BACKUP_MAP0_S 0
#define PERI_BACKUP_REG_MAP1_REG (DR_REG_PERI_BACKUP_BASE + 0x10)
/* PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP1 0xFFFFFFFF
#define PERI_BACKUP_MAP1_M ((PERI_BACKUP_MAP1_V)<<(PERI_BACKUP_MAP1_S))
#define PERI_BACKUP_MAP1_V 0xFFFFFFFF
#define PERI_BACKUP_MAP1_S 0
#define PERI_BACKUP_REG_MAP2_REG (DR_REG_PERI_BACKUP_BASE + 0x14)
/* PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP2 0xFFFFFFFF
#define PERI_BACKUP_MAP2_M ((PERI_BACKUP_MAP2_V)<<(PERI_BACKUP_MAP2_S))
#define PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define PERI_BACKUP_MAP2_S 0
#define PERI_BACKUP_REG_MAP3_REG (DR_REG_PERI_BACKUP_BASE + 0x18)
/* PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP3 0xFFFFFFFF
#define PERI_BACKUP_MAP3_M ((PERI_BACKUP_MAP3_V)<<(PERI_BACKUP_MAP3_S))
#define PERI_BACKUP_MAP3_V 0xFFFFFFFF
#define PERI_BACKUP_MAP3_S 0
#define PERI_BACKUP_INT_RAW_REG (DR_REG_PERI_BACKUP_BASE + 0x1C)
/* PERI_BACKUP_ERR_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define PERI_BACKUP_ERR_INT_RAW_V 0x1
#define PERI_BACKUP_ERR_INT_RAW_S 1
/* PERI_BACKUP_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
#define PERI_BACKUP_DONE_INT_RAW_V 0x1
#define PERI_BACKUP_DONE_INT_RAW_S 0
#define PERI_BACKUP_INT_ST_REG (DR_REG_PERI_BACKUP_BASE + 0x20)
/* PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_ST (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_V 0x1
#define PERI_BACKUP_ERR_INT_ST_S 1
/* PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_ST (BIT(0))
#define PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define PERI_BACKUP_DONE_INT_ST_V 0x1
#define PERI_BACKUP_DONE_INT_ST_S 0
#define PERI_BACKUP_INT_ENA_REG (DR_REG_PERI_BACKUP_BASE + 0x24)
/* PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
#define PERI_BACKUP_ERR_INT_ENA_V 0x1
#define PERI_BACKUP_ERR_INT_ENA_S 1
/* PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
#define PERI_BACKUP_DONE_INT_ENA_V 0x1
#define PERI_BACKUP_DONE_INT_ENA_S 0
#define PERI_BACKUP_INT_CLR_REG (DR_REG_PERI_BACKUP_BASE + 0x28)
/* PERI_BACKUP_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_V 0x1
#define PERI_BACKUP_ERR_INT_CLR_S 1
/* PERI_BACKUP_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
#define PERI_BACKUP_DONE_INT_CLR_V 0x1
#define PERI_BACKUP_DONE_INT_CLR_S 0
#define PERI_BACKUP_DATE_REG (DR_REG_PERI_BACKUP_BASE + 0xFC)
/* PERI_BACKUP_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating.*/
#define PERI_BACKUP_CLK_EN (BIT(31))
#define PERI_BACKUP_CLK_EN_M (BIT(31))
#define PERI_BACKUP_CLK_EN_V 0x1
#define PERI_BACKUP_CLK_EN_S 31
/* PERI_BACKUP_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
/*description: .*/
#define PERI_BACKUP_DATE 0x0FFFFFFF
#define PERI_BACKUP_DATE_M ((PERI_BACKUP_DATE_V)<<(PERI_BACKUP_DATE_S))
#define PERI_BACKUP_DATE_V 0xFFFFFFF
#define PERI_BACKUP_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_PERI_BACKUP_REG_H_ */

11
components/soc/esp32s3/include/soc/periph_defs.h
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@ -33,6 +33,8 @@ typedef enum {
PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE,
@ -130,6 +132,11 @@ typedef enum {
ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/
ETS_DMA_CH3_INTR_SOURCE, /**< interrupt of general DMA channel 3, LEVEL*/
ETS_DMA_CH4_INTR_SOURCE, /**< interrupt of general DMA channel 4, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH3_INTR_SOURCE,
ETS_DMA_OUT_CH4_INTR_SOURCE,
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
@ -147,8 +154,12 @@ typedef enum {
ETS_CORE1_DRAM0_PMS_INTR_SOURCE,
ETS_CORE1_PIF_PMS_INTR_SOURCE,
ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE,
ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE,
ETS_CACHE_CORE0_ACS_INTR_SOURCE,
ETS_CACHE_CORE1_ACS_INTR_SOURCE,
ETS_USB_DEVICE_INTR_SOURCE,
ETS_PREI_BACKUP_INTR_SOURCE,
ETS_DMA_EXTMEM_REJECT_SOURCE,
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t;

30
components/soc/esp32s3/include/soc/rmt_caps.h Normal file
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@ -0,0 +1,30 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#ifdef __cplusplus
}
#endif

3534
components/soc/esp32s3/include/soc/rmt_reg.h
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File diff suppressed because it is too large Load Diff

430
components/soc/esp32s3/include/soc/rmt_struct.h
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@ -11,305 +11,315 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t data_ch[8];
union {
struct {
uint32_t tx_start : 1;
uint32_t mem_rd_rst : 1;
uint32_t apb_mem_rst : 1;
uint32_t tx_conti_mode : 1;
uint32_t mem_tx_wrap_en : 1;
uint32_t idle_out_lv : 1;
uint32_t idle_out_en : 1;
uint32_t tx_stop : 1;
uint32_t div_cnt : 8;
uint32_t mem_size : 4;
uint32_t carrier_eff_en : 1;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved25 : 7;
uint32_t tx_start : 1;
uint32_t mem_rd_rst : 1;
uint32_t mem_rst : 1;
uint32_t tx_conti_mode : 1;
uint32_t mem_tx_wrap_en : 1;
uint32_t idle_out_lv : 1;
uint32_t idle_out_en : 1;
uint32_t tx_stop : 1;
uint32_t div_cnt : 8;
uint32_t mem_size : 4;
uint32_t carrier_eff_en : 1;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved25 : 7;
};
uint32_t val;
} tx_conf[4];
struct {
union {
struct {
uint32_t div_cnt : 8;
uint32_t idle_thres : 15;
uint32_t reserved23 : 1;
uint32_t mem_size : 4;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t reserved30 : 2;
uint32_t div_cnt : 8;
uint32_t idle_thres : 15;
uint32_t reserved23 : 1;
uint32_t mem_size : 4;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rx_en : 1;
uint32_t mem_wr_rst : 1;
uint32_t apb_mem_rst : 1;
uint32_t mem_owner : 1;
uint32_t rx_filter_en : 1;
uint32_t rx_filter_thres : 8;
uint32_t mem_rx_wrap_en : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved16 : 16;
uint32_t rx_en : 1;
uint32_t mem_wr_rst : 1;
uint32_t mem_rst : 1;
uint32_t mem_owner : 1;
uint32_t rx_filter_en : 1;
uint32_t rx_filter_thres : 8;
uint32_t mem_rx_wrap_en : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved16 : 16;
};
uint32_t val;
} conf1;
} rx_conf[4];
union {
struct {
uint32_t mem_raddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t apb_mem_waddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_empty : 1;
uint32_t apb_mem_wr_err : 1;
uint32_t reserved27 : 5;
uint32_t mem_raddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t mem_waddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_empty : 1;
uint32_t mem_wr_err : 1;
uint32_t reserved27 : 5;
};
uint32_t val;
} tx_status[4];
union {
struct {
uint32_t mem_waddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t apb_mem_raddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_owner_err : 1;
uint32_t mem_full : 1;
uint32_t apb_mem_rd_err : 1;
uint32_t reserved27 : 4;
uint32_t mem_waddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t mem_raddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_owner_err : 1;
uint32_t mem_full : 1;
uint32_t mem_rd_err : 1;
uint32_t reserved28 : 4;
};
uint32_t val;
} rx_status[4];
union {
struct {
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t low : 16;
uint32_t high : 16;
uint32_t low : 16;
uint32_t high : 16;
};
uint32_t val;
} tx_carrier[4];
union {
struct {
uint32_t low_thres : 16;
uint32_t high_thres : 16;
uint32_t low_thres : 16;
uint32_t high_thres : 16;
};
uint32_t val;
} rx_carrier[4];
union {
struct {
uint32_t limit : 9;
uint32_t tx_loop_num : 10;
uint32_t tx_loop_cnt_en : 1;
uint32_t loop_count_reset : 1;
uint32_t reserved21 : 11;
uint32_t limit : 9;
uint32_t tx_loop_num : 10;
uint32_t tx_loop_cnt_en : 1;
uint32_t loop_count_reset : 1;
uint32_t loop_stop_en : 1;
uint32_t reserved22 : 10;
};
uint32_t val;
} tx_lim[4];
union {
struct {
uint32_t rx_lim : 9;
uint32_t reserved9 : 23;
uint32_t rx_lim : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} rx_lim[4];
union {
struct {
uint32_t fifo_mask : 1;
uint32_t mem_clk_force_on : 1;
uint32_t mem_force_pd : 1;
uint32_t mem_force_pu : 1;
uint32_t sclk_div_num : 8;
uint32_t sclk_div_a : 6;
uint32_t sclk_div_b : 6;
uint32_t sclk_sel : 2;
uint32_t sclk_active : 1;
uint32_t reserved27 : 4;
uint32_t clk_en : 1;
uint32_t fifo_mask : 1;
uint32_t mem_clk_force_on : 1;
uint32_t mem_force_pd : 1;
uint32_t mem_force_pu : 1;
uint32_t sclk_div_num : 8;
uint32_t sclk_div_a : 6;
uint32_t sclk_div_b : 6;
uint32_t sclk_sel : 2;
uint32_t sclk_active : 1;
uint32_t reserved27 : 4;
uint32_t clk_en : 1;
};
uint32_t val;
} sys_conf;
union {
struct {
uint32_t ch0 : 1;
uint32_t ch1 : 1;
uint32_t ch2 : 1;
uint32_t ch3 : 1;
uint32_t en : 1;
uint32_t reserved5 : 27;
uint32_t ch0 : 1;
uint32_t ch1 : 1;
uint32_t ch2 : 1;
uint32_t ch3 : 1;
uint32_t en : 1;
uint32_t reserved5 : 27;
};
uint32_t val;
} tx_sim;
union {
struct {
uint32_t ref_cnt_rst_ch0 : 1;
uint32_t ref_cnt_rst_ch1 : 1;
uint32_t ref_cnt_rst_ch2 : 1;
uint32_t ref_cnt_rst_ch3 : 1;
uint32_t ref_cnt_rst_ch4 : 1;
uint32_t ref_cnt_rst_ch5 : 1;
uint32_t ref_cnt_rst_ch6 : 1;
uint32_t ref_cnt_rst_ch7 : 1;
uint32_t reserved8 : 24;
uint32_t ch0 : 1;
uint32_t ch1 : 1;
uint32_t ch2 : 1;
uint32_t ch3 : 1;
uint32_t ch4 : 1;
uint32_t ch5 : 1;
uint32_t ch6 : 1;
uint32_t ch7 : 1;
uint32_t reserved8 : 24;
};
uint32_t val;
} ref_cnt_rst;
union {
struct {
uint32_t date : 28;
uint32_t reserved28 : 4;
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
@ -342,3 +352,7 @@ extern rmt_mem_t RMTMEM;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RMT_STRUCT_H_ */

9
components/soc/esp32s3/include/soc/rtc.h
View File

@ -249,10 +249,16 @@ typedef struct {
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
uint16_t bt_powerup_cycles : 7;
uint16_t bt_wait_cycles : 9;
uint16_t rtc_powerup_cycles : 7;
uint16_t rtc_wait_cycles : 9;
uint16_t cpu_top_powerup_cycles : 7;
uint16_t cpu_top_wait_cycles : 9;
uint16_t dg_wrap_powerup_cycles : 7;
uint16_t dg_wrap_wait_cycles : 9;
uint16_t dg_peri_powerup_cycles : 7;
uint16_t dg_peri_wait_cycles : 9;
uint16_t rtc_mem_powerup_cycles : 7;
uint16_t rtc_mem_wait_cycles : 9;
} rtc_init_config_t;
@ -633,6 +639,9 @@ typedef struct {
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode

4607
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
View File

File diff suppressed because it is too large Load Diff

183
components/soc/esp32s3/include/soc/rtc_cntl_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
@ -71,7 +69,7 @@ typedef volatile struct {
uint32_t time_low0; /*RTC timer low 32 bits*/
union {
struct {
uint32_t rtc_timer_value0_high: 16; /*RTC timer high 16 bits*/
uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -110,10 +108,10 @@ typedef volatile struct {
} timer2;
union {
struct {
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t rom_ram_wait_timer: 9;
uint32_t rom_ram_powerup_timer: 7;
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t bt_wait_timer: 9;
uint32_t bt_powerup_timer: 7;
};
uint32_t val;
} timer3;
@ -128,18 +126,18 @@ typedef volatile struct {
} timer4;
union {
struct {
uint32_t reserved0: 8;
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
uint32_t rtcmem_wait_timer: 9;
uint32_t rtcmem_powerup_timer: 7;
uint32_t reserved0: 8;
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
uint32_t reserved16: 16;
};
uint32_t val;
} timer5;
union {
struct {
uint32_t reserved0: 16;
uint32_t dg_dcdc_wait_timer: 9;
uint32_t dg_dcdc_powerup_timer: 7;
uint32_t cpu_top_wait_timer: 9;
uint32_t cpu_top_powerup_timer: 7;
uint32_t dg_peri_wait_timer: 9;
uint32_t dg_peri_powerup_timer: 7;
};
uint32_t val;
} timer6;
@ -188,7 +186,7 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 15;
uint32_t rtc_wakeup_ena: 17; /*wakeup enable bitmap*/
uint32_t rtc_wakeup_ena:17; /*wakeup enable bitmap*/
};
uint32_t val;
} wakeup_state;
@ -337,7 +335,7 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 12;
uint32_t rtc_sleep_reject_ena: 18; /*sleep reject enable*/
uint32_t rtc_sleep_reject_ena:18; /*sleep reject enable*/
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
};
@ -354,7 +352,7 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 22;
uint32_t sdio_act_dnum: 10;
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} sdio_act_conf;
@ -425,7 +423,8 @@ typedef volatile struct {
uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/
uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/
uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/
uint32_t reserved26: 6;
uint32_t dbg_atten_wakeup: 4;
uint32_t reserved30: 2;
};
uint32_t val;
} bias_conf;
@ -457,12 +456,7 @@ typedef volatile struct {
uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/
uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/
uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/
uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/
uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/
uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/
uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/
uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/
uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/
uint32_t reserved12: 6; /*enable power down RTC memory in sleep*/
uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/
uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/
uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/
@ -473,67 +467,53 @@ typedef volatile struct {
} rtc_pwc;
union {
struct {
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
uint32_t rom0_force_pd: 1; /*ROM force power down*/
uint32_t rom0_force_pu: 1; /*ROM force power up*/
uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/
uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/
uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/
uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/
uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/
uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/
uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/
uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/
uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/
uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/
uint32_t wifi_force_pd: 1; /*wifi force power down*/
uint32_t wifi_force_pu: 1; /*wifi force power up*/
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
uint32_t dg_dcdc_force_pd: 1; /*digital dcdc force power down*/
uint32_t dg_dcdc_force_pu: 1; /*digital dcdc force power up*/
uint32_t dg_dcdc_pd_en: 1; /*enable power down digital dcdc in sleep*/
uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/
uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/
uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/
uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/
uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/
uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
uint32_t dg_wrap_pd_en: 1;
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
uint32_t reserved5: 6; /*internal SRAM 1 force power up*/
uint32_t bt_force_pd: 1; /*internal SRAM 2 force power down*/
uint32_t bt_force_pu: 1; /*internal SRAM 2 force power up*/
uint32_t dg_peri_force_pd: 1; /*internal SRAM 3 force power down*/
uint32_t dg_peri_force_pu: 1; /*internal SRAM 3 force power up*/
uint32_t reserved15: 2; /*internal SRAM 4 force power up*/
uint32_t wifi_force_pd: 1; /*wifi force power down*/
uint32_t wifi_force_pu: 1; /*wifi force power up*/
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
uint32_t cpu_top_force_pd: 1; /*digital dcdc force power down*/
uint32_t cpu_top_force_pu: 1; /*digital dcdc force power up*/
uint32_t reserved23: 4; /*enable power down internal SRAM 1 in sleep*/
uint32_t bt_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/
uint32_t dg_peri_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/
uint32_t cpu_top_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
uint32_t dg_wrap_pd_en: 1;
};
uint32_t val;
} dig_pwc;
union {
struct {
uint32_t reserved0: 7;
uint32_t dig_iso_force_off: 1;
uint32_t dig_iso_force_on: 1;
uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/
uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/
uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/
uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
uint32_t rom0_force_iso: 1; /*ROM force ISO*/
uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/
uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/
uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/
uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/
uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/
uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/
uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/
uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/
uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/
uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/
uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
uint32_t dg_wrap_force_noiso: 1;
uint32_t reserved0: 7;
uint32_t dig_iso_force_off: 1;
uint32_t dig_iso_force_on: 1;
uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/
uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/
uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/
uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
uint32_t reserved16: 6; /*internal SRAM 1 force no ISO*/
uint32_t bt_force_iso: 1; /*internal SRAM 2 force ISO*/
uint32_t bt_force_noiso: 1; /*internal SRAM 2 force no ISO*/
uint32_t dg_peri_force_iso: 1; /*internal SRAM 3 force ISO*/
uint32_t dg_peri_force_noiso: 1; /*internal SRAM 3 force no ISO*/
uint32_t cpu_top_force_iso: 1; /*internal SRAM 4 force ISO*/
uint32_t cpu_top_force_noiso: 1; /*internal SRAM 4 force no ISO*/
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
uint32_t dg_wrap_force_noiso: 1;
};
uint32_t val;
} dig_iso;
@ -573,7 +553,7 @@ typedef volatile struct {
uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/
uint32_t reserved2: 15;
uint32_t swd_bypass_rst: 1;
uint32_t swd_signal_width: 10; /*adjust signal width send to swd*/
uint32_t swd_signal_width:10; /*adjust signal width send to swd*/
uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/
uint32_t swd_feed: 1; /*Sw feed swd*/
uint32_t swd_disable: 1; /*disabel SWD*/
@ -692,7 +672,7 @@ typedef volatile struct {
uint32_t time_low1; /*RTC timer low 32 bits*/
union {
struct {
uint32_t rtc_timer_value1_high: 16; /*RTC timer high 16 bits*/
uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -701,7 +681,7 @@ typedef volatile struct {
union {
struct {
uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/
uint32_t xtal32k_restart_wait: 16; /*cycles to wait to repower on xtal 32k*/
uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/
uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/
uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/
};
@ -749,7 +729,7 @@ typedef volatile struct {
} cocpu_ctrl;
union {
struct {
uint32_t touch_sleep_cycles: 16; /*sleep cycles for timer*/
uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/
uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/
};
uint32_t val;
@ -809,14 +789,14 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 7;
uint32_t touch_bypass_neg_thres: 1;
uint32_t touch_bypass_neg_noise_thres: 1;
uint32_t touch_bypass_noise_thres: 1;
uint32_t touch_smooth_lvl: 2;
uint32_t touch_jitter_step: 4; /*touch jitter step*/
uint32_t config1: 4;
uint32_t config2: 2;
uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/
uint32_t touch_neg_noise_thres: 2;
uint32_t touch_noise_thres: 2;
uint32_t config3: 2;
uint32_t touch_hysteresis: 2;
uint32_t touch_debounce: 3; /*debounce counter*/
uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
uint32_t touch_filter_en: 1; /*touch filter enable*/
@ -848,7 +828,7 @@ typedef volatile struct {
} usb_conf;
union {
struct {
uint32_t touch_timeout_num: 22;
uint32_t touch_timeout_num:22;
uint32_t touch_timeout_en: 1;
uint32_t reserved23: 9;
};
@ -856,7 +836,7 @@ typedef volatile struct {
} touch_timeout_ctrl;
union {
struct {
uint32_t reject_cause: 18; /*sleep reject cause*/
uint32_t reject_cause:18; /*sleep reject cause*/
uint32_t reserved18: 14;
};
uint32_t val;
@ -870,7 +850,7 @@ typedef volatile struct {
} option1;
union {
struct {
uint32_t wakeup_cause: 17; /*sleep wakeup cause*/
uint32_t wakeup_cause:17; /*sleep wakeup cause*/
uint32_t reserved17: 15;
};
uint32_t val;
@ -878,7 +858,7 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 8;
uint32_t ulp_cp_timer_slp_cycle: 24; /*sleep cycles for ULP-coprocessor timer*/
uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/
};
uint32_t val;
} ulp_cp_timer_1;
@ -938,9 +918,12 @@ typedef volatile struct {
} int_ena_w1tc;
union {
struct {
uint32_t reserved0: 26;
uint32_t retention_en: 1;
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
uint32_t reserved0: 18;
uint32_t retention_clk_sel: 1;
uint32_t retention_done_wait: 3;
uint32_t retention_clkoff_wait: 4;
uint32_t retention_en: 1;
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
};
uint32_t val;
} retention_ctrl;
@ -959,9 +942,9 @@ typedef volatile struct {
uint32_t val;
} date;
} rtc_cntl_dev_t;
extern rtc_cntl_dev_t RTCCNTL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RTC_CNTL_STRUCT_H_ */

1064
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
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176
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
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@ -22,161 +22,161 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
uint32_t reserved20: 12;
uint32_t period : 20; /*time period that scl = 0*/
uint32_t reserved20 : 12;
};
uint32_t val;
} scl_low;
union {
struct {
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
uint32_t ms_mode: 1; /*1=master 0=slave*/
uint32_t trans_start: 1; /*force start*/
uint32_t tx_lsb_first: 1; /*transit lsb first*/
uint32_t rx_lsb_first: 1; /*receive lsb first*/
uint32_t reserved6: 23;
uint32_t i2c_ctrl_clk_gate_en: 1;
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
uint32_t sda_force_out : 1; /*1=push pull, 0=open drain*/
uint32_t scl_force_out : 1; /*1=push pull, 0=open drain*/
uint32_t ms_mode : 1; /*1=master, 0=slave*/
uint32_t trans_start : 1; /*force start*/
uint32_t tx_lsb_first : 1; /*transit lsb first*/
uint32_t rx_lsb_first : 1; /*receive lsb first*/
uint32_t reserved6 : 23;
uint32_t i2c_ctrl_clk_gate_en : 1;
uint32_t i2c_reset : 1; /*rtc i2c sw reset*/
uint32_t i2cclk_en : 1; /*rtc i2c reg clk gating*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t ack_rec: 1; /*ack response*/
uint32_t slave_rw: 1; /*slave read or write*/
uint32_t arb_lost: 1; /*arbitration is lost*/
uint32_t bus_busy: 1; /*bus is busy*/
uint32_t slave_addressed: 1; /*slave reg sub address*/
uint32_t byte_trans: 1; /*One byte transit done*/
uint32_t op_cnt: 2; /*which operation is working*/
uint32_t reserved8: 8;
uint32_t shift: 8; /*shifter content*/
uint32_t scl_main_state_last: 3; /*i2c last main status*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*scl last status*/
uint32_t reserved31: 1;
uint32_t ack_rec : 1; /*ack response*/
uint32_t slave_rw : 1; /*slave read or write*/
uint32_t arb_lost : 1; /*arbitration is lost*/
uint32_t bus_busy : 1; /*bus is busy*/
uint32_t slave_addressed : 1; /*slave reg sub address*/
uint32_t byte_trans : 1; /*One byte transit done*/
uint32_t op_cnt : 2; /*which operation is working*/
uint32_t reserved8 : 8;
uint32_t shift : 8; /*shifter content*/
uint32_t scl_main_state_last : 3; /*i2c last main status*/
uint32_t reserved27 : 1;
uint32_t scl_state_last : 3; /*scl last status*/
uint32_t reserved31 : 1;
};
uint32_t val;
} status;
union {
struct {
uint32_t time_out: 20; /*time out threshold*/
uint32_t reserved20: 12;
uint32_t time_out : 20; /*time out threshold*/
uint32_t reserved20 : 12;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*slave address*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
uint32_t addr : 15; /*slave address*/
uint32_t reserved15 : 16;
uint32_t en_10bit : 1; /*i2c 10bit mode enable*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t period: 20; /*time period that scl = 1*/
uint32_t reserved20: 12;
uint32_t period : 20; /*time period that scl = 1*/
uint32_t reserved20 : 12;
};
uint32_t val;
} scl_high;
union {
struct {
uint32_t sda_duty_num: 20; /*time period for SDA to toggle after SCL goes low*/
uint32_t reserved20: 12;
uint32_t sda_duty_num : 20; /*time period for SDA to toggle after SCL goes low*/
uint32_t reserved20 : 12;
};
uint32_t val;
} sda_duty;
union {
struct {
uint32_t scl_start_period: 20; /*time period for SCL to toggle after I2C start is triggered*/
uint32_t reserved20: 12;
uint32_t scl_start_period : 20; /*time period for SCL to toggle after I2C start is triggered*/
uint32_t reserved20 : 12;
};
uint32_t val;
} scl_start_period;
union {
struct {
uint32_t scl_stop_period: 20; /*time period for SCL to stop after I2C end is triggered*/
uint32_t reserved20: 12;
uint32_t scl_stop_period : 20; /*time period for SCL to stop after I2C end is triggered*/
uint32_t reserved20 : 12;
};
uint32_t val;
} scl_stop_period;
union {
struct {
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
uint32_t time_out: 1; /*clear time out interrupt*/
uint32_t ack_err: 1; /*clear ack error interrupt*/
uint32_t rx_data: 1; /*clear receive data interrupt*/
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
uint32_t detect_start: 1; /*clear detect start interrupt*/
uint32_t reserved9: 23;
uint32_t slave_tran_comp : 1; /*clear slave transit complete interrupt*/
uint32_t arbitration_lost : 1; /*clear arbitration lost interrupt*/
uint32_t master_tran_comp : 1; /*clear master transit complete interrupt*/
uint32_t trans_complete : 1; /*clear transit complete interrupt*/
uint32_t time_out : 1; /*clear time out interrupt*/
uint32_t ack_err : 1; /*clear ack error interrupt*/
uint32_t rx_data : 1; /*clear receive data interrupt*/
uint32_t tx_data : 1; /*clear transit load data complete interrupt*/
uint32_t detect_start : 1; /*clear detect start interrupt*/
uint32_t reserved9 : 23;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
uint32_t time_out: 1; /*time out interrupt raw*/
uint32_t ack_err: 1; /*ack error interrupt raw*/
uint32_t rx_data: 1; /*receive data interrupt raw*/
uint32_t tx_data: 1; /*transit data interrupt raw*/
uint32_t detect_start: 1; /*detect start interrupt raw*/
uint32_t reserved9: 23;
uint32_t slave_tran_comp : 1; /*slave transit complete interrupt raw*/
uint32_t arbitration_lost : 1; /*arbitration lost interrupt raw*/
uint32_t master_tran_comp : 1; /*master transit complete interrupt raw*/
uint32_t trans_complete : 1; /*transit complete interrupt raw*/
uint32_t time_out : 1; /*time out interrupt raw*/
uint32_t ack_err : 1; /*ack error interrupt raw*/
uint32_t rx_data : 1; /*receive data interrupt raw*/
uint32_t tx_data : 1; /*transit data interrupt raw*/
uint32_t detect_start : 1; /*detect start interrupt raw*/
uint32_t reserved9 : 23;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
uint32_t trans_complete: 1; /*transit complete interrupt state*/
uint32_t time_out: 1; /*time out interrupt state*/
uint32_t ack_err: 1; /*ack error interrupt state*/
uint32_t rx_data: 1; /*receive data interrupt state*/
uint32_t tx_data: 1; /*transit data interrupt state*/
uint32_t detect_start: 1; /*detect start interrupt state*/
uint32_t reserved9: 23;
uint32_t slave_tran_comp : 1; /*slave transit complete interrupt state*/
uint32_t arbitration_lost : 1; /*arbitration lost interrupt state*/
uint32_t master_tran_comp : 1; /*master transit complete interrupt state*/
uint32_t trans_complete : 1; /*transit complete interrupt state*/
uint32_t time_out : 1; /*time out interrupt state*/
uint32_t ack_err : 1; /*ack error interrupt state*/
uint32_t rx_data : 1; /*receive data interrupt state*/
uint32_t tx_data : 1; /*transit data interrupt state*/
uint32_t detect_start : 1; /*detect start interrupt state*/
uint32_t reserved9 : 23;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
uint32_t time_out: 1; /*enable time out interrupt*/
uint32_t ack_err: 1; /*enable eack error interrupt*/
uint32_t rx_data: 1; /*enable receive data interrupt*/
uint32_t tx_data: 1; /*enable transit data interrupt*/
uint32_t detect_start: 1; /*enable detect start interrupt*/
uint32_t reserved9: 23;
uint32_t slave_tran_comp : 1; /*enable slave transit complete interrupt*/
uint32_t arbitration_lost : 1; /*enable arbitration lost interrupt*/
uint32_t master_tran_comp : 1; /*enable master transit complete interrupt*/
uint32_t trans_complete : 1; /*enable transit complete interrupt*/
uint32_t time_out : 1; /*enable time out interrupt*/
uint32_t ack_err : 1; /*enable eack error interrupt*/
uint32_t rx_data : 1; /*enable receive data interrupt*/
uint32_t tx_data : 1; /*enable transit data interrupt*/
uint32_t detect_start : 1; /*enable detect start interrupt*/
uint32_t reserved9 : 23;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t i2c_rdata: 8; /*data received*/
uint32_t slave_tx_data: 8; /*data sent by slave*/
uint32_t reserved16: 15;
uint32_t i2c_done: 1; /*i2c done*/
uint32_t i2c_rdata : 8; /*data received*/
uint32_t slave_tx_data : 8; /*data sent by slave*/
uint32_t reserved16 : 15;
uint32_t i2c_done : 1; /*i2c done*/
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t command0: 14; /*command0*/
uint32_t reserved14: 17;
uint32_t done: 1; /*command0_done*/
uint32_t command0 : 14; /* command0*/
uint32_t reserved14 : 17;
uint32_t done : 1; /* command0_done*/
};
uint32_t val;
} command[16];
@ -215,15 +215,13 @@ typedef volatile struct {
uint32_t reserved_f8;
union {
struct {
uint32_t i2c_date: 28;
uint32_t reserved28: 4;
uint32_t i2c_date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} rtc_i2c_dev_t;
extern rtc_i2c_dev_t RTC_I2C;
#ifdef __cplusplus
}
#endif

3684
components/soc/esp32s3/include/soc/rtc_io_reg.h
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285
components/soc/esp32s3/include/soc/rtc_io_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,262 +11,263 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RTC_IO_STRUCT_H_
#define _SOC_RTC_IO_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t reserved0: 10;
uint32_t data: 22; /*RTC GPIO 0 ~ 21 output data*/
uint32_t reserved0 : 10;
uint32_t data : 22; /*RTC GPIO 0 ~ 21 output data*/
};
uint32_t val;
} out;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
uint32_t reserved0 : 10;
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
};
uint32_t val;
} out_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
uint32_t reserved0 : 10;
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
};
uint32_t val;
} out_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t enable: 22; /*RTC GPIO 0 ~ 21 enable*/
uint32_t reserved0 : 10;
uint32_t enable : 22; /*RTC GPIO 0 ~ 21 enable*/
};
uint32_t val;
} enable;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
uint32_t reserved0 : 10;
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
};
uint32_t val;
} enable_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
uint32_t reserved0 : 10;
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
};
uint32_t val;
} enable_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t status: 22; /*RTC GPIO 0 ~ 21 interrupt status*/
uint32_t reserved0 : 10;
uint32_t status : 22; /*RTC GPIO 0 ~ 21 interrupt status*/
};
uint32_t val;
} status;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
uint32_t reserved0 : 10;
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
};
uint32_t val;
} status_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
uint32_t reserved0 : 10;
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
};
uint32_t val;
} status_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t in: 22; /*RTC GPIO input data*/
uint32_t reserved0 : 10;
uint32_t in : 22; /*RTC GPIO input data*/
};
uint32_t val;
} in_val;
union {
struct {
uint32_t reserved0: 2;
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11: 21;
uint32_t reserved0 : 2;
uint32_t pad_driver : 1; /*if set to 0: normal output, if set to 1: open drain*/
uint32_t reserved3 : 4;
uint32_t int_type : 3; /*if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger*/
uint32_t wakeup_enable : 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11 : 21;
};
uint32_t val;
} pin[22];
union {
struct {
uint32_t sel0: 5;
uint32_t sel1: 5;
uint32_t sel2: 5;
uint32_t sel3: 5;
uint32_t sel4: 5;
uint32_t no_gating_12m: 1;
uint32_t reserved26: 6;
uint32_t sel0 : 5;
uint32_t sel1 : 5;
uint32_t sel2 : 5;
uint32_t sel3 : 5;
uint32_t sel4 : 5;
uint32_t no_gating_12m : 1;
uint32_t reserved26 : 6;
};
uint32_t val;
} debug_sel;
union {
struct {
uint32_t reserved0: 13;
uint32_t fun_ie: 1; /*input enable in work mode*/
uint32_t slp_oe: 1; /*output enable in sleep mode*/
uint32_t slp_ie: 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t fun_sel: 2; /*function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t xpd: 1; /*TOUCH_XPD*/
uint32_t tie_opt: 1; /*TOUCH_TIE_OPT*/
uint32_t start: 1; /*TOUCH_START*/
uint32_t reserved0 : 13;
uint32_t fun_ie : 1; /*input enable in work mode*/
uint32_t slp_oe : 1; /*output enable in sleep mode*/
uint32_t slp_ie : 1; /*input enable in sleep mode*/
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t fun_sel : 2; /*function sel*/
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t xpd : 1; /*TOUCH_XPD*/
uint32_t tie_opt : 1; /*TOUCH_TIE_OPT*/
uint32_t start : 1; /*TOUCH_START*/
uint32_t dac: 3; /*TOUCH_DAC*/
uint32_t reserved26: 1;
uint32_t rue: 1; /*RUE*/
uint32_t rde: 1; /*RDE*/
uint32_t drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t rue : 1; /*RUE*/
uint32_t rde : 1; /*RDE*/
uint32_t drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} touch_pad[15];
union {
struct {
uint32_t reserved0: 13;
uint32_t x32p_fun_ie: 1; /*input enable in work mode*/
uint32_t x32p_slp_oe: 1; /*output enable in sleep mode*/
uint32_t x32p_slp_ie: 1; /*input enable in sleep mode*/
uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32p_fun_sel: 2; /*function sel*/
uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t x32p_rue: 1; /*RUE*/
uint32_t x32p_rde: 1; /*RDE*/
uint32_t x32p_drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 13;
uint32_t x32p_fun_ie : 1; /*input enable in work mode*/
uint32_t x32p_slp_oe : 1; /*output enable in sleep mode*/
uint32_t x32p_slp_ie : 1; /*input enable in sleep mode*/
uint32_t x32p_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t x32p_fun_sel : 2; /*function sel*/
uint32_t x32p_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t x32p_rue : 1; /*RUE*/
uint32_t x32p_rde : 1; /*RDE*/
uint32_t x32p_drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} xtal_32p_pad;
union {
struct {
uint32_t reserved0: 13;
uint32_t x32n_fun_ie: 1; /*input enable in work mode*/
uint32_t x32n_slp_oe: 1; /*output enable in sleep mode*/
uint32_t x32n_slp_ie: 1; /*input enable in sleep mode*/
uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32n_fun_sel: 2; /*function sel*/
uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t x32n_rue: 1; /*RUE*/
uint32_t x32n_rde: 1; /*RDE*/
uint32_t x32n_drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 13;
uint32_t x32n_fun_ie : 1; /*input enable in work mode*/
uint32_t x32n_slp_oe : 1; /*output enable in sleep mode*/
uint32_t x32n_slp_ie : 1; /*input enable in sleep mode*/
uint32_t x32n_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t x32n_fun_sel : 2; /*function sel*/
uint32_t x32n_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t x32n_rue : 1; /*RUE*/
uint32_t x32n_rde : 1; /*RDE*/
uint32_t x32n_drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} xtal_32n_pad;
union {
struct {
uint32_t reserved0: 3;
uint32_t dac: 8; /*PDAC1_DAC*/
uint32_t xpd_dac: 1; /*PDAC1_XPD_DAC*/
uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
uint32_t fun_ie: 1; /*input enable in work mode*/
uint32_t slp_oe: 1; /*output enable in sleep mode*/
uint32_t slp_ie: 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t fun_sel: 2; /*PDAC1 function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rue: 1; /*PDAC1_RUE*/
uint32_t rde: 1; /*PDAC1_RDE*/
uint32_t drv: 2; /*PDAC1_DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 3;
uint32_t dac : 8; /*PDAC1_DAC*/
uint32_t xpd_dac : 1; /*PDAC1_XPD_DAC*/
uint32_t dac_xpd_force : 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
uint32_t fun_ie : 1; /*input enable in work mode*/
uint32_t slp_oe : 1; /*output enable in sleep mode*/
uint32_t slp_ie : 1; /*input enable in sleep mode*/
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t fun_sel : 2; /*PDAC1 function sel*/
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rue : 1; /*PDAC1_RUE*/
uint32_t rde : 1; /*PDAC1_RDE*/
uint32_t drv : 2; /*PDAC1_DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} pad_dac[2];
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad19_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad19_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad19_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad19_fun_sel: 2; /*function sel*/
uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad19_rue: 1; /*RUE*/
uint32_t rtc_pad19_rde: 1; /*RDE*/
uint32_t rtc_pad19_drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 13;
uint32_t rtc_pad19_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad19_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad19_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad19_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad19_fun_sel : 2; /*function sel*/
uint32_t rtc_pad19_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad19_rue : 1; /*RUE*/
uint32_t rtc_pad19_rde : 1; /*RDE*/
uint32_t rtc_pad19_drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} rtc_pad19;
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad20_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad20_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad20_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad20_fun_sel: 2; /*function sel*/
uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad20_rue: 1; /*RUE*/
uint32_t rtc_pad20_rde: 1; /*RDE*/
uint32_t rtc_pad20_drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 13;
uint32_t rtc_pad20_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad20_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad20_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad20_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad20_fun_sel : 2; /*function sel*/
uint32_t rtc_pad20_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad20_rue : 1; /*RUE*/
uint32_t rtc_pad20_rde : 1; /*RDE*/
uint32_t rtc_pad20_drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} rtc_pad20;
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad21_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad21_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad21_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad21_fun_sel: 2; /*function sel*/
uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad21_rue: 1; /*RUE*/
uint32_t rtc_pad21_rde: 1; /*RDE*/
uint32_t rtc_pad21_drv: 2; /*DRV*/
uint32_t reserved31: 1;
uint32_t reserved0 : 13;
uint32_t rtc_pad21_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad21_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad21_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad21_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad21_fun_sel : 2; /*function sel*/
uint32_t rtc_pad21_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad21_rue : 1; /*RUE*/
uint32_t rtc_pad21_rde : 1; /*RDE*/
uint32_t rtc_pad21_drv : 2; /*DRV*/
uint32_t reserved31 : 1;
};
uint32_t val;
} rtc_pad21;
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5;
uint32_t reserved0 : 27;
uint32_t sel : 5;
};
uint32_t val;
} ext_wakeup0;
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
uint32_t reserved0 : 27;
uint32_t sel : 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
};
uint32_t val;
} xtl_ext_ctr;
union {
struct {
uint32_t reserved0: 23;
uint32_t debug_bit_sel: 5;
uint32_t scl_sel: 2;
uint32_t sda_sel: 2;
uint32_t reserved0 : 23;
uint32_t debug_bit_sel : 5;
uint32_t scl_sel : 2;
uint32_t sda_sel : 2;
};
uint32_t val;
} sar_i2c_io;
union {
struct {
uint32_t io_touch_bufsel: 4; /*BUF_SEL when touch work without fsm*/
uint32_t io_touch_bufmode: 1; /*BUF_MODE when touch work without fsm*/
uint32_t reserved5: 27;
uint32_t io_touch_bufsel : 4; /*BUF_SEL when touch work without fsm*/
uint32_t io_touch_bufmode : 1; /*BUF_MODE when touch work without fsm*/
uint32_t reserved5 : 27;
};
uint32_t val;
} touch_ctrl;
@ -340,15 +341,17 @@ typedef volatile struct {
uint32_t reserved_1f8;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} rtc_io_dev_t;
extern rtc_io_dev_t RTCIO;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_IO_STRUCT_H_ */

2736
components/soc/esp32s3/include/soc/sens_reg.h
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122
components/soc/esp32s3/include/soc/sens_struct.h
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@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SENS_STRUCT_H_
#define _SOC_SENS_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@ -234,26 +235,18 @@ typedef volatile struct {
} sar_touch_conf;
union {
struct {
uint32_t thresh: 22; /*Finger threshold for touch pad 1*/
uint32_t reserved22: 10;
uint32_t touch_denoise_data : 22;
uint32_t reserved22 : 10;
};
uint32_t val;
} sar_touch_denoise;
union {
struct {
uint32_t thresh : 22; /*Finger threshold for touch pad 1*/
uint32_t reserved22 : 10;
};
uint32_t val;
} touch_thresh[14];
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
union {
struct {
uint32_t touch_pad_active: 15; /*touch active status*/
@ -431,13 +424,12 @@ typedef volatile struct {
uint32_t sar_nouse; /**/
union {
struct {
uint32_t reserved0: 26;
uint32_t dac_clk_en: 1;
uint32_t rtc_i2c_clk_en: 1;
uint32_t reserved28: 1;
uint32_t tsens_clk_en: 1;
uint32_t saradc_clk_en: 1;
uint32_t iomux_clk_en: 1;
uint32_t reserved0 : 27;
uint32_t rtc_i2c_clk_en : 1;
uint32_t reserved28 : 1;
uint32_t tsens_clk_en : 1;
uint32_t saradc_clk_en : 1;
uint32_t iomux_clk_en : 1;
};
uint32_t val;
} sar_peri_clk_gate_conf;
@ -445,7 +437,7 @@ typedef volatile struct {
struct {
uint32_t reserved0: 25;
uint32_t reset: 1;
uint32_t dac_reset: 1;
uint32_t reserved26 : 1;
uint32_t rtc_i2c_reset: 1;
uint32_t reserved28: 1;
uint32_t tsens_reset: 1;
@ -492,15 +484,81 @@ typedef volatile struct {
} sar_cocpu_int_ena_w1tc;
union {
struct {
uint32_t sar_date: 28;
uint32_t reserved28: 4;
uint32_t debug_bit_sel : 5;
uint32_t reserved5 : 27;
};
uint32_t val;
} sar_debug_conf;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t sar_date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} sardate;
} sens_dev_t;
extern sens_dev_t SENS;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SENS_STRUCT_H_ */

7848
components/soc/esp32s3/include/soc/sensitive_reg.h
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1878
components/soc/esp32s3/include/soc/sensitive_struct.h
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37
components/soc/esp32s3/include/soc/sigmadelta_caps.h Normal file
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@ -0,0 +1,37 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S3 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

2
components/soc/esp32s3/include/soc/soc.h
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@ -85,11 +85,13 @@
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_PERI_BACKUP_BASE 0x6002A000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_SPI4_BASE 0x60037000
#define DR_REG_USB_DEVICE_BASE 0x60038000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_LCD_CAM_BASE 0x60041000

3671
components/soc/esp32s3/include/soc/spi_mem_reg.h
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679
components/soc/esp32s3/include/soc/spi_mem_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,489 +11,563 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SPI_MEM_STRUCT_H_
#define _SOC_SPI_MEM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t reserved0 : 17; /*reserved*/
uint32_t flash_pe : 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t reserved0 : 17; /*reserved*/
uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_res : 1; /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pp : 1; /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
};
uint32_t val;
} cmd;
uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t fdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/
uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/
uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_t fcs_crc_en : 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12 : 1; /*reserved*/
uint32_t fastrd_mode : 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual : 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t reserved15 : 3; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t reserved22 : 1; /*reserved*/
uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t reserved25 : 7; /*reserved*/
uint32_t reserved0 : 3; /*reserved*/
uint32_t fdummy_out : 1; /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
uint32_t fdout_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/
uint32_t fdin_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/
uint32_t faddr_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/
uint32_t fcmd_dual : 1; /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/
uint32_t fcmd_quad : 1; /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/
uint32_t fcmd_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/
uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12 : 1; /*reserved*/
uint32_t fastrd_mode : 1; /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/
uint32_t fread_dual : 1; /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
uint32_t reserved16 : 2; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/
uint32_t fread_quad : 1; /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */
uint32_t wrsr_2b : 1; /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */
uint32_t fread_dio : 1; /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */
uint32_t fread_qio : 1; /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t cs_hold_dly_res : 12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
uint32_t cs_hold_dly : 12; /*SPI fsm is delayed to idle by spi clock cycles.*/
uint32_t cs_dly_num : 2; /*spi_mem_cs signal is delayed by system clock cycles*/
uint32_t cs_dly_mode : 2; /*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/
uint32_t reserved30 : 1;
uint32_t cs_dly_edge : 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/
uint32_t clk_mode : 2; /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
uint32_t cs_hold_dly_res : 10; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by SPI_CLK.*/
uint32_t reserved12 : 18; /*reserved*/
uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time : 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/
uint32_t reserved13 : 18; /*reserved*/
uint32_t sync_reset : 1; /*The FSM will be reset.*/
uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t ecc_cs_hold_time: 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/
uint32_t ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
uint32_t ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
uint32_t reserved15: 10; /*reserved*/
uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_t sync_reset : 1; /*The FSM will be reset.*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk.*/
uint32_t clk_equ_sysclk : 1; /*reserved*/
uint32_t clkcnt_l : 8; /*It must equal to the value of SPI_MEM_CLKCNT_N. */
uint32_t clkcnt_h : 8; /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
uint32_t clkcnt_n : 8; /*When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t reserved8 : 1; /*reserved*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t reserved16 : 8; /*reserved*/
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/
uint32_t reserved0: 6; /*reserved*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t reserved8: 1; /*reserved*/
uint32_t ck_out_edge : 1; /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
uint32_t fwrite_quad : 1; /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
uint32_t fwrite_dio : 1; /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
uint32_t fwrite_qio : 1; /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/
uint32_t reserved16 : 8; /*reserved*/
uint32_t usr_miso_highpart : 1; /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
uint32_t usr_mosi_highpart : 1; /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
uint32_t usr_dummy_idle : 1; /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
uint32_t usr_mosi : 1; /*This bit enable the DOUT phase of an write-data operation.*/
uint32_t usr_miso : 1; /*This bit enable the DIN phase of a read-data operation.*/
uint32_t usr_dummy : 1; /*This bit enable the DUMMY phase of an operation.*/
uint32_t usr_addr : 1; /*This bit enable the ADDR phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the CMD phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved6 : 20; /*reserved*/
uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t usr_dummy_cyclelen : 6; /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/
uint32_t reserved6 : 20; /*reserved*/
uint32_t usr_addr_bitlen : 6; /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
uint32_t usr_command_value : 16; /*The value of user defined(USR) command.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen : 4; /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len : 11; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved11 : 21; /*reserved*/
uint32_t usr_mosi_bit_len:10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len : 11; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved11 : 21; /*reserved*/
uint32_t usr_miso_bit_len:10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} miso_dlen;
union {
struct {
uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t reserved24 : 8; /*reserved*/
uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} rd_status;
uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/
uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/
union {
struct {
uint32_t cs0_dis : 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis : 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/
uint32_t reserved2 : 1; /*reserved*/
uint32_t trans_end : 1; /*The bit is used to indicate the transimitting is done.*/
uint32_t trans_end_en : 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
uint32_t cs_pol : 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
uint32_t fsub_pin : 1; /*For SPI0 flash is connected to SUBPINs.*/
uint32_t ssub_pin : 1; /*For SPI0 sram is connected to SUBPINs.*/
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set.*/
uint32_t auto_per : 1; /*reserved*/
uint32_t reserved12 : 20; /*reserved*/
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/
uint32_t reserved2: 1; /*reserved*/
uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/
uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
uint32_t reserved5: 2; /*reserved*/
uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/
uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t auto_per: 1; /*reserved*/
uint32_t reserved12: 20; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc; /*For SPI1 the value of crc32.*/
uint32_t tx_crc; /*For SPI1 the value of crc32.*/
union {
struct {
uint32_t req_en : 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte : 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash_usr_cmd : 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_t fdin_dual : 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdout_dual : 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t faddr_dual : 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad : 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad : 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t faddr_quad : 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t reserved9 : 23; /*reserved*/
uint32_t req_en : 1; /*Set this bit to enable Cache's access and SPI0's transfer.*/
uint32_t usr_cmd_4byte : 1; /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/
uint32_t flash_usr_cmd : 1; /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
uint32_t fdin_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
uint32_t fdout_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/
uint32_t faddr_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/
uint32_t fdin_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/
uint32_t fdout_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/
uint32_t faddr_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t usr_scmd_4byte : 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t usr_sram_dio : 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_t usr_sram_qio : 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_t usr_wr_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_t usr_rd_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd : 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t sram_rdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved12 : 2; /*reserved*/
uint32_t sram_addr_bitlen : 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd : 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t sram_oct : 1; /*reserved*/
uint32_t sram_wdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved28 : 4; /*reserved*/
uint32_t usr_scmd_4byte : 1; /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
uint32_t usr_sram_dio : 1; /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
uint32_t usr_sram_qio : 1; /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
uint32_t usr_wr_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/
uint32_t usr_rd_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/
uint32_t usr_rcmd : 1; /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/
uint32_t sram_rdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/
uint32_t reserved12 : 2; /*reserved*/
uint32_t sram_addr_bitlen : 6; /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/
uint32_t usr_wcmd : 1; /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
uint32_t sram_oct : 1; /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/
uint32_t sram_wdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t swb_mode : 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t sdin_dual : 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdout_dual : 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t saddr_dual : 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t scmd_dual : 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdin_quad : 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdout_quad : 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t saddr_quad : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t scmd_quad : 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdin_oct : 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdout_oct : 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/
uint32_t saddr_oct : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/
uint32_t scmd_oct : 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved23 : 9; /*reserved*/
uint32_t sclk_mode : 2; /*SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/
uint32_t swb_mode : 8; /*Mode bits when SPI0 accesses to Ext_RAM.*/
uint32_t sdin_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
uint32_t sdout_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
uint32_t saddr_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/
uint32_t scmd_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/
uint32_t sdin_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/
uint32_t sdout_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/
uint32_t saddr_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/
uint32_t scmd_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/
uint32_t sdin_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
uint32_t sdout_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
uint32_t saddr_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/
uint32_t scmd_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/
uint32_t sdummy_out : 1; /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value : 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
uint32_t usr_rd_cmd_value : 16; /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen : 4; /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value : 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/
uint32_t usr_wr_cmd_value : 16; /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen : 4; /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t cnt_l : 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/
uint32_t cnt_h : 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t cnt_n : 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t equ_sysclk : 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
uint32_t cnt_l : 8; /*It must equal to the value of SPI_MEM_SCLKCNT_N. */
uint32_t cnt_h : 8; /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/
uint32_t cnt_n : 8; /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t equ_sysclk : 1; /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
};
uint32_t val;
} sram_clk;
union {
struct {
uint32_t st : 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved3 : 29; /*reserved*/
uint32_t st : 3; /*The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} fsm;
uint32_t data_buf[18]; /*data buffer*/
uint32_t data_buf[16]; /*data buffer*/
union {
struct {
uint32_t waiti_en : 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/
uint32_t waiti_dummy : 1; /*The dummy phase enable when auto wait flash idle*/
uint32_t waiti_cmd : 8; /*The command to auto wait idle*/
uint32_t waiti_dummy_cyclelen : 8; /*The dummy cycle length when auto wait flash idle*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t waiti_en : 1; /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
uint32_t waiti_dummy : 1; /*The dummy phase enable when auto wait flash idle*/
uint32_t waiti_cmd : 8; /*The command to auto wait idle*/
uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when auto wait flash idle */
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} flash_waiti_ctrl;
union {
struct {
uint32_t flash_per : 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes : 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t reserved2 : 30;
uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_per_wait_en : 1; /*Set this bit to add delay time after program erase resume(PER) is sent.*/
uint32_t flash_pes_wait_en : 1; /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
uint32_t pes_per_en : 1; /*Set this bit to enable PES transfer trigger PES transfer option.*/
uint32_t pesr_idle_en : 1; /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} flash_sus_cmd;
union {
struct {
uint32_t flash_pes_en : 1; /*Auto-suspending enable*/
uint32_t flash_per_command : 8; /*Program/Erase resume command.*/
uint32_t flash_pes_command : 8; /*Program/Erase suspend command.*/
uint32_t reserved17 : 15;
uint32_t flash_pes_en : 1; /*Set this bit to enable auto-suspend function.*/
uint32_t flash_per_command : 8; /*Program/Erase resume command value.*/
uint32_t flash_pes_command : 8; /*Program/Erase suspend command value.*/
uint32_t reserved17 : 15; /*reserved*/
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t flash_sus : 1; /*The status of flash suspend only used in SPI1.*/
uint32_t reserved1 : 31;
uint32_t flash_sus : 1; /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/
uint32_t reserved1 : 1; /*reserved*/
uint32_t flash_hpm_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
uint32_t flash_res_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
uint32_t flash_dp_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
uint32_t flash_per_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
uint32_t flash_pes_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
uint32_t reserved7 : 25; /*reserved*/
};
uint32_t val;
} sus_status;
union {
struct {
uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5 : 27;
uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5: 27;
};
uint32_t val;
} timing_cali;
union {
struct {
uint32_t din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t din0_num : 2; /*SPI_D input delay number.*/
uint32_t din1_num : 2; /*SPI_Q input delay number.*/
uint32_t din2_num : 2; /*SPI_WP input delay number.*/
uint32_t din3_num : 2; /*SPI_HD input delay number.*/
uint32_t din4_num : 2; /*SPI_IO4 input delay number.*/
uint32_t din5_num : 2; /*SPI_IO5 input delay number.*/
uint32_t din6_num : 2; /*SPI_IO6 input delay number.*/
uint32_t din7_num : 2; /*SPI_IO7 input delay number.*/
uint32_t dins_num : 2; /*SPI_DQS input delay number.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved9 : 23; /*reserved*/
uint32_t dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} dout_mode;
uint32_t reserved_b8;
union {
struct {
uint32_t spi_smem_timing_clk_ena : 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/
uint32_t spi_smem_timing_cali : 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t spi_smem_extra_dummy_cyclelen : 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5 : 27;
uint32_t smem_timing_clk_ena : 1; /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
uint32_t smem_timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
uint32_t smem_extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} spi_smem_timing_cali;
union {
struct {
uint32_t spi_smem_din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t smem_din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} spi_smem_din_mode;
union {
struct {
uint32_t spi_smem_din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dins_num : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t smem_din0_num : 2; /*SPI_D input delay number.*/
uint32_t smem_din1_num : 2; /*SPI_Q input delay number.*/
uint32_t smem_din2_num : 2; /*SPI_WP input delay number.*/
uint32_t smem_din3_num : 2; /*SPI_HD input delay number.*/
uint32_t smem_din4_num : 2; /*SPI_IO4 input delay number.*/
uint32_t smem_din5_num : 2; /*SPI_IO5 input delay number.*/
uint32_t smem_din6_num : 2; /*SPI_IO6 input delay number.*/
uint32_t smem_din7_num : 2; /*SPI_IO7 input delay number.*/
uint32_t smem_dins_num : 2; /*SPI_DQS input delay number.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} spi_smem_din_num;
union {
struct {
uint32_t spi_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t reserved9 : 23; /*reserved*/
uint32_t smem_dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} spi_smem_dout_mode;
uint32_t reserved_cc;
union {
struct {
uint32_t spi_smem_cs_setup : 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_hold : 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_setup_time : 5; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t spi_smem_cs_hold_time : 5; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t spi_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accessed external RAM.*/
uint32_t reserved15 : 17;
uint32_t ecc_err_int_num : 8; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} ecc_ctrl;
uint32_t ecc_err_addr;
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
uint32_t ecc_data_err_bit : 7; /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
uint32_t ecc_chk_err_bit : 3; /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
uint32_t ecc_byte_err : 1; /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
uint32_t ecc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ecc_err_bit;
uint32_t reserved_d8;
union {
struct {
uint32_t smem_cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
uint32_t smem_cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
uint32_t smem_cs_setup_time : 5; /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
uint32_t smem_cs_hold_time : 5; /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
uint32_t smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
uint32_t smem_ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/
uint32_t smem_ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/
uint32_t reserved17 : 7; /*reserved*/
uint32_t smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
uint32_t smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} spi_smem_ac;
union {
struct {
uint32_t spi_fmem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/
uint32_t spi_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to flash.*/
uint32_t spi_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to flash.*/
uint32_t spi_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_fmem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/
uint32_t spi_fmem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t spi_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t spi_fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t spi_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t spi_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t spi_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
uint32_t spi_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
uint32_t spi_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
uint32_t fmem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in DDR mode.*/
uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder RX data of the word in DDR mode.*/
uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to swap TX data of a word in DDR mode.*/
uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/
uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/
uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
uint32_t fmem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
uint32_t fmem_ddr_dqs_loop_mode : 1; /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
uint32_t reserved23 : 1; /*reserved*/
uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} ddr;
union {
struct {
uint32_t spi_smem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/
uint32_t spi_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to external RAM.*/
uint32_t spi_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to external RAM.*/
uint32_t spi_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_smem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/
uint32_t spi_smem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t spi_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t spi_smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t spi_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t spi_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t spi_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
uint32_t spi_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
uint32_t spi_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
uint32_t smem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
uint32_t smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
uint32_t smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/
uint32_t smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/
uint32_t smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/
uint32_t smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
uint32_t smem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
uint32_t smem_ddr_dqs_loop_mode : 1; /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
uint32_t reserved23 : 1; /*reserved*/
uint32_t smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
uint32_t smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
uint32_t smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
uint32_t smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} spi_smem_ddr;
union {
struct {
uint32_t clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
uint32_t reserved1 : 31; /*reserved*/
uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
uint32_t reserved1: 31; /*reserved*/
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t spi01_clk_sel : 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
uint32_t reserved2 : 30; /*reserved*/
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} core_clk_sel;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
union {
struct {
uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_en : 1; /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t per_end_int_clr : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_int_clr : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_int_clr : 1; /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_int_clr : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_int_clr : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/
uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t per_end_int_st : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_int_st : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_int_st : 1; /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_int_st : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_int_st : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_st;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
@ -687,14 +761,19 @@ typedef volatile struct {
uint32_t reserved_3f8;
union {
struct {
uint32_t date : 28; /*SPI register version.*/
uint32_t reserved28 : 4; /*reserved*/
uint32_t date : 28; /*SPI register version.*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SPI_MEM_STRUCT_H_ */

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