rtc: add pwdet and sar adc power related low level func

components/esp_hw_support/port/esp32/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,12 +15,22 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "hal/sar_ctrl_ll.h"
 
+static const char *TAG = "sar_periph_ctrl";
 extern portMUX_TYPE rtc_spinlock;
 
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
+
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to ON state
@@ -35,3 +45,28 @@ void sar_periph_ctrl_power_disable(void)
     sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,12 +16,22 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "hal/sar_ctrl_ll.h"
 
+static const char *TAG = "sar_periph_ctrl";
 extern portMUX_TYPE rtc_spinlock;
 
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
+
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to FSM state
@@ -36,3 +46,28 @@ void sar_periph_ctrl_power_disable(void)
     sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,12 +16,22 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "hal/sar_ctrl_ll.h"
 
+static const char *TAG = "sar_periph_ctrl";
 extern portMUX_TYPE rtc_spinlock;
 
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
+
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to FSM state
@@ -36,3 +46,28 @@ void sar_periph_ctrl_power_disable(void)
     sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,8 +15,21 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+static const char *TAG = "sar_periph_ctrl";
+extern portMUX_TYPE rtc_spinlock;
+
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
 
 void sar_periph_ctrl_init(void)
 {
@@ -27,3 +40,30 @@ void sar_periph_ctrl_power_disable(void)
 {
     //TODO: IDF-6124
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+        sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_force_power_ctrl_from_pwdet(false);
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,12 +16,22 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "hal/sar_ctrl_ll.h"
 
+static const char *TAG = "sar_periph_ctrl";
 extern portMUX_TYPE rtc_spinlock;
 
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
+
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to FSM state
@@ -36,3 +46,28 @@ void sar_periph_ctrl_power_disable(void)
     sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,12 +16,22 @@
  */
 
 #include "sdkconfig.h"
+#include "esp_log.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "hal/sar_ctrl_ll.h"
 
+static const char *TAG = "sar_periph_ctrl";
 extern portMUX_TYPE rtc_spinlock;
 
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+// This gets incremented when sar_periph_ctrl_pwdet_power_acquire() is called,
+// and decremented when sar_periph_ctrl_pwdet_power_release() is called. PWDET
+// is powered down when the value reaches zero. Should be modified within critical section.
+static int s_pwdet_power_on_cnt;
+
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to FSM state
@@ -36,3 +46,28 @@ void sar_periph_ctrl_power_disable(void)
     sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 }
+
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    /* Sanity check */
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}

components/hal/esp32c2/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,12 +19,16 @@
 #pragma once
 
 #include <stdlib.h>
+#include "soc/soc.h"
 #include "soc/rtc_cntl_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x6004EB60
+#define PWDET_SAR_POWER_FORCE BIT(7)
+#define PWDET_SAR_POWER_CNTL  BIT(6)
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -51,6 +55,24 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     }
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
 
 #ifdef __cplusplus
 }

components/hal/esp32c3/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,12 +19,17 @@
 #pragma once
 
 #include <stdlib.h>
+#include "soc/soc.h"
 #include "soc/rtc_cntl_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x6000E060
+#define PWDET_SAR_POWER_FORCE BIT(7)
+#define PWDET_SAR_POWER_CNTL  BIT(6)
+
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -51,6 +56,24 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     }
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
 
 #ifdef __cplusplus
 }

components/hal/esp32c6/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,11 +18,18 @@
 #pragma once
 
 #include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/apb_saradc_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x600A8010
+#define PWDET_SAR_POWER_FORCE BIT(24)
+#define PWDET_SAR_POWER_CNTL  BIT(23)
+
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -44,6 +51,33 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     abort();
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
+/**
+ * @brief Set SAR power ctrl source
+ *
+ * @param[in] force  set PWDET as SAR power ctrl source when force is true
+ */
+static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force)
+{
+    APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force;
+}
 
 #ifdef __cplusplus
 }

components/hal/esp32h4/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,11 +19,16 @@
 #pragma once
 
 #include <stdlib.h>
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x600A8010
+#define PWDET_SAR_POWER_FORCE BIT(24)
+#define PWDET_SAR_POWER_CNTL  BIT(23)
+
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -45,6 +50,24 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     abort();
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
 
 #ifdef __cplusplus
 }

components/hal/esp32s2/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,12 +19,17 @@
 #pragma once
 
 #include <stdlib.h>
+#include "soc/soc.h"
 #include "soc/sens_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x6000E060
+#define PWDET_SAR_POWER_FORCE BIT(7)
+#define PWDET_SAR_POWER_CNTL  BIT(6)
+
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -51,6 +56,24 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     }
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
 
 #ifdef __cplusplus
 }

components/hal/esp32s3/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,12 +19,17 @@
 #pragma once
 
 #include <stdlib.h>
+#include "soc/soc.h"
 #include "soc/sens_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define PWDET_CONF_REG        0x6000E060
+#define PWDET_SAR_POWER_FORCE BIT(7)
+#define PWDET_SAR_POWER_CNTL  BIT(6)
+
 
 typedef enum {
     SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
@@ -51,6 +56,24 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
     }
 }
 
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
+    }
+}
+
 
 #ifdef __cplusplus
 }