drivers: fix issue reported by coverity

components/esp_hw_support/dma/gdma.c

@@ -716,7 +716,7 @@ static void IRAM_ATTR gdma_default_rx_isr(void *args)
     gdma_ll_rx_clear_interrupt_status(group->hal.dev, pair->pair_id, intr_status);
 
     if (intr_status & GDMA_LL_EVENT_RX_SUC_EOF) {
-        if (rx_chan && rx_chan->on_recv_eof) {
+        if (rx_chan->on_recv_eof) {
             uint32_t eof_addr = gdma_ll_rx_get_success_eof_desc_addr(group->hal.dev, pair->pair_id);
             gdma_event_data_t edata = {
                 .rx_eof_desc_addr = eof_addr

components/hal/esp32s3/include/hal/i2c_ll.h

@@ -300,10 +300,7 @@ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, boo
 __attribute__((always_inline))
 static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
 {
-    ESP_STATIC_ASSERT(sizeof(i2c_comd0_reg_t) == sizeof(i2c_ll_hw_cmd_t),
+    hw->comd[cmd_idx].val = cmd.val;
-                      "i2c_comdX_reg_t structure size must be equal to i2c_ll_hw_cmd_t structure size");
-    volatile i2c_ll_hw_cmd_t* commands = (volatile i2c_ll_hw_cmd_t*) &hw->comd0;
-    commands[cmd_idx].val = cmd.val;
 }
 
 /**

components/soc/esp32s3/include/soc/i2c_struct.h

@@ -902,8 +902,8 @@ typedef union {
 
 
 /** Group: Command registers */
-/** Type of comd0 register
+/** Type of command register
- *  I2C command register 0
+ *  I2C command register
  */
 typedef union {
     struct {
@@ -915,181 +915,16 @@ typedef union {
          *  structure for more
          *  Information.
          */
-        uint32_t command0:14;
+        uint32_t command:14;
         uint32_t reserved_14:17;
         /** command0_done : R/W/SS; bitpos: [31]; default: 0;
          *  When command 0 is done in I2C Master mode, this bit changes to high
          *  level.
          */
-        uint32_t command0_done:1;
+        uint32_t command_done:1;
     };
     uint32_t val;
-} i2c_comd0_reg_t;
+} i2c_comd_reg_t;
-
-/** Type of comd1 register
- *  I2C command register 1
- */
-typedef union {
-    struct {
-        /** command1 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 1. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command1:14;
-        uint32_t reserved_14:17;
-        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 1 is done in I2C Master mode, this bit changes to high
-         *  level.
-         */
-        uint32_t command1_done:1;
-    };
-    uint32_t val;
-} i2c_comd1_reg_t;
-
-/** Type of comd2 register
- *  I2C command register 2
- */
-typedef union {
-    struct {
-        /** command2 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 2. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command2:14;
-        uint32_t reserved_14:17;
-        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 2 is done in I2C Master mode, this bit changes to high
-         *  Level.
-         */
-        uint32_t command2_done:1;
-    };
-    uint32_t val;
-} i2c_comd2_reg_t;
-
-/** Type of comd3 register
- *  I2C command register 3
- */
-typedef union {
-    struct {
-        /** command3 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 3. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command3:14;
-        uint32_t reserved_14:17;
-        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 3 is done in I2C Master mode, this bit changes to high
-         *  level.
-         */
-        uint32_t command3_done:1;
-    };
-    uint32_t val;
-} i2c_comd3_reg_t;
-
-/** Type of comd4 register
- *  I2C command register 4
- */
-typedef union {
-    struct {
-        /** command4 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 4. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command4:14;
-        uint32_t reserved_14:17;
-        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 4 is done in I2C Master mode, this bit changes to high
-         *  level.
-         */
-        uint32_t command4_done:1;
-    };
-    uint32_t val;
-} i2c_comd4_reg_t;
-
-/** Type of comd5 register
- *  I2C command register 5
- */
-typedef union {
-    struct {
-        /** command5 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 5. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command5:14;
-        uint32_t reserved_14:17;
-        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 5 is done in I2C Master mode, this bit changes to high level.
-         */
-        uint32_t command5_done:1;
-    };
-    uint32_t val;
-} i2c_comd5_reg_t;
-
-/** Type of comd6 register
- *  I2C command register 6
- */
-typedef union {
-    struct {
-        /** command6 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 6. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command6:14;
-        uint32_t reserved_14:17;
-        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 6 is done in I2C Master mode, this bit changes to high level.
-         */
-        uint32_t command6_done:1;
-    };
-    uint32_t val;
-} i2c_comd6_reg_t;
-
-/** Type of comd7 register
- *  I2C command register 7
- */
-typedef union {
-    struct {
-        /** command7 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 7. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command7:14;
-        uint32_t reserved_14:17;
-        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 7 is done in I2C Master mode, this bit changes to high level.
-         */
-        uint32_t command7_done:1;
-    };
-    uint32_t val;
-} i2c_comd7_reg_t;
 
 
 /** Group: Version register */
@@ -1158,14 +993,7 @@ typedef struct {
     volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
     volatile i2c_filter_cfg_reg_t filter_cfg;
     volatile i2c_clk_conf_reg_t clk_conf;
-    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd_reg_t comd[8];
-    volatile i2c_comd1_reg_t comd1;
-    volatile i2c_comd2_reg_t comd2;
-    volatile i2c_comd3_reg_t comd3;
-    volatile i2c_comd4_reg_t comd4;
-    volatile i2c_comd5_reg_t comd5;
-    volatile i2c_comd6_reg_t comd6;
-    volatile i2c_comd7_reg_t comd7;
     volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
     volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
     volatile i2c_scl_sp_conf_reg_t scl_sp_conf;

components/touch_element/touch_element.c

@@ -361,7 +361,7 @@ static void te_intr_cb(void *arg)
     static int scan_done_cnt = 0;
     static uint32_t touch_pre_trig_status = 0;
     int task_awoken = pdFALSE;
-    te_intr_msg_t te_intr_msg;
+    te_intr_msg_t te_intr_msg = {};
     /*< Figure out which touch sensor channel is triggered and the trigger type */
     uint32_t intr_mask = touch_pad_read_intr_status_mask();
     if (intr_mask == 0x0) {  //For dummy interrupt