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mcpwm: support esp32c6

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This commit is contained in:
morris 2022-09-05 14:40:58 +08:00
parent 7b425cbcd7
commit f997b81242
26 changed files with 2031 additions and 57 deletions
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84
components/driver/deprecated/driver/mcpwm.h
View File

@ -24,7 +24,7 @@ extern "C" {
*
* @note This function initializes one gpio at a time.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)
* 'X' is timer_num(0-2)
* @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16
@ -40,7 +40,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
*
* @note This function initialize a group of MCPWM GPIOs at a time.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param mcpwm_pin MCPWM pin structure
*
* @return
@ -56,7 +56,7 @@ esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_
* The default resolution can be changed by calling mcpwm_group_set_resolution() and mcpwm_timer_set_resolution(),
* before calling this function.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers.
* @param mcpwm_conf configure structure mcpwm_config_t
*
@ -74,7 +74,7 @@ esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcp
* to set them back.
* The group resolution must be an integral multiple of timer resolution.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param resolution set expected frequency resolution
*
* @return
@ -91,7 +91,7 @@ esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, unsigned long int r
* to set them back.
* The group resolution must be an integral multiple of timer resolution.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param resolution set expected frequency resolution
*
@ -104,7 +104,7 @@ esp_err_t mcpwm_timer_set_resolution(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer
/**
* @brief Set frequency(in Hz) of MCPWM timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param frequency set the frequency in Hz of each timer
*
@ -117,7 +117,7 @@ esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, u
/**
* @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the generator(MCPWMXA/MCPWMXB), 'X' is operator number selected
* @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator
@ -131,7 +131,7 @@ esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_
/**
* @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the generator(MCPWMXA/MCPWMXB), 'x' is operator number selected
* @param duty_in_us set duty value in microseconds of each operator
@ -147,7 +147,7 @@ esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
* @note
* Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the generator(MCPWMXA/MCPWMXB), 'x' is operator number selected
* @param duty_type set active low or active high duty type
@ -161,7 +161,7 @@ esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, m
/**
* @brief Get frequency of timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -172,7 +172,7 @@ uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
/**
* @brief Get duty cycle of each operator
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the generator(MCPWMXA/MCPWMXB), 'x' is operator number selected
*
@ -184,7 +184,7 @@ float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_oper
/**
* @brief Get duty cycle of each operator in us
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the generator(MCPWMXA/MCPWMXB), 'x' is operator number selected
*
@ -196,7 +196,7 @@ uint32_t mcpwm_get_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, m
/**
* @brief Use this function to set MCPWM signal high
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
*
@ -210,7 +210,7 @@ esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
/**
* @brief Use this function to set MCPWM signal low
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param gen set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
*
@ -224,7 +224,7 @@ esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
/**
* @brief Start MCPWM signal on timer 'x'
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -236,7 +236,7 @@ esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
/**
* @brief Start MCPWM signal on timer 'x'
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -248,7 +248,7 @@ esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
/**
* @brief Initialize carrier configuration
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param carrier_conf configure structure mcpwm_carrier_config_t
*
@ -261,7 +261,7 @@ esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, co
/**
* @brief Enable MCPWM carrier submodule, for respective timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -273,7 +273,7 @@ esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
/**
* @brief Disable MCPWM carrier submodule, for respective timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -285,7 +285,7 @@ esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
/**
* @brief Set period of carrier
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns
* (carrier_period <= 15)
@ -299,7 +299,7 @@ esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_n
/**
* @brief Set duty_cycle of carrier
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%
* (chop_duty <= 7)
@ -315,7 +315,7 @@ esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim
*
* @note The carrier oneshot pulse can't disabled.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)
* (pulse_width <= 15)
@ -329,7 +329,7 @@ esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_
/**
* @brief Enable or disable carrier output inversion
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param carrier_ivt_mode enable or disable carrier output inversion
*
@ -343,7 +343,7 @@ esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time
/**
* @brief Enable and initialize deadtime for each MCPWM timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param dt_mode set deadtime mode
* @param red set rising edge delay = (red + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`)
@ -359,7 +359,7 @@ esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
/**
* @brief Disable deadtime on MCPWM timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -371,7 +371,7 @@ esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num
/**
* @brief Initialize fault submodule, currently low level triggering is not supported
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param intput_level set fault signal level, which will cause fault to occur
* @param fault_sig set the fault pin, which needs to be enabled
*
@ -386,7 +386,7 @@ esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t int
* @note
* currently low level triggering is not supported
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param fault_sig set the fault pin, which needs to be enabled for oneshot mode
* @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
@ -404,7 +404,7 @@ esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim
* @note
* currently low level triggering is not supported
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param fault_sig set the fault pin, which needs to be enabled for cyc mode
* @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
@ -420,7 +420,7 @@ esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_n
/**
* @brief Disable fault signal
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param fault_sig fault pin, which needs to be disabled
*
* @return
@ -432,7 +432,7 @@ esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_
/**
* @brief Enable capture channel
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param cap_channel capture channel, which needs to be enabled
* @param cap_conf capture channel configuration
*
@ -445,7 +445,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
/**
* @brief Disable capture channel
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param cap_channel capture channel, which needs to be disabled
*
* @return
@ -457,7 +457,7 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch
/**
* @brief Get capture value
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param cap_sig capture channel on which value is to be measured
*
* @return
@ -465,10 +465,18 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch
*/
uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
/**
* @brief Get capture timer's resolution
*
* @param mcpwm_num set MCPWM unit
* @return Capture timer's resolution
*/
uint32_t mcpwm_capture_get_resolution(mcpwm_unit_t mcpwm_num);
/**
* @brief Get edge of capture signal
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param cap_sig capture channel of whose edge is to be determined
*
* @return
@ -479,7 +487,7 @@ uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_sig
/**
* @brief Initialize sync submodule and sets the signal that will cause the timer be loaded with pre-defined value
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param sync_conf sync configuration on this timer
*
@ -492,7 +500,7 @@ esp_err_t mcpwm_sync_configure(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
/**
* @brief Disable sync submodule on given timer
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @return
@ -505,7 +513,7 @@ esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
* @brief Set sync output on given timer
* Configures what event triggers MCPWM timer to output a sync signal.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
* @param trigger set the trigger that will cause the timer to generate a software sync signal.
* Specifically, `MCPWM_SWSYNC_SOURCE_DISABLED` will disable the timer from generating sync signal.
@ -518,7 +526,7 @@ esp_err_t mcpwm_set_timer_sync_output(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time
/**
* @brief Trigger a software sync event and sends it to a specific timer.
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
*
* @note This software sync event will have the same effect as hw one, except that:
@ -534,7 +542,7 @@ esp_err_t mcpwm_timer_trigger_soft_sync(mcpwm_unit_t mcpwm_num, mcpwm_timer_t ti
/**
* @brief Set external GPIO sync input inverter
*
* @param mcpwm_num set MCPWM unit(0-1)
* @param mcpwm_num set MCPWM unit
* @param sync_sig set sync signal of MCPWM, only supports GPIO sync signal
* @param invert whether GPIO sync source input is inverted (to get negative edge trigger)
*

20
components/driver/deprecated/mcpwm_legacy.c
View File

@ -22,6 +22,7 @@
#include "driver/mcpwm_types_legacy.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
static const char *TAG = "mcpwm(legacy)";
@ -47,7 +48,7 @@ _Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_GROUPS, "MCPWM unit number not equal
#define MCPWM_INTR_FLAG 0
#endif
#define MCPWM_GROUP_CLK_SRC_HZ 160000000
#define MCPWM_GROUP_CLK_SRC_HZ 160000000 // MCPWM clock source is fixed to `MCPWM_CAPTURE_CLK_SRC_PLL160M`
#define MCPWM_GROUP_CLK_PRESCALE (16)
#define MCPWM_GROUP_CLK_HZ (MCPWM_GROUP_CLK_SRC_HZ / MCPWM_GROUP_CLK_PRESCALE)
#define MCPWM_TIMER_CLK_HZ (MCPWM_GROUP_CLK_HZ / 10)
@ -405,6 +406,8 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
mcpwm_hal_init(hal, &config);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_group_enable_clock(hal->dev, true);
mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(hal->dev, context[mcpwm_num].group_pre_scale);
mcpwm_ll_timer_set_clock_prescale(hal->dev, timer_num, context[mcpwm_num].timer_pre_scale[timer_num]);
mcpwm_ll_timer_set_count_mode(hal->dev, timer_num, mcpwm_conf->counter_mode);
@ -795,6 +798,8 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
};
mcpwm_hal_init(hal, &init_config);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_group_enable_clock(hal->dev, true);
mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(hal->dev, context[mcpwm_num].group_pre_scale);
mcpwm_ll_capture_enable_timer(hal->dev, true);
mcpwm_ll_capture_enable_channel(hal->dev, cap_channel, true);
@ -867,6 +872,19 @@ uint32_t MCPWM_ISR_ATTR mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, m
return mcpwm_ll_capture_get_value(hal->dev, cap_sig);
}
uint32_t mcpwm_capture_get_resolution(mcpwm_unit_t mcpwm_num)
{
if (mcpwm_num >= MCPWM_UNIT_MAX) {
ESP_LOGE(TAG, "Invalid MCPWM instance");
return 0;
}
#if SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
return MCPWM_GROUP_CLK_SRC_HZ / context[mcpwm_num].group_pre_scale;
#else
return esp_clk_apb_freq();
#endif
}
uint32_t MCPWM_ISR_ATTR mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
{
if (mcpwm_num >= MCPWM_UNIT_MAX && cap_sig >= SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER) {

15
components/driver/mcpwm/mcpwm_cap.c
View File

@ -92,6 +92,16 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc
cap_timer = heap_caps_calloc(1, sizeof(mcpwm_cap_timer_t), MCPWM_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(cap_timer, ESP_ERR_NO_MEM, err, TAG, "no mem for capture timer");
ESP_GOTO_ON_ERROR(mcpwm_cap_timer_register_to_group(cap_timer, config->group_id), err, TAG, "register timer failed");
mcpwm_group_t *group = cap_timer->group;
int group_id = group->group_id;
#if SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
// capture timer clock source is same as the MCPWM group
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)config->clk_src), err, TAG, "set group clock failed");
cap_timer->resolution_hz = group->resolution_hz;
#else
// capture timer has independent clock source selection
switch (config->clk_src) {
case MCPWM_CAPTURE_CLK_SRC_APB:
cap_timer->resolution_hz = esp_clk_apb_freq();
@ -103,10 +113,7 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid clock source:%d", config->clk_src);
}
ESP_GOTO_ON_ERROR(mcpwm_cap_timer_register_to_group(cap_timer, config->group_id), err, TAG, "register timer failed");
mcpwm_group_t *group = cap_timer->group;
int group_id = group->group_id;
#endif
// fill in other capture timer specific members
cap_timer->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;

17
components/driver/mcpwm/mcpwm_com.c
View File

@ -15,6 +15,7 @@
#include "esp_log.h"
#include "esp_check.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "soc/mcpwm_periph.h"
#include "hal/mcpwm_ll.h"
#include "mcpwm_private.h"
@ -55,6 +56,7 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id)
// disable all interrupts and clear pending status
mcpwm_ll_intr_enable(hal->dev, UINT32_MAX, false);
mcpwm_ll_intr_clear_status(hal->dev, UINT32_MAX);
mcpwm_ll_group_enable_clock(hal->dev, true);
}
} else { // group already install
group = s_platform.groups[group_id];
@ -81,6 +83,7 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
if (s_platform.group_ref_counts[group_id] == 0) {
do_deinitialize = true;
s_platform.groups[group_id] = NULL; // deregister from platfrom
mcpwm_ll_group_enable_clock(group->hal.dev, false);
// hal layer deinitialize
mcpwm_hal_deinit(&group->hal);
periph_module_disable(mcpwm_periph_signals.groups[group_id].module);
@ -93,7 +96,7 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
}
}
esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, mcpwm_timer_clock_source_t clk_src)
esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_src)
{
esp_err_t ret = ESP_OK;
uint32_t periph_src_clk_hz = 0;
@ -114,7 +117,8 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, mcpwm_timer_clock_sour
if (do_clock_init) {
// [clk_tree] ToDo: replace the following switch-case table by clock_tree APIs
switch (clk_src) {
case MCPWM_TIMER_CLK_SRC_DEFAULT:
#if SOC_MCPWM_CLK_SUPPORT_PLL160M
case SOC_MOD_CLK_PLL_F160M:
periph_src_clk_hz = 160000000;
#if CONFIG_PM_ENABLE
sprintf(group->pm_lock_name, "mcpwm_%d", group->group_id); // e.g. mcpwm_0
@ -123,10 +127,19 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, mcpwm_timer_clock_sour
ESP_LOGD(TAG, "install ESP_PM_APB_FREQ_MAX lock for MCPWM group(%d)", group->group_id);
#endif // CONFIG_PM_ENABLE
break;
#endif // SOC_MCPWM_CLK_SUPPORT_PLL160M
#if SOC_MCPWM_CLK_SUPPORT_XTAL
case SOC_MOD_CLK_XTAL:
periph_src_clk_hz = esp_clk_xtal_freq();
break;
#endif // SOC_MCPWM_CLK_SUPPORT_XTAL
default:
ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "clock source %d is not supported", clk_src);
break;
}
mcpwm_ll_group_set_clock_source(group->hal.dev, clk_src);
mcpwm_ll_group_set_clock_prescale(group->hal.dev, MCPWM_PERIPH_CLOCK_PRE_SCALE);
group->resolution_hz = periph_src_clk_hz / MCPWM_PERIPH_CLOCK_PRE_SCALE;
ESP_LOGD(TAG, "group (%d) clock resolution:%"PRIu32"Hz", group->group_id, group->resolution_hz);

6
components/driver/mcpwm/mcpwm_private.h
View File

@ -57,8 +57,8 @@ struct mcpwm_group_t {
mcpwm_hal_context_t hal; // HAL instance is at group level
portMUX_TYPE spinlock; // group level spinlock
uint32_t resolution_hz; // MCPWM group clock resolution
esp_pm_lock_handle_t pm_lock; // power management lock
mcpwm_timer_clock_source_t clk_src; // source clock
esp_pm_lock_handle_t pm_lock; // power management lock
soc_module_clk_t clk_src; // peripheral source clock
mcpwm_cap_timer_t *cap_timer; // mcpwm capture timers
mcpwm_timer_t *timers[SOC_MCPWM_TIMERS_PER_GROUP]; // mcpwm timer array
mcpwm_oper_t *operators[SOC_MCPWM_OPERATORS_PER_GROUP]; // mcpwm operator array
@ -220,7 +220,7 @@ struct mcpwm_cap_channel_t {
mcpwm_group_t *mcpwm_acquire_group_handle(int group_id);
void mcpwm_release_group_handle(mcpwm_group_t *group);
esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, mcpwm_timer_clock_source_t clk_src);
esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_src);
#ifdef __cplusplus
}

2
components/driver/mcpwm/mcpwm_timer.c
View File

@ -101,7 +101,7 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle
mcpwm_hal_context_t *hal = &group->hal;
int timer_id = timer->timer_id;
// select the clock source
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, config->clk_src), err, TAG, "set group clock failed");
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)config->clk_src), err, TAG, "set group clock failed");
// reset the timer to a determined state
mcpwm_hal_timer_reset(hal, timer_id);
// set timer resolution

6
components/driver/test_apps/legacy_mcpwm_driver/main/test_legacy_mcpwm.c
View File

@ -487,7 +487,7 @@ static void mcpwm_swsync_test(mcpwm_unit_t unit)
vTaskDelay(pdMS_TO_TICKS(100));
uint32_t delta_timestamp_us = (cap_timestamp[2] - cap_timestamp[1]) * 1000000 / esp_clk_apb_freq();
uint32_t delta_timestamp_us = (cap_timestamp[2] - cap_timestamp[1]) * 1000000 / mcpwm_capture_get_resolution(unit);
uint32_t expected_phase_us = 1000000 / mcpwm_get_frequency(unit, MCPWM_TIMER_0) * test_sync_phase / 1000;
// accept +-2 error
TEST_ASSERT_UINT32_WITHIN(2, expected_phase_us, delta_timestamp_us);
@ -552,8 +552,8 @@ static void mcpwm_capture_test(mcpwm_unit_t unit, mcpwm_capture_signal_t cap_cha
gpio_set_level(TEST_CAP_GPIO, 1);
TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(40)));
uint32_t cap_val1 = mcpwm_capture_signal_get_value(unit, cap_chan);
// capture clock source is APB (80MHz), 100ms means 8000000 ticks
TEST_ASSERT_UINT_WITHIN(100000, 8000000, cap_val1 - cap_val0);
uint32_t delta = mcpwm_capture_get_resolution(unit) / (cap_val1 - cap_val0);
TEST_ASSERT_UINT_WITHIN(2, 10, delta);
TEST_ESP_OK(mcpwm_capture_disable_channel(unit, cap_channel));
}

4
components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c
View File

@ -48,7 +48,11 @@ TEST_CASE("mcpwm_operator_install_uninstall", "[mcpwm]")
TEST_ESP_OK(mcpwm_operator_connect_timer(operators[k++], timers[i]));
}
}
#if SOC_MCPWM_GROUPS > 1
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, mcpwm_operator_connect_timer(operators[0], timers[1]));
#endif
printf("uninstall operators and timers\r\n");
for (int i = 0; i < total_operators; i++) {
TEST_ESP_OK(mcpwm_del_operator(operators[i]));

26
components/hal/esp32/include/hal/mcpwm_ll.h
View File

@ -63,6 +63,32 @@ typedef enum {
////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, mcpwm_timer_clock_source_t clk_src)
{
(void)mcpwm;
(void)clk_src;
}
/**
* @brief Enable MCPWM module clock
*
* @note Not support to enable/disable the peripheral clock
*
* @param mcpwm Peripheral instance address
* @param en true to enable, false to disable
*/
static inline void mcpwm_ll_group_enable_clock(mcpwm_dev_t *mcpwm, bool en)
{
(void)mcpwm; // only one MCPWM instance
(void)en;
}
/**
* @brief Set the MCPWM group clock prescale
*

8
components/hal/esp32c6/include/hal/clk_gate_ll.h
View File

@ -54,6 +54,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return PCR_TWAI1_CLK_EN;
case PERIPH_GDMA_MODULE:
return PCR_GDMA_CLK_EN;
case PERIPH_MCPWM0_MODULE:
return PCR_PWM_CLK_EN;
case PERIPH_AES_MODULE:
return PCR_AES_CLK_EN;
case PERIPH_SHA_MODULE:
@ -120,6 +122,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return PCR_TWAI1_RST_EN;
case PERIPH_GDMA_MODULE:
return PCR_GDMA_RST_EN;
case PERIPH_MCPWM0_MODULE:
return PCR_PWM_RST_EN;
case PERIPH_AES_MODULE:
if (enable == true) {
// Clear reset on digital signature, otherwise AES unit is held in reset also.
@ -210,6 +214,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return PCR_TWAI1_CONF_REG;
case PERIPH_GDMA_MODULE:
return PCR_GDMA_CONF_REG;
case PERIPH_MCPWM0_MODULE:
return PCR_PWM_CONF_REG;
case PERIPH_AES_MODULE:
return PCR_AES_CONF_REG;
case PERIPH_SHA_MODULE:
@ -262,6 +268,8 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return PCR_TWAI1_CONF_REG;
case PERIPH_GDMA_MODULE:
return PCR_GDMA_CONF_REG;
case PERIPH_MCPWM0_MODULE:
return PCR_PWM_CONF_REG;
case PERIPH_AES_MODULE:
return PCR_AES_CONF_REG;
case PERIPH_SHA_MODULE:

1649
components/hal/esp32c6/include/hal/mcpwm_ll.h Normal file
View File

File diff suppressed because it is too large Load Diff

26
components/hal/esp32s3/include/hal/mcpwm_ll.h
View File

@ -63,6 +63,32 @@ typedef enum {
////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
/**
* @brief Set the clock source for MCPWM
*
* @param mcpwm Peripheral instance address
* @param clk_src Clock source for the MCPWM peripheral
*/
static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, mcpwm_timer_clock_source_t clk_src)
{
(void)mcpwm;
(void)clk_src;
}
/**
* @brief Enable MCPWM module clock
*
* @note Not support to enable/disable the peripheral clock
*
* @param mcpwm Peripheral instance address
* @param en true to enable, false to disable
*/
static inline void mcpwm_ll_group_enable_clock(mcpwm_dev_t *mcpwm, bool en)
{
(void)mcpwm; // only one MCPWM instance
(void)en;
}
/**
* @brief Set the MCPWM group clock prescale
*

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@ -431,6 +431,10 @@ config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_CLK_SUPPORT_PLL160M
bool
default y
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n

2
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@ -228,7 +228,7 @@ typedef enum {
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< SElect APB as the default clock choice */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
///////////////////////////////////////////////////I2S//////////////////////////////////////////////////////////////////

1
components/soc/esp32/include/soc/soc_caps.h
View File

@ -229,6 +229,7 @@
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_CLK_SUPPORT_PLL160M (1) ///< Support PLL160M as clock source
/*-------------------------- MPU CAPS ----------------------------------------*/
//TODO: correct the caller and remove unsupported lines

1
components/soc/esp32c6/CMakeLists.txt
View File

@ -8,6 +8,7 @@ set(srcs
"spi_periph.c"
"ledc_periph.c"
"pcnt_periph.c"
"mcpwm_periph.c"
"rmt_periph.c"
"i2s_periph.c"
"i2c_periph.c"

64
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -15,6 +15,10 @@ config SOC_PCNT_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
@ -435,6 +439,66 @@ config SOC_RMT_SUPPORT_APB
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MCPWM_CLK_SUPPORT_PLL160M
bool
default y
config SOC_MCPWM_CLK_SUPPORT_XTAL
bool
default y
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128

38
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@ -219,6 +219,44 @@ typedef enum {
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if CONFIG_IDF_ENV_FPGA
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#else
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#endif
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if CONFIG_IDF_ENV_FPGA
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#else
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#endif
} soc_periph_mcpwm_capture_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**

2
components/soc/esp32c6/include/soc/mcpwm_struct.h
View File

@ -1683,7 +1683,7 @@ typedef struct mcpwm_dev_t {
volatile mcpwm_version_reg_t version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM;
extern mcpwm_dev_t MCPWM0;
#ifndef __cplusplus
_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure");

3
components/soc/esp32c6/include/soc/periph_defs.h
View File

@ -38,6 +38,7 @@ typedef enum {
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_MODULE_MAX
@ -105,7 +106,7 @@ typedef enum {
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_PWM_INTR_SOURCE,
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,

18
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -29,6 +29,7 @@
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-5313
#define SOC_BT_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
@ -235,6 +236,23 @@
#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
#define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_CLK_SUPPORT_PLL160M (1) ///< Support PLL160M as clock source
#define SOC_MCPWM_CLK_SUPPORT_XTAL (1) ///< Support XTAL as clock source
// TODO: IDF-5348 (Copy from esp32c3, need check)
/*-------------------------- RTC CAPS --------------------------------------*/
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)

2
components/soc/esp32c6/ld/esp32c6.peripherals.ld
View File

@ -27,7 +27,7 @@ PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( ATOMIC_LOCKER = 0x60011000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM = 0x60014000 );
PROVIDE ( MCPWM0 = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( HINF = 0x60016000 );
PROVIDE ( SLC = 0x60017000 );

83
components/soc/esp32c6/mcpwm_periph.c Normal file
View File

@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_MCPWM0_MODULE,
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
}
};

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -507,6 +507,10 @@ config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_CLK_SUPPORT_PLL160M
bool
default y
config SOC_PCNT_GROUPS
int
default 1

2
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@ -244,7 +244,7 @@ typedef enum {
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< SElect APB as the default clock choice */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////

1
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -207,6 +207,7 @@
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_CLK_SUPPORT_PLL160M (1) ///< Support PLL160M as clock source
/*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h"