mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat: add APM support for ESP32C5
This commit is contained in:
Sachin Billore
parent
f5e9ccbce1
commit
f92afd85cd
@ -16,12 +16,6 @@
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#include "hal/apm_hal.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
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#include "soc/hp_apm_reg.h"
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#include "soc/lp_apm_reg.h"
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#include "soc/lp_apm0_reg.h"
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#endif
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void bootloader_init_mem(void)
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{
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@ -38,13 +32,6 @@ void bootloader_init_mem(void)
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#endif
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#endif
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#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
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// disable apm filter
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REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
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REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
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REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
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#endif
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#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
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// protect memory region
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esp_cpu_configure_region_protection();
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472
components/hal/esp32c5/include/hal/apm_ll.h
Normal file
472
components/hal/esp32c5/include/hal/apm_ll.h
Normal file
@ -0,0 +1,472 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "soc/pcr_reg.h"
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#include "soc/tee_reg.h"
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#include "soc/lp_tee_reg.h"
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#include "soc/lp_apm0_reg.h"
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#include "soc/hp_apm_reg.h"
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#include "soc/lp_apm_reg.h"
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#include "soc/interrupts.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU
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#define APM_LL_CTRL_EXCEPTION_ID_S 18
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#define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU
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#define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U
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#define APM_LL_CTRL_EXCEPTION_MODE_S 16
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#define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U
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#define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU
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#define APM_LL_CTRL_EXCEPTION_REGION_S 0
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#define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU
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#define APM_LL_HP_MAX_REGION_NUM 15
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#define APM_LL_LP_MAX_REGION_NUM 3
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#define APM_LL_MASTER_MAX 32
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#define LP_APM0_MAX_ACCESS_PATH 0x1
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#define HP_APM_MAX_ACCESS_PATH 0x4
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#define LP_APM_MAX_ACCESS_PATH 0x2
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#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION_FILTER_EN_REG) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION_FILTER_EN_REG) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : 0)); \
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})
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#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
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#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : 0)); \
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})
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#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : 0)); \
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})
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#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ATTR_REG + 0xC * (regn_num)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : 0)); \
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})
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#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0)); \
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})
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#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0))
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#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : 0)); \
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})
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#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : 0)); \
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})
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#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0)); \
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})
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#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : 0)); \
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})
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#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
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#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U
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#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
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#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_INT_EN_REG) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_INT_EN_REG) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) : 0)); \
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})
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#define APM_CTRL_CLK_EN (BIT(0))
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#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_CLOCK_GATE_REG) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_CLOCK_GATE_REG) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : 0)); \
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})
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#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \
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({\
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(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_FUNC_CTRL_REG) : \
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((HP_APM_CTRL == apm_ctrl) ? (HP_APM_FUNC_CTRL_REG) : \
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((LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : 0)); \
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})
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/**
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* @brief APM Master ID
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*/
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typedef enum {
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APM_LL_MASTER_HPCORE = 0,
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APM_LL_MASTER_LPCORE = 1,
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APM_LL_MASTER_REGDMA = 2,
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APM_LL_MASTER_SDIOSLV = 3,
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APM_LL_MASTER_MODEM = 4,
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APM_LL_MASTER_MEM_MONITOR = 5,
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APM_LL_MASTER_TRACE = 6,
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APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID
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APM_LL_MASTER_GDMA_SPI2 = 16,
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APM_LL_MASTER_GDMA_UHCI0 = 18,
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APM_LL_MASTER_GDMA_I2S0 = 19,
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APM_LL_MASTER_GDMA_AES = 22,
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APM_LL_MASTER_GDMA_SHA = 23,
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APM_LL_MASTER_GDMA_ADC = 24,
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APM_LL_MASTER_GDMA_PARLIO = 25,
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} apm_ll_master_id_t;
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/**
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* @brief APM Controller
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*/
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typedef enum {
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LP_APM0_CTRL = 0,
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HP_APM_CTRL = 1,
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LP_APM_CTRL = 2,
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} apm_ll_apm_ctrl_t;
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/**
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* @brief APM Secure Mode
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*/
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typedef enum {
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APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */
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APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */
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APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */
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APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */
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} apm_ll_secure_mode_t;
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/**
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* @brief APM Ctrl access path
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*/
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typedef enum {
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APM_CTRL_ACCESS_PATH_M0 = 0x0,
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APM_CTRL_ACCESS_PATH_M1 = 0x1,
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APM_CTRL_ACCESS_PATH_M2 = 0x2,
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APM_CTRL_ACCESS_PATH_M3 = 0x3,
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APM_CTRL_ACCESS_PATH_M4 = 0x4,
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} apm_ll_ctrl_access_path_t;
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/**
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* @brief APM Ctrl path.
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*/
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typedef struct {
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apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */
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apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */
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} apm_ctrl_path_t;
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/**
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* @brief APM exception information
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*/
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typedef struct {
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apm_ctrl_path_t apm_path;
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uint8_t excp_regn;
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uint8_t excp_mode;
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uint8_t excp_id;
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uint8_t excp_type;
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uint32_t excp_addr;
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} apm_ctrl_exception_info_t;
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/**
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* @brief Set secure mode
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param master_id APM master ID
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* @param sec_mode Secure mode
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*/
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static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
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apm_ll_secure_mode_t sec_mode)
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{
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if (apm_ctrl == HP_APM_CTRL) {
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REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
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} else if ((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) {
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REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, sec_mode);
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}
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}
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/**
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* @brief TEE controller clock auto gating enable
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*
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* @param enable Flag for HP clock auto gating enable/disable
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*/
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static inline void apm_tee_ll_clk_gating_enable(bool enable)
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{
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if (enable) {
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REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
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} else {
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REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
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}
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}
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/**
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* @brief enable/disable APM Ctrl Region access permission filter
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param regn_num Memory Region number
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* @param enable Flag for Region access filter enable/disable
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*/
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static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
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uint32_t regn_num, bool enable)
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{
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if (enable) {
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REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
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} else {
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REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
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}
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}
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/**
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* @brief enable/disable APM Ctrl access path(M[0:n])
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param apm_m_path APM Ctrl access path
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* @param enable Flag for LP APM0 M path filter enable/disable
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*/
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static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
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apm_ll_ctrl_access_path_t apm_m_path, bool enable)
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{
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HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
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((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
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((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
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);
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if (enable) {
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REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
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} else {
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REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
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}
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}
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/**
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* @brief APM Ctrl Region start address configuration
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param regn_num Region number to be configured
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* @param addr Region start address
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*/
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static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl,
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uint32_t regn_num, uint32_t addr)
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{
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HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
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((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
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);
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REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr);
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}
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/**
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* @brief APM Ctrl Region end address configuration
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param regn_num Region number to be configured
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* @param addr Region end address
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*/
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static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl,
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uint32_t regn_num, uint32_t addr)
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{
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HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
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((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
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);
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REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr);
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}
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/**
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* @brief HP Region pms attributes configuration
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*
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* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
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* @param regn_num Region number to be configured
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* @param sec_mode Secure mode of the Master
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* @param regn_pms XWR permissions for the given secure mode and Region number
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*/
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static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl,
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uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
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{
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HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
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((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
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);
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uint32_t val = 0;
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val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num));
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val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode);
|
||||
val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
|
||||
REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get APM Ctrl access path(M[0:n]) exception status
|
||||
*
|
||||
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
|
||||
* @param apm_m_path APM Ctrl access path
|
||||
*/
|
||||
static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl,
|
||||
apm_ll_ctrl_access_path_t apm_m_path)
|
||||
{
|
||||
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
|
||||
);
|
||||
|
||||
return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear APM Ctrl access path(M[0:n]) exception
|
||||
*
|
||||
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
|
||||
* @param amp_m_path APM Ctrl access path
|
||||
*/
|
||||
static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl,
|
||||
apm_ll_ctrl_access_path_t apm_m_path)
|
||||
{
|
||||
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
|
||||
);
|
||||
|
||||
REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path),
|
||||
APM_CTRL_M_REGION_STATUS_CLR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get APM Ctrl access path(M[0:n]) exception information
|
||||
*
|
||||
* @param excp_info Exception related information like addr,
|
||||
* region, apm_ctrl, apm_m_path, sec_mode and master id
|
||||
*/
|
||||
static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
|
||||
{
|
||||
HAL_ASSERT(((excp_info->apm_path.apm_ctrl == LP_APM0_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
|
||||
((excp_info->apm_path.apm_ctrl == HP_APM_CTRL) && (excp_info->apm_path.apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
|
||||
((excp_info->apm_path.apm_ctrl == LP_APM_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM_MAX_ACCESS_PATH))
|
||||
);
|
||||
|
||||
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
|
||||
APM_LL_CTRL_EXCEPTION_ID);
|
||||
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
|
||||
APM_LL_CTRL_EXCEPTION_MODE);
|
||||
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
|
||||
APM_LL_CTRL_EXCEPTION_REGION);
|
||||
excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path);
|
||||
excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Interrupt enable for APM Ctrl at access path(M[0:n])
|
||||
*
|
||||
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
|
||||
* @param apm_m_path APM Ctrl access patch(M[0:n])
|
||||
* @param enable Flag for access path interrupt enable/disable
|
||||
*/
|
||||
static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl,
|
||||
apm_ll_ctrl_access_path_t apm_m_path, bool enable)
|
||||
{
|
||||
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
|
||||
);
|
||||
|
||||
if (enable) {
|
||||
REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
|
||||
} else {
|
||||
REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief APM Ctrl clock auto gating enable
|
||||
*
|
||||
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
|
||||
* @param enable Flag for HP clock auto gating enable/disable
|
||||
*/
|
||||
static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
|
||||
} else {
|
||||
REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief APM/TEE/HP System Reg reset event bypass enable
|
||||
*
|
||||
* Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
|
||||
* but also some reset events.
|
||||
* Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
|
||||
* Some reset events will be bypassed.
|
||||
*
|
||||
* @param enable Flag for event bypass enable/disable
|
||||
*/
|
||||
static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
|
||||
} else {
|
||||
REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return APM Ctrl interrupt source number.
|
||||
*
|
||||
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
|
||||
* @param apm_m_path APM Ctrl access patch(M[0:n])
|
||||
*/
|
||||
static inline esp_err_t apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path)
|
||||
{
|
||||
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
|
||||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
|
||||
);
|
||||
|
||||
switch (apm_ctrl) {
|
||||
case LP_APM0_CTRL :
|
||||
return (ETS_LP_APM0_INTR_SOURCE);
|
||||
case HP_APM_CTRL :
|
||||
return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path);
|
||||
case LP_APM_CTRL :
|
||||
return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -131,6 +131,14 @@ config SOC_SECURE_BOOT_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APM_CTRL_FILTER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PMU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -57,7 +57,8 @@
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1
|
||||
#define SOC_SECURE_BOOT_SUPPORTED 1
|
||||
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
|
||||
#define SOC_APM_SUPPORTED 1
|
||||
#define SOC_APM_CTRL_FILTER_SUPPORTED 1
|
||||
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
|
||||
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
|
||||
#define SOC_LP_TIMER_SUPPORTED 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user