From d4ca7c246e224d5a383bef6f4b75b29f590e13f1 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Wed, 3 Jan 2024 16:48:13 +0100 Subject: [PATCH] fix(freertos): Fixed incorrect int level restoration on esp32p4 This commit fixes a bug where in the portENABLE_INTERRUPTS() macro incorrectly restored the interrupt level to 1 (non-CLIC controller). --- .../portable/riscv/include/freertos/portmacro.h | 4 ++-- .../freertos/FreeRTOS-Kernel/portable/riscv/port.c | 8 ++------ components/riscv/include/riscv/rv_utils.h | 10 +++++++++- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h index b4405606d2..ebb5f396cd 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: MIT * - * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -466,7 +466,7 @@ void vPortTCBPreDeleteHook( void *pxTCB ); // --------------------- Interrupts ------------------------ #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK_FROM_ISR() -#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK_FROM_ISR(1) +#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK_FROM_ISR(RVHAL_INTR_ENABLE_THRESH) /** * ISR versions to enable/disable interrupts diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index 5e30219b19..cb6ace1700 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: MIT * - * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -144,11 +144,7 @@ BaseType_t xPortStartScheduler(void) /* Setup the hardware to generate the tick. */ vPortSetupTimer(); -#if !SOC_INT_CLIC_SUPPORTED - esprv_intc_int_set_threshold(1); /* set global INTC masking level */ -#else - esprv_intc_int_set_threshold(0); /* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */ -#endif /* !SOC_INT_CLIC_SUPPORTED */ + esprv_intc_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */ rv_utils_intr_global_enable(); vPortYield(); diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index 9048f52785..b2906739f6 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,6 +43,14 @@ extern "C" { and spinlocks */ #define RVHAL_EXCM_LEVEL 4 +/* SW defined interrupt threshold level to allow all interrupts */ +#if SOC_INT_CLIC_SUPPORTED +/* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */ +#define RVHAL_INTR_ENABLE_THRESH 0 +#else +#define RVHAL_INTR_ENABLE_THRESH 1 +#endif /* SOC_INT_CLIC_SUPPORTED */ + /* --------------------------------------------------- CPU Control ----------------------------------------------------- * * ------------------------------------------------------------------------------------------------------------------ */