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mcpwm: clean up hal driver and add doc

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This commit is contained in:
morris 2022-05-28 16:59:59 +08:00
parent 2d08431433
commit f7ff7ac4d0
18 changed files with 2733 additions and 1418 deletions
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158
components/driver/mcpwm.c
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@ -187,7 +187,7 @@ esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
MCPWM_TIMER_CHECK(mcpwm_num, timer_num);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_timer_set_execute_command(context[mcpwm_num].hal.dev, timer_num, MCPWM_TIMER_START_NO_STOP);
mcpwm_ll_timer_set_start_stop_command(context[mcpwm_num].hal.dev, timer_num, MCPWM_TIMER_START_NO_STOP);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
}
@ -197,7 +197,7 @@ esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
MCPWM_TIMER_CHECK(mcpwm_num, timer_num);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_timer_set_execute_command(context[mcpwm_num].hal.dev, timer_num, MCPWM_TIMER_STOP_AT_ZERO);
mcpwm_ll_timer_set_start_stop_command(context[mcpwm_num].hal.dev, timer_num, MCPWM_TIMER_STOP_EMPTY);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
}
@ -307,63 +307,63 @@ esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, m
switch (mcpwm_ll_timer_get_count_mode(hal->dev, timer_num)) {
case MCPWM_TIMER_COUNT_MODE_UP:
if (duty_type == MCPWM_DUTY_MODE_0) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_GEN_ACTION_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_GEN_ACTION_KEEP);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_KEEP);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_DUTY_MODE_1) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_GEN_ACTION_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_HIGH);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_LOW) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_HIGH);
}
break;
case MCPWM_TIMER_COUNT_MODE_DOWN:
if (duty_type == MCPWM_DUTY_MODE_0) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_HIGH);
} else if (duty_type == MCPWM_DUTY_MODE_1) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_NO_CHANGE);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_LOW) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_HIGH);
}
break;
case MCPWM_TIMER_COUNT_MODE_UP_DOWN:
if (duty_type == MCPWM_DUTY_MODE_0) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_HIGH);
} else if (duty_type == MCPWM_DUTY_MODE_1) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_LOW) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_LOW);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_LOW);
} else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) {
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_timer_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_DOWN, gen, MCPWM_ACTION_FORCE_HIGH);
mcpwm_ll_generator_set_action_on_compare_event(hal->dev, op, gen, MCPWM_TIMER_DIRECTION_UP, gen, MCPWM_ACTION_FORCE_HIGH);
}
@ -382,14 +382,12 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module);
mcpwm_hal_init_config_t config = {
.host_id = mcpwm_num
.group_id = mcpwm_num
};
mcpwm_hal_init(hal, &config);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_group_set_clock_prescale(hal->dev, context[mcpwm_num].group_pre_scale);
mcpwm_ll_group_enable_shadow_mode(hal->dev);
mcpwm_ll_group_flush_shadow(hal->dev);
mcpwm_ll_timer_set_clock_prescale(hal->dev, timer_num, context[mcpwm_num].timer_pre_scale[timer_num]);
mcpwm_ll_timer_set_count_mode(hal->dev, timer_num, mcpwm_conf->counter_mode);
mcpwm_ll_timer_update_period_at_once(hal->dev, timer_num);
@ -397,7 +395,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
unsigned long int real_timer_clk_hz =
SOC_MCPWM_BASE_CLK_HZ / real_group_prescale / mcpwm_ll_timer_get_clock_prescale(hal->dev, timer_num);
mcpwm_ll_timer_set_peak(hal->dev, timer_num, real_timer_clk_hz / mcpwm_conf->frequency, false);
mcpwm_ll_operator_select_timer(hal->dev, timer_num, timer_num); //the driver currently always use the timer x for operator x
mcpwm_ll_operator_connect_timer(hal->dev, timer_num, timer_num); //the driver currently always use the timer x for operator x
mcpwm_critical_exit(mcpwm_num);
mcpwm_set_duty(mcpwm_num, timer_num, 0, mcpwm_conf->cmpr_a);
@ -516,7 +514,7 @@ esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_
MCPWM_TIMER_CHECK(mcpwm_num, timer_num);
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_carrier_set_oneshot_width(context[mcpwm_num].hal.dev, op, pulse_width + 1);
mcpwm_ll_carrier_set_first_pulse_width(context[mcpwm_num].hal.dev, op, pulse_width + 1);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
}
@ -575,7 +573,7 @@ esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_deadtime_enable_update_delay_on_tez(hal->dev, op, true);
// The dead time delay unit equals to MCPWM group resolution
mcpwm_ll_deadtime_resolution_to_timer(hal->dev, op, false);
mcpwm_ll_operator_set_deadtime_clock_src(hal->dev, op, MCPWM_LL_DEADTIME_CLK_SRC_GROUP);
mcpwm_ll_deadtime_set_rising_delay(hal->dev, op, red + 1);
mcpwm_ll_deadtime_set_falling_delay(hal->dev, op, fed + 1);
switch (dt_mode) {
@ -691,7 +689,7 @@ esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_fault_enable_detection(hal->dev, fault_sig, false);
for (int i = 0; i < SOC_MCPWM_OPERATORS_PER_GROUP; i++) {
mcpwm_ll_fault_clear_ost(hal->dev, i); // make sure operator has exit the ost fault state totally
mcpwm_ll_brake_clear_ost(hal->dev, i); // make sure operator has exit the ost fault state totally
}
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
@ -706,13 +704,13 @@ esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_n
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_fault_enable_cbc_mode(hal->dev, op, fault_sig, true);
mcpwm_ll_fault_enable_cbc_refresh_on_tez(hal->dev, op, true);
mcpwm_ll_fault_enable_oneshot_mode(hal->dev, op, fault_sig, false);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TRIP_TYPE_CBC, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_UP, MCPWM_TRIP_TYPE_CBC, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TRIP_TYPE_CBC, action_on_pwmxb);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_UP, MCPWM_TRIP_TYPE_CBC, action_on_pwmxb);
mcpwm_ll_brake_enable_cbc_mode(hal->dev, op, fault_sig, true);
mcpwm_ll_brake_enable_cbc_refresh_on_tez(hal->dev, op, true);
mcpwm_ll_brake_enable_oneshot_mode(hal->dev, op, fault_sig, false);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_OPER_BRAKE_MODE_CBC, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_OPER_BRAKE_MODE_CBC, action_on_pwmxb);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, action_on_pwmxb);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
}
@ -726,18 +724,19 @@ esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_fault_clear_ost(hal->dev, op);
mcpwm_ll_fault_enable_oneshot_mode(hal->dev, op, fault_sig, true);
mcpwm_ll_fault_enable_cbc_mode(hal->dev, op, fault_sig, false);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TRIP_TYPE_OST, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_UP, MCPWM_TRIP_TYPE_OST, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TRIP_TYPE_OST, action_on_pwmxb);
mcpwm_ll_generator_set_action_on_trip_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_UP, MCPWM_TRIP_TYPE_OST, action_on_pwmxb);
mcpwm_ll_brake_clear_ost(hal->dev, op);
mcpwm_ll_brake_enable_oneshot_mode(hal->dev, op, fault_sig, true);
mcpwm_ll_brake_enable_cbc_mode(hal->dev, op, fault_sig, false);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_OPER_BRAKE_MODE_OST, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 0, MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, action_on_pwmxa);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_DOWN, MCPWM_OPER_BRAKE_MODE_OST, action_on_pwmxb);
mcpwm_ll_generator_set_action_on_brake_event(hal->dev, op, 1, MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, action_on_pwmxb);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
}
static void MCPWM_ISR_ATTR mcpwm_default_isr_handler(void *arg) {
static void MCPWM_ISR_ATTR mcpwm_default_isr_handler(void *arg)
{
mcpwm_context_t *curr_context = (mcpwm_context_t *) arg;
uint32_t intr_status = mcpwm_ll_intr_get_capture_status(curr_context->hal.dev);
mcpwm_ll_intr_clear_capture_status(curr_context->hal.dev, intr_status);
@ -746,11 +745,11 @@ static void MCPWM_ISR_ATTR mcpwm_default_isr_handler(void *arg) {
if ((intr_status >> i) & 0x1) {
if (curr_context->cap_isr_func[i].fn != NULL) {
cap_event_data_t edata;
edata.cap_edge = mcpwm_ll_capture_is_negedge(curr_context->hal.dev, i) ? MCPWM_NEG_EDGE
: MCPWM_POS_EDGE;
edata.cap_edge = mcpwm_ll_capture_get_edge(curr_context->hal.dev, i) == MCPWM_CAP_EDGE_NEG ? MCPWM_NEG_EDGE
: MCPWM_POS_EDGE;
edata.cap_value = mcpwm_ll_capture_get_value(curr_context->hal.dev, i);
if (curr_context->cap_isr_func[i].fn(curr_context->group_id, i, &edata,
curr_context->cap_isr_func[i].args)) {
curr_context->cap_isr_func[i].args)) {
need_yield = true;
}
}
@ -773,7 +772,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module);
mcpwm_hal_init_config_t init_config = {
.host_id = mcpwm_num
.group_id = mcpwm_num
};
mcpwm_hal_init(hal, &init_config);
mcpwm_critical_enter(mcpwm_num);
@ -784,7 +783,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
mcpwm_ll_capture_enable_posedge(hal->dev, cap_channel, cap_conf->cap_edge & MCPWM_POS_EDGE);
mcpwm_ll_capture_set_prescale(hal->dev, cap_channel, cap_conf->cap_prescale);
// capture feature should be used with interupt, so enable it by default
mcpwm_ll_intr_enable_capture(hal->dev, cap_channel, true);
mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_channel), true);
mcpwm_ll_intr_clear_capture_status(hal->dev, 1 << cap_channel);
mcpwm_critical_exit(mcpwm_num);
@ -794,8 +793,8 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
esp_err_t ret = ESP_OK;
if (context[mcpwm_num].mcpwm_intr_handle == NULL) {
ret = esp_intr_alloc(mcpwm_periph_signals.groups[mcpwm_num].irq_id, MCPWM_INTR_FLAG,
mcpwm_default_isr_handler,
(void *) (context + mcpwm_num), &(context[mcpwm_num].mcpwm_intr_handle));
mcpwm_default_isr_handler,
(void *) (context + mcpwm_num), &(context[mcpwm_num].mcpwm_intr_handle));
}
mcpwm_mutex_unlock(mcpwm_num);
@ -811,7 +810,7 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_capture_enable_channel(hal->dev, cap_channel, false);
mcpwm_ll_intr_enable_capture(hal->dev, cap_channel, false);
mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_channel), false);
mcpwm_critical_exit(mcpwm_num);
mcpwm_mutex_lock(mcpwm_num);
@ -828,7 +827,7 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch
esp_err_t ret = ESP_OK;
if (should_free_handle) {
ret = esp_intr_free(context[mcpwm_num].mcpwm_intr_handle);
if (ret != ESP_OK){
if (ret != ESP_OK) {
ESP_LOGE(TAG, "failed to free interrupt handle");
}
context[mcpwm_num].mcpwm_intr_handle = NULL;
@ -853,7 +852,7 @@ uint32_t MCPWM_ISR_ATTR mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mc
ESP_RETURN_ON_FALSE(mcpwm_num < SOC_MCPWM_GROUPS, ESP_ERR_INVALID_ARG, TAG, MCPWM_GROUP_NUM_ERROR);
ESP_RETURN_ON_FALSE(cap_sig < SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER, ESP_ERR_INVALID_ARG, TAG, MCPWM_CAPTURE_ERROR);
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
return mcpwm_ll_capture_is_negedge(hal->dev, cap_sig) ? 2 : 1;
return mcpwm_ll_capture_get_edge(hal->dev, cap_sig) == MCPWM_CAP_EDGE_NEG ? 2 : 1;
}
esp_err_t mcpwm_sync_configure(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_sync_config_t *sync_conf)
@ -868,12 +867,12 @@ esp_err_t mcpwm_sync_configure(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
uint32_t set_phase = 0;
set_phase = mcpwm_ll_timer_get_peak(hal->dev, timer_num, false) * sync_conf->timer_val / 1000;
mcpwm_ll_timer_set_sync_phase_value(hal->dev, timer_num, set_phase);
if (sync_conf->sync_sig == MCPWM_SELECT_NO_INPUT){
mcpwm_ll_timer_set_soft_synchro(hal->dev, timer_num);
if (sync_conf->sync_sig == MCPWM_SELECT_NO_INPUT) {
mcpwm_ll_timer_clear_sync_input(hal->dev, timer_num);
} else if (sync_conf->sync_sig <= MCPWM_SELECT_TIMER2_SYNC) {
mcpwm_ll_timer_set_timer_synchro(hal->dev, timer_num, sync_conf->sync_sig - MCPWM_SELECT_TIMER0_SYNC);
mcpwm_ll_timer_set_timer_sync_input(hal->dev, timer_num, sync_conf->sync_sig - MCPWM_SELECT_TIMER0_SYNC);
} else {
mcpwm_ll_timer_set_gpio_synchro(hal->dev, timer_num, sync_conf->sync_sig - MCPWM_SELECT_GPIO_SYNC0);
mcpwm_ll_timer_set_gpio_sync_input(hal->dev, timer_num, sync_conf->sync_sig - MCPWM_SELECT_GPIO_SYNC0);
}
mcpwm_ll_timer_enable_sync_input(hal->dev, timer_num, true);
mcpwm_critical_exit(mcpwm_num);
@ -903,13 +902,14 @@ esp_err_t mcpwm_timer_trigger_soft_sync(mcpwm_unit_t mcpwm_num, mcpwm_timer_t ti
return ESP_OK;
}
esp_err_t mcpwm_sync_invert_gpio_synchro(mcpwm_unit_t mcpwm_num, mcpwm_sync_signal_t sync_sig, bool invert){
esp_err_t mcpwm_sync_invert_gpio_synchro(mcpwm_unit_t mcpwm_num, mcpwm_sync_signal_t sync_sig, bool invert)
{
ESP_RETURN_ON_FALSE(sync_sig >= MCPWM_SELECT_GPIO_SYNC0 && sync_sig <= MCPWM_SELECT_GPIO_SYNC2,
ESP_ERR_INVALID_ARG, TAG, "invalid sync sig");
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
mcpwm_critical_enter(mcpwm_num);
mcpwm_ll_invert_gpio_synchro(hal->dev, sync_sig - MCPWM_SELECT_GPIO_SYNC0, invert);
mcpwm_ll_invert_gpio_sync_input(hal->dev, sync_sig - MCPWM_SELECT_GPIO_SYNC0, invert);
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;
@ -922,19 +922,19 @@ esp_err_t mcpwm_set_timer_sync_output(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
mcpwm_critical_enter(mcpwm_num);
switch (trigger) {
case MCPWM_SWSYNC_SOURCE_SYNCIN:
mcpwm_ll_timer_sync_out_penetrate(hal->dev, timer_num);
break;
case MCPWM_SWSYNC_SOURCE_TEZ:
mcpwm_ll_timer_sync_out_on_timer_event(hal->dev, timer_num, MCPWM_TIMER_EVENT_ZERO);
break;
case MCPWM_SWSYNC_SOURCE_TEP:
mcpwm_ll_timer_sync_out_on_timer_event(hal->dev, timer_num, MCPWM_TIMER_EVENT_PEAK);
break;
case MCPWM_SWSYNC_SOURCE_DISABLED:
default:
mcpwm_ll_timer_disable_sync_out(hal->dev, timer_num);
break;
case MCPWM_SWSYNC_SOURCE_SYNCIN:
mcpwm_ll_timer_propagate_input_sync(hal->dev, timer_num);
break;
case MCPWM_SWSYNC_SOURCE_TEZ:
mcpwm_ll_timer_sync_out_on_timer_event(hal->dev, timer_num, MCPWM_TIMER_EVENT_EMPTY);
break;
case MCPWM_SWSYNC_SOURCE_TEP:
mcpwm_ll_timer_sync_out_on_timer_event(hal->dev, timer_num, MCPWM_TIMER_EVENT_FULL);
break;
case MCPWM_SWSYNC_SOURCE_DISABLED:
default:
mcpwm_ll_timer_disable_sync_out(hal->dev, timer_num);
break;
}
mcpwm_critical_exit(mcpwm_num);
return ESP_OK;

2321
components/hal/esp32/include/hal/mcpwm_ll.h
View File

File diff suppressed because it is too large Load Diff

1311
components/hal/esp32s3/include/hal/mcpwm_ll.h
View File

File diff suppressed because it is too large Load Diff

74
components/hal/include/hal/mcpwm_hal.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
@ -18,18 +10,28 @@
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for MCPWM (common part)
#pragma once
#include "soc/mcpwm_struct.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct mcpwm_dev_t *mcpwm_soc_handle_t; // MCPWM SOC layer handle
/**
* @brief HAL layer configuration
*/
typedef struct {
int host_id; ///< Which MCPWM peripheral to use, 0-1.
int group_id; // Indicate the MCPWM hardware group
} mcpwm_hal_init_config_t;
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
mcpwm_dev_t *dev; ///< Beginning address of the peripheral registers of a single MCPWM unit. Call `mcpwm_hal_init` to initialize it.
mcpwm_soc_handle_t dev; // MCPWM SOC layer handle
} mcpwm_hal_context_t;
/**
@ -39,3 +41,39 @@ typedef struct {
* @param init_config Configuration for the HAL to be used only once.
*/
void mcpwm_hal_init(mcpwm_hal_context_t *hal, const mcpwm_hal_init_config_t *init_config);
/**
* @brief Deinitialize the HAL driver.
*
* @param hal Context of the HAL layer.
*/
void mcpwm_hal_deinit(mcpwm_hal_context_t *hal);
/**
* @brief Reset MCPWM timer
*
* @param hal Context of the HAL layer.
* @param timer_id Timer ID
*/
void mcpwm_hal_timer_reset(mcpwm_hal_context_t *hal, int timer_id);
/**
* @brief Reset MCPWM operator
*
* @param hal Context of the HAL layer.
* @param oper_id Operator ID
*/
void mcpwm_hal_operator_reset(mcpwm_hal_context_t *hal, int oper_id);
/**
* @brief Reset MCPWM generator
*
* @param hal Context of the HAL layer.
* @param oper_id Operator ID
* @param gen_id Generator ID
*/
void mcpwm_hal_generator_reset(mcpwm_hal_context_t *hal, int oper_id, int gen_id);
#ifdef __cplusplus
}
#endif

88
components/hal/include/hal/mcpwm_types.h
View File

@ -1,29 +1,47 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief MCPWM timer clock source
*/
typedef soc_periph_mcpwm_timer_clk_src_t mcpwm_timer_clock_source_t;
/**
* @brief MCPWM capture clock source
*/
typedef soc_periph_mcpwm_capture_clk_src_t mcpwm_capture_clock_source_t;
/**
* @brief MCPWM timer count direction
*/
typedef enum {
MCPWM_TIMER_DIRECTION_UP, /*!< Counting direction: Increase */
MCPWM_TIMER_DIRECTION_DOWN, /*!< Counting direction: Decrease */
} mcpwm_timer_direction_t;
/**
* @brief MCPWM timer events
*/
typedef enum {
MCPWM_TIMER_EVENT_ZERO, /*!< MCPWM timer counts to zero */
MCPWM_TIMER_EVENT_PEAK, /*!< MCPWM timer counts to peak */
MCPWM_TIMER_EVENT_EMPTY, /*!< MCPWM timer counts to zero (i.e. counter is empty) */
MCPWM_TIMER_EVENT_FULL, /*!< MCPWM timer counts to peak (i.e. counter is full) */
MCPWM_TIMER_EVENT_INVALID, /*!< MCPWM timer invalid event */
} mcpwm_timer_event_t;
/**
* @brief MCPWM timer count modes
*/
typedef enum {
MCPWM_TIMER_COUNT_MODE_PAUSE, /*!< MCPWM timer paused */
MCPWM_TIMER_COUNT_MODE_UP, /*!< MCPWM timer counting up */
@ -31,14 +49,20 @@ typedef enum {
MCPWM_TIMER_COUNT_MODE_UP_DOWN, /*!< MCPWM timer counting up and down */
} mcpwm_timer_count_mode_t;
/**
* @brief MCPWM timer commands, specify the way to start or stop the timer
*/
typedef enum {
MCPWM_TIMER_STOP_AT_ZERO, /*!< MCPWM timer stops when couting to zero */
MCPWM_TIMER_STOP_AT_PEAK, /*!< MCPWM timer stops when counting to peak */
MCPWM_TIMER_START_NO_STOP, /*!< MCPWM timer starts couting */
MCPWM_TIMER_START_STOP_AT_ZERO, /*!< MCPWM timer starts counting and stops when couting to zero */
MCPWM_TIMER_START_STOP_AT_PEAK, /*!< MCPWM timer starts counting and stops when counting to peak */
} mcpwm_timer_execute_cmd_t;
MCPWM_TIMER_STOP_EMPTY, /*!< MCPWM timer stops when next count reaches zero */
MCPWM_TIMER_STOP_FULL, /*!< MCPWM timer stops when next count reaches peak */
MCPWM_TIMER_START_NO_STOP, /*!< MCPWM timer starts couting, and don't stop until received stop command */
MCPWM_TIMER_START_STOP_EMPTY, /*!< MCPWM timer starts counting and stops when next count reaches zero */
MCPWM_TIMER_START_STOP_FULL, /*!< MCPWM timer starts counting and stops when next count reaches peak */
} mcpwm_timer_start_stop_cmd_t;
/**
* @brief MCPWM generator actions
*/
typedef enum {
MCPWM_GEN_ACTION_KEEP, /*!< Generator action: Keep the same level */
MCPWM_GEN_ACTION_LOW, /*!< Generator action: Force to low level */
@ -46,7 +70,23 @@ typedef enum {
MCPWM_GEN_ACTION_TOGGLE, /*!< Generator action: Toggle level */
} mcpwm_generator_action_t;
/**
* @brief MCPWM operator brake mode
*/
typedef enum {
MCPWM_TRIP_TYPE_CBC, /*!< CBC trip type, shut down the operator cycle by cycle*/
MCPWM_TRIP_TYPE_OST, /*!< OST trip type, shut down the operator in one shot */
} mcpwm_trip_type_t;
MCPWM_OPER_BRAKE_MODE_CBC, /*!< Brake mode: CBC (cycle by cycle)*/
MCPWM_OPER_BRAKE_MODE_OST, /*!< Brake mode, OST (one shot) */
MCPWM_OPER_BRAKE_MODE_INVALID, /*!< MCPWM operator invalid brake mode */
} mcpwm_operator_brake_mode_t;
/**
* @brief MCPWM capture edge
*/
typedef enum {
MCPWM_CAP_EDGE_POS, /*!< Capture on the positive edge */
MCPWM_CAP_EDGE_NEG, /*!< Capture on the negative edge */
} mcpwm_capture_edge_t;
#ifdef __cplusplus
}
#endif

65
components/hal/mcpwm_hal.c
View File

@ -1,23 +1,56 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// The HAL layer for MCPWM (common part)
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include "soc/soc_caps.h"
#include "hal/mcpwm_hal.h"
#include "hal/mcpwm_ll.h"
void mcpwm_hal_init(mcpwm_hal_context_t *hal, const mcpwm_hal_init_config_t *init_config)
{
hal->dev = MCPWM_LL_GET_HW(init_config->host_id);
hal->dev = MCPWM_LL_GET_HW(init_config->group_id);
mcpwm_ll_group_enable_shadow_mode(hal->dev);
mcpwm_ll_group_flush_shadow(hal->dev);
}
void mcpwm_hal_deinit(mcpwm_hal_context_t *hal)
{
hal->dev = NULL;
}
void mcpwm_hal_timer_reset(mcpwm_hal_context_t *hal, int timer_id)
{
mcpwm_ll_timer_set_count_mode(hal->dev, timer_id, MCPWM_TIMER_COUNT_MODE_PAUSE);
mcpwm_ll_timer_update_period_at_once(hal->dev, timer_id);
// disable sync input and output by default
mcpwm_ll_timer_disable_sync_out(hal->dev, timer_id);
mcpwm_ll_timer_enable_sync_input(hal->dev, timer_id, false);
mcpwm_ll_timer_clear_sync_input(hal->dev, timer_id);
}
void mcpwm_hal_operator_reset(mcpwm_hal_context_t *hal, int oper_id)
{
// allow to update action, compare, and dead time configuration
mcpwm_ll_operator_stop_update_action(hal->dev, oper_id, false);
mcpwm_ll_operator_update_action_at_once(hal->dev, oper_id);
mcpwm_ll_deadtime_stop_update_delay(hal->dev, oper_id, false);
mcpwm_ll_deadtime_update_delay_at_once(hal->dev, oper_id);
for (int i = 0; i < SOC_MCPWM_COMPARATORS_PER_OPERATOR; i++) {
mcpwm_ll_operator_stop_update_compare(hal->dev, oper_id, i, false);
mcpwm_ll_operator_update_compare_at_once(hal->dev, oper_id, i);
}
mcpwm_ll_brake_enable_cbc_refresh_on_tez(hal->dev, oper_id, false);
mcpwm_ll_fault_enable_cbc_refresh_on_tep(hal->dev, oper_id, false);
mcpwm_ll_brake_enable_soft_cbc(hal->dev, oper_id, false);
mcpwm_ll_brake_enable_soft_ost(hal->dev, oper_id, false);
}
void mcpwm_hal_generator_reset(mcpwm_hal_context_t *hal, int oper_id, int gen_id)
{
mcpwm_ll_generator_reset_actions(hal->dev, oper_id, gen_id);
mcpwm_ll_gen_disable_continue_force_action(hal->dev, oper_id, gen_id);
mcpwm_ll_gen_disable_noncontinue_force_action(hal->dev, oper_id, gen_id);
}

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@ -387,10 +387,6 @@ config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_BASE_CLK_HZ
int
default 160000000
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n

28
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@ -210,6 +210,34 @@ typedef enum {
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_D2}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (160MHz) as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< SElect APB as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
#ifdef __cplusplus
}
#endif

4
components/soc/esp32/include/soc/mcpwm_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -1435,7 +1435,7 @@ typedef struct {
mcpwm_fh_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
typedef struct mcpwm_dev_t {
volatile mcpwm_clk_cfg_reg_t clk_cfg;
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;

1
components/soc/esp32/include/soc/soc_caps.h
View File

@ -223,7 +223,6 @@
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/
//TODO: correct the caller and remove unsupported lines

18
components/soc/esp32/mcpwm_periph.c
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -451,10 +451,6 @@ config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_BASE_CLK_HZ
int
default 160000000
config SOC_PCNT_GROUPS
bool
default y

28
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@ -217,6 +217,34 @@ typedef enum {
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_D2}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< SElect APB as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
#ifdef __cplusplus
}
#endif

4
components/soc/esp32s3/include/soc/mcpwm_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -1435,7 +1435,7 @@ typedef struct {
mcpwm_fh_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
typedef struct mcpwm_dev_t {
volatile mcpwm_clk_cfg_reg_t clk_cfg;
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;

1
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -185,7 +185,6 @@
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h"

18
components/soc/esp32s3/mcpwm_periph.c
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"

18
components/soc/include/soc/mcpwm_periph.h
View File

@ -1,16 +1,8 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

6
tools/ci/check_copyright_ignore.txt
View File

@ -867,8 +867,6 @@ components/hal/include/hal/ds_hal.h
components/hal/include/hal/esp_flash_err.h
components/hal/include/hal/interrupt_controller_hal.h
components/hal/include/hal/interrupt_controller_types.h
components/hal/include/hal/mcpwm_hal.h
components/hal/include/hal/mcpwm_types.h
components/hal/include/hal/mpu_hal.h
components/hal/include/hal/mpu_types.h
components/hal/include/hal/rtc_io_types.h
@ -889,7 +887,6 @@ components/hal/include/hal/wdt_hal.h
components/hal/include/hal/wdt_types.h
components/hal/interrupt_controller_hal.c
components/hal/ledc_hal_iram.c
components/hal/mcpwm_hal.c
components/hal/mpu_hal.c
components/hal/platform_port/include/hal/assert.h
components/hal/platform_port/include/hal/check.h
@ -1224,7 +1221,6 @@ components/soc/esp32/include/soc/uhci_struct.h
components/soc/esp32/include/soc/wdev_reg.h
components/soc/esp32/interrupts.c
components/soc/esp32/ledc_periph.c
components/soc/esp32/mcpwm_periph.c
components/soc/esp32/sdio_slave_periph.c
components/soc/esp32/sdmmc_periph.c
components/soc/esp32/sigmadelta_periph.c
@ -1502,7 +1498,6 @@ components/soc/esp32s3/include/soc/world_controller_reg.h
components/soc/esp32s3/include/soc/world_controller_struct.h
components/soc/esp32s3/interrupts.c
components/soc/esp32s3/ledc_periph.c
components/soc/esp32s3/mcpwm_periph.c
components/soc/esp32s3/rtc_io_periph.c
components/soc/esp32s3/sdio_slave_periph.c
components/soc/esp32s3/sdmmc_periph.c
@ -1519,7 +1514,6 @@ components/soc/include/soc/gpio_periph.h
components/soc/include/soc/i2c_periph.h
components/soc/include/soc/interrupts.h
components/soc/include/soc/ledc_periph.h
components/soc/include/soc/mcpwm_periph.h
components/soc/include/soc/rtc_cntl_periph.h
components/soc/include/soc/rtc_periph.h
components/soc/include/soc/sdio_slave_periph.h