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Merge branch 'feature/support_chip912_cpll_spll_eco1_v5.3' into 'release/v5.3'

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feat: support(esp32p4_eco1): modify cpll and spll config (v5.3)

See merge request espressif/esp-idf!30783
This commit is contained in:
Michael (XIAO Xufeng) 2024-05-20 00:48:27 +08:00
commit f63e544dc3
4 changed files with 61 additions and 25 deletions
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21
components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,6 +29,7 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/chip_revision.h"
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
@ -90,14 +91,14 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
// regi2c is enabled by default on ESP32P4, do nothing
// On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
// And we are fixing SPLL to be 480MHz at all runtime
// Suppose to fix the issue on ECO1, will check when chip comes back
// TODO: IDF-8939
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
esp_rom_delay_us(100);
unsigned chip_version = efuse_hal_chip_revision();
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
// On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
// And we are fixing SPLL to be 480MHz after app is up
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
esp_rom_delay_us(100);
}
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
}
@ -170,7 +171,7 @@ esp_err_t bootloader_init(void)
}
#endif // !CONFIG_APP_BUILD_TYPE_RAM
// check whether a WDT reset happend
// check whether a WDT reset happened
bootloader_check_wdt_reset();
// config WDT
bootloader_config_wdt();

3
components/esp_hw_support/port/esp32p4/Kconfig.hw_support
View File

@ -11,11 +11,14 @@ choice ESP32P4_REV_MIN
config ESP32P4_REV_MIN_0
bool "Rev v0.0"
config ESP32P4_REV_MIN_1
bool "Rev v0.1"
endchoice
config ESP32P4_REV_MIN_FULL
int
default 0 if ESP32P4_REV_MIN_0
default 1 if ESP32P4_REV_MIN_1
config ESP_REV_MIN_FULL
int

9
components/esp_hw_support/port/esp32p4/pmu_sleep.c
View File

@ -12,6 +12,7 @@
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/chip_revision.h"
#include "soc/soc.h"
#include "soc/regi2c_syspll.h"
#include "soc/regi2c_cpll.h"
@ -27,6 +28,7 @@
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#include "hal/efuse_hal.h"
#define HP(state) (PMU_MODE_HP_ ## state)
#define LP(state) (PMU_MODE_LP_ ## state)
@ -317,8 +319,11 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void)
}
pmu_sleep_shutdown_ldo();
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
unsigned chip_version = efuse_hal_chip_revision();
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
}
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}

53
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@ -9,6 +9,7 @@
#include <stdint.h>
#include "soc/clkout_channel.h"
#include "soc/soc.h"
#include "soc/chip_revision.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
@ -22,6 +23,8 @@
#include "hal/log.h"
#include "esp32p4/rom/rtc.h"
#include "hal/misc.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
@ -309,7 +312,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u
{
uint8_t div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0);
uint8_t ref_div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_REF_DIV);
return xtal_freq_mhz * (div + 4) / (ref_div + 1);
unsigned chip_version = efuse_hal_chip_revision();
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
return xtal_freq_mhz * (div + 4) / (ref_div + 1);
} else
return xtal_freq_mhz * div / (ref_div + 1);
}
/**
@ -339,19 +346,39 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_
// Currently, only supporting 40MHz XTAL
HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
switch (cpll_freq_mhz) {
case CLK_LL_PLL_400M_FREQ_MHZ:
/* Configure 400M CPLL */
div7_0 = 6;
div_ref = 0;
break;
case CLK_LL_PLL_360M_FREQ_MHZ:
default:
/* Configure 360M CPLL */
div7_0 = 5;
div_ref = 0;
break;
unsigned chip_version = efuse_hal_chip_revision();
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
switch (cpll_freq_mhz) {
case CLK_LL_PLL_400M_FREQ_MHZ:
/* Configure 400M CPLL */
div7_0 = 6;
div_ref = 0;
break;
case CLK_LL_PLL_360M_FREQ_MHZ:
default:
/* Configure 360M CPLL */
div7_0 = 5;
div_ref = 0;
break;
}
} else {
/*div7_0 bit2 & bit3 is swapped from ECO1*/
switch (cpll_freq_mhz) {
case CLK_LL_PLL_400M_FREQ_MHZ:
/* Configure 400M CPLL */
div7_0 = 10;
div_ref = 0;
break;
case CLK_LL_PLL_360M_FREQ_MHZ:
default:
/* Configure 360M CPLL */
div7_0 = 9;
div_ref = 0;
break;
}
}
uint8_t i2c_cpll_lref = (oc_enb_fcal << I2C_CPLL_OC_ENB_FCAL_LSB) | (dchgp << I2C_CPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_cpll_div_7_0 = div7_0;
uint8_t i2c_cpll_dcur = (1 << I2C_CPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_CPLL_OC_DHREF_SEL_LSB) | dcur;