diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c
index f11f508710..d7877ca452 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_time.c
@@ -7,6 +7,7 @@
 #include <stdint.h>
 #include "esp32c6/rom/ets_sys.h"
 #include "soc/rtc.h"
+#include "soc/pcr_reg.h"
 #include "hal/lp_timer_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/timer_ll.h"
@@ -154,10 +155,13 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
 
             /*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
               So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times.
-              And ensure that this modification will not affect ECO0.*/
+              And ensure that this modification will not affect ECO0.
+              And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
+              calibration. */
             if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
                 if (cal_clk == RTC_CAL_RC_FAST) {
                     cal_val = cal_val >> 5;
+                    CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
                 }
             }
             break;
@@ -218,6 +222,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
     if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
         if (cal_clk == RTC_CAL_RC_FAST) {
             slowclk_cycles = slowclk_cycles >> 5;
+            SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
         }
     }
 
diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c
index a58e3d6d4a..d8f5826e33 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_time.c
@@ -11,6 +11,7 @@
 #include "hal/clk_tree_ll.h"
 #include "hal/timer_ll.h"
 #include "soc/timer_group_reg.h"
+#include "soc/pcr_reg.h"
 #include "esp_rom_sys.h"
 #include "assert.h"
 #include "hal/efuse_hal.h"
@@ -154,10 +155,13 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
 
             /*The Fosc CLK of calibration circuit is divided by 32 for ECO2.
               So we need to multiply the frequency of the Fosc for ECO2 and above chips by 32 times.
-              And ensure that this modification will not affect ECO0 and ECO1.*/
+              And ensure that this modification will not affect ECO0 and ECO1.
+              And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
+              calibration. */
             if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
                 if (cal_clk == RTC_CAL_RC_FAST) {
                     cal_val = cal_val >> 5;
+                    CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
                 }
             }
             break;
@@ -218,6 +222,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
     if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
         if (cal_clk == RTC_CAL_RC_FAST) {
             slowclk_cycles = slowclk_cycles >> 5;
+            SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index b1d1f75398..ed783cabe3 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -265,6 +265,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
 
         // TODO: Replace with hal implementation
+        REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
         REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
         REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
         REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index fa8965b5db..8218084be0 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -256,6 +256,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE);
 
         // TODO: Replace with hal implementation
+        REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
         REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
         REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
         REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);