mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
uart: format driver code by astyle
This commit is contained in:
morris
SalimTerryLi
parent
c50b102787
commit
f4ccb8e766
@ -51,7 +51,7 @@
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#define XOFF (0x13)
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#define XON (0x11)
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static const char* UART_TAG = "uart";
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static const char *UART_TAG = "uart";
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#define UART_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(UART_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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@ -104,7 +104,7 @@ typedef struct {
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int wr;
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int rd;
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int len;
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int* data;
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int *data;
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} uart_pat_rb_t;
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typedef struct {
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@ -123,8 +123,8 @@ typedef struct {
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RingbufHandle_t rx_ring_buf; /*!< RX ring buffer handler*/
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bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */
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uint32_t rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/
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uint8_t* rx_ptr; /*!< pointer to the current data in ring buffer*/
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uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/
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uint8_t *rx_ptr; /*!< pointer to the current data in ring buffer*/
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uint8_t *rx_head_ptr; /*!< pointer to the head of RX item*/
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uint8_t rx_data_buf[SOC_UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
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uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
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uart_pat_rb_t rx_pattern_pos;
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@ -137,8 +137,8 @@ typedef struct {
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int tx_buf_size; /*!< TX ring buffer size */
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RingbufHandle_t tx_ring_buf; /*!< TX ring buffer handler*/
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bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/
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uint8_t* tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/
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uart_tx_data_t* tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/
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uint8_t *tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/
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uart_tx_data_t *tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/
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uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/
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uint32_t tx_len_cur;
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uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */
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@ -199,16 +199,16 @@ static void uart_module_enable(uart_port_t uart_num)
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if (uart_context[uart_num].hw_enabled != true) {
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periph_module_enable(uart_periph_signal[uart_num].module);
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if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
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// Workaround for ESP32C3: enable core reset
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// before enabling uart module clock
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// to prevent uart output garbage value.
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#if SOC_UART_REQUIRE_CORE_RESET
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// Workaround for ESP32C3: enable core reset
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// before enabling uart module clock
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// to prevent uart output garbage value.
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#if SOC_UART_REQUIRE_CORE_RESET
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uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
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periph_module_reset(uart_periph_signal[uart_num].module);
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uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
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#else
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#else
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periph_module_reset(uart_periph_signal[uart_num].module);
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#endif
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#endif
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}
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uart_context[uart_num].hw_enabled = true;
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}
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@ -237,7 +237,7 @@ esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit
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return ESP_OK;
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}
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esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit)
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esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t *data_bit)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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uart_hal_get_data_bit_num(&(uart_context[uart_num].hal), data_bit);
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@ -254,7 +254,7 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
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return ESP_OK;
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}
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esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bit)
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esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t *stop_bit)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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@ -272,7 +272,7 @@ esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode)
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return ESP_OK;
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}
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esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode)
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esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t *parity_mode)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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@ -336,7 +336,7 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow
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return ESP_OK;
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}
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esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl)
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esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t *flow_ctrl)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL)
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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@ -373,7 +373,7 @@ esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
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static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
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{
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int* pdata = NULL;
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int *pdata = NULL;
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
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pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
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@ -389,7 +389,7 @@ static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
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static esp_err_t UART_ISR_ATTR uart_pattern_enqueue(uart_port_t uart_num, int pos)
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{
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esp_err_t ret = ESP_OK;
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uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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int next = p_pos->wr + 1;
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if (next >= p_pos->len) {
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next = 0;
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@ -407,11 +407,11 @@ static esp_err_t UART_ISR_ATTR uart_pattern_enqueue(uart_port_t uart_num, int po
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static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
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{
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if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
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if (p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
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return ESP_ERR_INVALID_STATE;
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} else {
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esp_err_t ret = ESP_OK;
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uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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if (p_pos->rd == p_pos->wr) {
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ret = ESP_FAIL;
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} else {
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@ -426,9 +426,9 @@ static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
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static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
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{
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uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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int rd = p_pos->rd;
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while(rd != p_pos->wr) {
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while (rd != p_pos->wr) {
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p_pos->data[rd] -= diff_len;
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int rd_rec = rd;
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rd ++;
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@ -446,7 +446,7 @@ int uart_pattern_pop_pos(uart_port_t uart_num)
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{
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UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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int pos = -1;
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if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
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pos = pat_pos->data[pat_pos->rd];
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@ -460,7 +460,7 @@ int uart_pattern_get_pos(uart_port_t uart_num)
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{
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UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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int pos = -1;
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if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
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pos = pat_pos->data[pat_pos->rd];
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@ -474,12 +474,12 @@ esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
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int* pdata = (int*) malloc(queue_length * sizeof(int));
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if(pdata == NULL) {
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int *pdata = (int *) malloc(queue_length * sizeof(int));
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if (pdata == NULL) {
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return ESP_ERR_NO_MEM;
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}
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
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int *ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
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p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
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p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
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p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
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@ -553,12 +553,12 @@ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num)
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esp_err_t uart_enable_rx_intr(uart_port_t uart_num)
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{
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return uart_enable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL|UART_INTR_RXFIFO_TOUT);
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return uart_enable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
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}
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esp_err_t uart_disable_rx_intr(uart_port_t uart_num)
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{
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return uart_disable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL|UART_INTR_RXFIFO_TOUT);
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return uart_disable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
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}
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esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
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@ -578,12 +578,12 @@ esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
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return ESP_OK;
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}
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esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags, uart_isr_handle_t *handle)
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esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void *), void *arg, int intr_alloc_flags, uart_isr_handle_t *handle)
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{
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int ret;
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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ret=esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags, fn, arg, handle);
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ret = esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags, fn, arg, handle);
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UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
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return ret;
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}
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@ -595,8 +595,8 @@ esp_err_t uart_isr_free(uart_port_t uart_num)
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UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
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UART_CHECK((p_uart_obj[uart_num]->intr_handle != NULL), "uart driver error", ESP_ERR_INVALID_ARG);
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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ret=esp_intr_free(p_uart_obj[uart_num]->intr_handle);
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p_uart_obj[uart_num]->intr_handle=NULL;
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ret = esp_intr_free(p_uart_obj[uart_num]->intr_handle);
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p_uart_obj[uart_num]->intr_handle = NULL;
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UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
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return ret;
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}
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@ -699,16 +699,16 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
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UART_CHECK((intr_conf), "param null", ESP_FAIL);
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uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
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UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
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if(intr_conf->intr_enable_mask & UART_INTR_RXFIFO_TOUT) {
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if (intr_conf->intr_enable_mask & UART_INTR_RXFIFO_TOUT) {
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uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), intr_conf->rx_timeout_thresh);
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} else {
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//Disable rx_tout intr
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uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), 0);
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}
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if(intr_conf->intr_enable_mask & UART_INTR_RXFIFO_FULL) {
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if (intr_conf->intr_enable_mask & UART_INTR_RXFIFO_FULL) {
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uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), intr_conf->rxfifo_full_thresh);
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}
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if(intr_conf->intr_enable_mask & UART_INTR_TXFIFO_EMPTY) {
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if (intr_conf->intr_enable_mask & UART_INTR_TXFIFO_EMPTY) {
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uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), intr_conf->txfifo_empty_intr_thresh);
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}
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uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), intr_conf->intr_enable_mask);
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@ -716,7 +716,7 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
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return ESP_OK;
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}
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static int UART_ISR_ATTR uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, uint8_t pat_num)
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static int UART_ISR_ATTR uart_find_pattern_from_last(uint8_t *buf, int length, uint8_t pat_chr, uint8_t pat_num)
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{
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int cnt = 0;
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int len = length;
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@ -737,37 +737,37 @@ static int UART_ISR_ATTR uart_find_pattern_from_last(uint8_t* buf, int length, u
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//internal isr handler for default driver code.
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static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
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{
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uart_obj_t *p_uart = (uart_obj_t*) param;
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uart_obj_t *p_uart = (uart_obj_t *) param;
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uint8_t uart_num = p_uart->uart_num;
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int rx_fifo_len = 0;
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uint32_t uart_intr_status = 0;
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uart_event_t uart_event;
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portBASE_TYPE HPTaskAwoken = 0;
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static uint8_t pat_flg = 0;
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while(1) {
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while (1) {
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// The `continue statement` may cause the interrupt to loop infinitely
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// we exit the interrupt here
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uart_intr_status = uart_hal_get_intsts_mask(&(uart_context[uart_num].hal));
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//Exit form while loop
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if(uart_intr_status == 0){
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if (uart_intr_status == 0) {
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break;
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}
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uart_event.type = UART_EVENT_MAX;
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if(uart_intr_status & UART_INTR_TXFIFO_EMPTY) {
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if (uart_intr_status & UART_INTR_TXFIFO_EMPTY) {
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UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
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uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
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UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
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uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
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if(p_uart->tx_waiting_brk) {
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if (p_uart->tx_waiting_brk) {
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continue;
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}
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//TX semaphore will only be used when tx_buf_size is zero.
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if(p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) {
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if (p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) {
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p_uart->tx_waiting_fifo = false;
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xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, &HPTaskAwoken);
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} else {
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//We don't use TX ring buffer, because the size is zero.
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if(p_uart->tx_buf_size == 0) {
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if (p_uart->tx_buf_size == 0) {
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continue;
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}
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bool en_tx_flg = false;
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@ -775,25 +775,25 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
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//We need to put a loop here, in case all the buffer items are very short.
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//That would cause a watch_dog reset because empty interrupt happens so often.
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//Although this is a loop in ISR, this loop will execute at most 128 turns.
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while(tx_fifo_rem) {
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if(p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) {
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while (tx_fifo_rem) {
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if (p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) {
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size_t size;
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p_uart->tx_head = (uart_tx_data_t*) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size);
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if(p_uart->tx_head) {
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p_uart->tx_head = (uart_tx_data_t *) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size);
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if (p_uart->tx_head) {
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//The first item is the data description
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//Get the first item to get the data information
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if(p_uart->tx_len_tot == 0) {
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if (p_uart->tx_len_tot == 0) {
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p_uart->tx_ptr = NULL;
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p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
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if(p_uart->tx_head->type == UART_DATA_BREAK) {
|
||||
if (p_uart->tx_head->type == UART_DATA_BREAK) {
|
||||
p_uart->tx_brk_flg = 1;
|
||||
p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len;
|
||||
}
|
||||
//We have saved the data description from the 1st item, return buffer.
|
||||
vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
|
||||
} else if(p_uart->tx_ptr == NULL) {
|
||||
} else if (p_uart->tx_ptr == NULL) {
|
||||
//Update the TX item pointer, we will need this to return item to buffer.
|
||||
p_uart->tx_ptr = (uint8_t*)p_uart->tx_head;
|
||||
p_uart->tx_ptr = (uint8_t *)p_uart->tx_head;
|
||||
en_tx_flg = true;
|
||||
p_uart->tx_len_cur = size;
|
||||
}
|
||||
@ -827,7 +827,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
p_uart->tx_ptr = NULL;
|
||||
//Sending item done, now we need to send break if there is a record.
|
||||
//Set TX break signal after FIFO is empty
|
||||
if(p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) {
|
||||
if (p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) {
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len);
|
||||
@ -853,12 +853,11 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((uart_intr_status & UART_INTR_RXFIFO_TOUT)
|
||||
|| (uart_intr_status & UART_INTR_RXFIFO_FULL)
|
||||
|| (uart_intr_status & UART_INTR_CMD_CHAR_DET)
|
||||
) {
|
||||
if(pat_flg == 1) {
|
||||
} else if ((uart_intr_status & UART_INTR_RXFIFO_TOUT)
|
||||
|| (uart_intr_status & UART_INTR_RXFIFO_FULL)
|
||||
|| (uart_intr_status & UART_INTR_CMD_CHAR_DET)
|
||||
) {
|
||||
if (pat_flg == 1) {
|
||||
uart_intr_status |= UART_INTR_CMD_CHAR_DET;
|
||||
pat_flg = 0;
|
||||
}
|
||||
@ -894,7 +893,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
p_uart->rx_stash_len = rx_fifo_len;
|
||||
//If we fail to push data to ring buffer, we will have to stash the data, and send next time.
|
||||
//Mainly for applications that uses flow control or small ring buffer.
|
||||
if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
|
||||
if (pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
|
||||
p_uart->rx_buffer_full_flg = true;
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
|
||||
@ -906,11 +905,11 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
|
||||
} else {
|
||||
uart_pattern_enqueue(uart_num,
|
||||
pat_idx <= -1 ?
|
||||
//can not find the pattern in buffer,
|
||||
p_uart->rx_buffered_len + p_uart->rx_stash_len :
|
||||
// find the pattern in buffer
|
||||
p_uart->rx_buffered_len + pat_idx);
|
||||
pat_idx <= -1 ?
|
||||
//can not find the pattern in buffer,
|
||||
p_uart->rx_buffered_len + p_uart->rx_stash_len :
|
||||
// find the pattern in buffer
|
||||
p_uart->rx_buffered_len + pat_idx);
|
||||
}
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) {
|
||||
@ -924,7 +923,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
if (rx_fifo_len < pat_num) {
|
||||
//some of the characters are read out in last interrupt
|
||||
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
|
||||
} else if(pat_idx >= 0) {
|
||||
} else if (pat_idx >= 0) {
|
||||
// find the pattern in stash buffer.
|
||||
uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
|
||||
}
|
||||
@ -937,14 +936,14 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
|
||||
if(uart_intr_status & UART_INTR_CMD_CHAR_DET) {
|
||||
if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
|
||||
uart_event.type = UART_PATTERN_DET;
|
||||
uart_event.size = rx_fifo_len;
|
||||
pat_flg = 1;
|
||||
}
|
||||
}
|
||||
} else if(uart_intr_status & UART_INTR_RXFIFO_OVF) {
|
||||
} else if (uart_intr_status & UART_INTR_RXFIFO_OVF) {
|
||||
// When fifo overflows, we reset the fifo.
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
|
||||
@ -956,10 +955,10 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
UART_EXIT_CRITICAL_ISR(&uart_selectlock);
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_OVF);
|
||||
uart_event.type = UART_FIFO_OVF;
|
||||
} else if(uart_intr_status & UART_INTR_BRK_DET) {
|
||||
} else if (uart_intr_status & UART_INTR_BRK_DET) {
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_BRK_DET);
|
||||
uart_event.type = UART_BREAK;
|
||||
} else if(uart_intr_status & UART_INTR_FRAM_ERR) {
|
||||
} else if (uart_intr_status & UART_INTR_FRAM_ERR) {
|
||||
UART_ENTER_CRITICAL_ISR(&uart_selectlock);
|
||||
if (p_uart->uart_select_notif_callback) {
|
||||
p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
|
||||
@ -967,7 +966,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
UART_EXIT_CRITICAL_ISR(&uart_selectlock);
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_FRAM_ERR);
|
||||
uart_event.type = UART_FRAME_ERR;
|
||||
} else if(uart_intr_status & UART_INTR_PARITY_ERR) {
|
||||
} else if (uart_intr_status & UART_INTR_PARITY_ERR) {
|
||||
UART_ENTER_CRITICAL_ISR(&uart_selectlock);
|
||||
if (p_uart->uart_select_notif_callback) {
|
||||
p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
|
||||
@ -975,32 +974,32 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
UART_EXIT_CRITICAL_ISR(&uart_selectlock);
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_PARITY_ERR);
|
||||
uart_event.type = UART_PARITY_ERR;
|
||||
} else if(uart_intr_status & UART_INTR_TX_BRK_DONE) {
|
||||
} else if (uart_intr_status & UART_INTR_TX_BRK_DONE) {
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_tx_break(&(uart_context[uart_num].hal), 0);
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
|
||||
if(p_uart->tx_brk_flg == 1) {
|
||||
if (p_uart->tx_brk_flg == 1) {
|
||||
uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
|
||||
}
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
|
||||
if(p_uart->tx_brk_flg == 1) {
|
||||
if (p_uart->tx_brk_flg == 1) {
|
||||
p_uart->tx_brk_flg = 0;
|
||||
p_uart->tx_waiting_brk = 0;
|
||||
} else {
|
||||
xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken);
|
||||
}
|
||||
} else if(uart_intr_status & UART_INTR_TX_BRK_IDLE) {
|
||||
} else if (uart_intr_status & UART_INTR_TX_BRK_IDLE) {
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
|
||||
} else if(uart_intr_status & UART_INTR_CMD_CHAR_DET) {
|
||||
} else if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
|
||||
uart_event.type = UART_PATTERN_DET;
|
||||
} else if ((uart_intr_status & UART_INTR_RS485_PARITY_ERR)
|
||||
|| (uart_intr_status & UART_INTR_RS485_FRM_ERR)
|
||||
|| (uart_intr_status & UART_INTR_RS485_CLASH)) {
|
||||
|| (uart_intr_status & UART_INTR_RS485_FRM_ERR)
|
||||
|| (uart_intr_status & UART_INTR_RS485_CLASH)) {
|
||||
// RS485 collision or frame error interrupt triggered
|
||||
UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
|
||||
@ -1009,7 +1008,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RS485_CLASH | UART_INTR_RS485_FRM_ERR | UART_INTR_RS485_PARITY_ERR);
|
||||
uart_event.type = UART_EVENT_MAX;
|
||||
} else if(uart_intr_status & UART_INTR_TX_DONE) {
|
||||
} else if (uart_intr_status & UART_INTR_TX_DONE) {
|
||||
if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) && uart_hal_is_tx_idle(&(uart_context[uart_num].hal)) != true) {
|
||||
// The TX_DONE interrupt is triggered but transmit is active
|
||||
// then postpone interrupt processing for next interrupt
|
||||
@ -1033,13 +1032,13 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
||||
uart_event.type = UART_EVENT_MAX;
|
||||
}
|
||||
|
||||
if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
|
||||
if (uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
|
||||
if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) {
|
||||
ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
|
||||
}
|
||||
}
|
||||
}
|
||||
if(HPTaskAwoken == pdTRUE) {
|
||||
if (HPTaskAwoken == pdTRUE) {
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
}
|
||||
@ -1053,11 +1052,11 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
|
||||
portTickType ticks_start = xTaskGetTickCount();
|
||||
//Take tx_mux
|
||||
res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)ticks_to_wait);
|
||||
if(res == pdFALSE) {
|
||||
if (res == pdFALSE) {
|
||||
return ESP_ERR_TIMEOUT;
|
||||
}
|
||||
xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, 0);
|
||||
if(uart_hal_is_tx_idle(&(uart_context[uart_num].hal))) {
|
||||
if (uart_hal_is_tx_idle(&(uart_context[uart_num].hal))) {
|
||||
xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1074,7 +1073,7 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
|
||||
}
|
||||
//take 2nd tx_done_sem, wait given from ISR
|
||||
res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait);
|
||||
if(res == pdFALSE) {
|
||||
if (res == pdFALSE) {
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
|
||||
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
@ -1085,12 +1084,12 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len)
|
||||
int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
|
||||
UART_CHECK(buffer, "buffer null", (-1));
|
||||
if(len == 0) {
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
}
|
||||
int tx_len = 0;
|
||||
@ -1101,14 +1100,14 @@ int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len)
|
||||
uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
|
||||
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
}
|
||||
uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*) buffer, len, (uint32_t *)&tx_len);
|
||||
uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t *) buffer, len, (uint32_t *)&tx_len);
|
||||
xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
|
||||
return tx_len;
|
||||
}
|
||||
|
||||
static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool brk_en, int brk_len)
|
||||
static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool brk_en, int brk_len)
|
||||
{
|
||||
if(size == 0) {
|
||||
if (size == 0) {
|
||||
return 0;
|
||||
}
|
||||
size_t original_size = size;
|
||||
@ -1116,29 +1115,29 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool
|
||||
//lock for uart_tx
|
||||
xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
|
||||
p_uart_obj[uart_num]->coll_det_flg = false;
|
||||
if(p_uart_obj[uart_num]->tx_buf_size > 0) {
|
||||
if (p_uart_obj[uart_num]->tx_buf_size > 0) {
|
||||
size_t max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf);
|
||||
int offset = 0;
|
||||
uart_tx_data_t evt;
|
||||
evt.tx_data.size = size;
|
||||
evt.tx_data.brk_len = brk_len;
|
||||
if(brk_en) {
|
||||
if (brk_en) {
|
||||
evt.type = UART_DATA_BREAK;
|
||||
} else {
|
||||
evt.type = UART_DATA;
|
||||
}
|
||||
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) &evt, sizeof(uart_tx_data_t), portMAX_DELAY);
|
||||
while(size > 0) {
|
||||
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY);
|
||||
while (size > 0) {
|
||||
size_t send_size = size > max_size / 2 ? max_size / 2 : size;
|
||||
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) (src + offset), send_size, portMAX_DELAY);
|
||||
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) (src + offset), send_size, portMAX_DELAY);
|
||||
size -= send_size;
|
||||
offset += send_size;
|
||||
uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
|
||||
}
|
||||
} else {
|
||||
while(size) {
|
||||
while (size) {
|
||||
//semaphore for tx_fifo available
|
||||
if(pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
|
||||
if (pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
|
||||
uint32_t sent = 0;
|
||||
if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
@ -1146,8 +1145,8 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool
|
||||
uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
|
||||
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
}
|
||||
uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*)src, size, &sent);
|
||||
if(sent < size) {
|
||||
uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t *)src, size, &sent);
|
||||
if (sent < size) {
|
||||
p_uart_obj[uart_num]->tx_waiting_fifo = true;
|
||||
uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
|
||||
}
|
||||
@ -1155,7 +1154,7 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool
|
||||
src += sent;
|
||||
}
|
||||
}
|
||||
if(brk_en) {
|
||||
if (brk_en) {
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_tx_break(&(uart_context[uart_num].hal), brk_len);
|
||||
@ -1169,7 +1168,7 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool
|
||||
return original_size;
|
||||
}
|
||||
|
||||
int uart_write_bytes(uart_port_t uart_num, const void* src, size_t size)
|
||||
int uart_write_bytes(uart_port_t uart_num, const void *src, size_t size)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
|
||||
UART_CHECK((p_uart_obj[uart_num] != NULL), "uart driver error", (-1));
|
||||
@ -1177,7 +1176,7 @@ int uart_write_bytes(uart_port_t uart_num, const void* src, size_t size)
|
||||
return uart_tx_all(uart_num, src, size, 0, 0);
|
||||
}
|
||||
|
||||
int uart_write_bytes_with_break(uart_port_t uart_num, const void* src, size_t size, int brk_len)
|
||||
int uart_write_bytes_with_break(uart_port_t uart_num, const void *src, size_t size, int brk_len)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
|
||||
@ -1189,9 +1188,9 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const void* src, size_t si
|
||||
|
||||
static bool uart_check_buf_full(uart_port_t uart_num)
|
||||
{
|
||||
if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
|
||||
if (p_uart_obj[uart_num]->rx_buffer_full_flg) {
|
||||
BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
|
||||
if(res == pdTRUE) {
|
||||
if (res == pdTRUE) {
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
|
||||
p_uart_obj[uart_num]->rx_buffer_full_flg = false;
|
||||
@ -1203,22 +1202,22 @@ static bool uart_check_buf_full(uart_port_t uart_num)
|
||||
return false;
|
||||
}
|
||||
|
||||
int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t ticks_to_wait)
|
||||
int uart_read_bytes(uart_port_t uart_num, void *buf, uint32_t length, TickType_t ticks_to_wait)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
|
||||
UART_CHECK((buf), "uart data null", (-1));
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
|
||||
uint8_t* data = NULL;
|
||||
uint8_t *data = NULL;
|
||||
size_t size;
|
||||
size_t copy_len = 0;
|
||||
int len_tmp;
|
||||
if(xSemaphoreTake(p_uart_obj[uart_num]->rx_mux,(portTickType)ticks_to_wait) != pdTRUE) {
|
||||
if (xSemaphoreTake(p_uart_obj[uart_num]->rx_mux, (portTickType)ticks_to_wait) != pdTRUE) {
|
||||
return -1;
|
||||
}
|
||||
while(length) {
|
||||
if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
|
||||
data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait);
|
||||
if(data) {
|
||||
while (length) {
|
||||
if (p_uart_obj[uart_num]->rx_cur_remain == 0) {
|
||||
data = (uint8_t *) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait);
|
||||
if (data) {
|
||||
p_uart_obj[uart_num]->rx_head_ptr = data;
|
||||
p_uart_obj[uart_num]->rx_ptr = data;
|
||||
p_uart_obj[uart_num]->rx_cur_remain = size;
|
||||
@ -1226,7 +1225,7 @@ int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t
|
||||
//When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time,
|
||||
//which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty
|
||||
//to solve the possible asynchronous issues.
|
||||
if(uart_check_buf_full(uart_num)) {
|
||||
if (uart_check_buf_full(uart_num)) {
|
||||
//This condition will never be true if `uart_read_bytes`
|
||||
//and `uart_rx_intr_handler_default` are scheduled on the same core.
|
||||
continue;
|
||||
@ -1236,7 +1235,7 @@ int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t
|
||||
}
|
||||
}
|
||||
}
|
||||
if(p_uart_obj[uart_num]->rx_cur_remain > length) {
|
||||
if (p_uart_obj[uart_num]->rx_cur_remain > length) {
|
||||
len_tmp = length;
|
||||
} else {
|
||||
len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
|
||||
@ -1250,7 +1249,7 @@ int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t
|
||||
p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
|
||||
copy_len += len_tmp;
|
||||
length -= len_tmp;
|
||||
if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
|
||||
if (p_uart_obj[uart_num]->rx_cur_remain == 0) {
|
||||
vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr);
|
||||
p_uart_obj[uart_num]->rx_head_ptr = NULL;
|
||||
p_uart_obj[uart_num]->rx_ptr = NULL;
|
||||
@ -1262,7 +1261,7 @@ int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t
|
||||
return copy_len;
|
||||
}
|
||||
|
||||
esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
|
||||
esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t *size)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
|
||||
@ -1274,7 +1273,7 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
|
||||
|
||||
esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
|
||||
|
||||
static esp_err_t uart_disable_intr_mask_and_return_prev(uart_port_t uart_num, uint32_t disable_mask, uint32_t* prev_mask)
|
||||
static esp_err_t uart_disable_intr_mask_and_return_prev(uart_port_t uart_num, uint32_t disable_mask, uint32_t *prev_mask)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
@ -1288,16 +1287,16 @@ esp_err_t uart_flush_input(uart_port_t uart_num)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
|
||||
uart_obj_t* p_uart = p_uart_obj[uart_num];
|
||||
uint8_t* data;
|
||||
uart_obj_t *p_uart = p_uart_obj[uart_num];
|
||||
uint8_t *data;
|
||||
size_t size;
|
||||
uint32_t prev_mask;
|
||||
|
||||
//rx sem protect the ring buffer read related functions
|
||||
xSemaphoreTake(p_uart->rx_mux, (portTickType)portMAX_DELAY);
|
||||
uart_disable_intr_mask_and_return_prev(uart_num, UART_INTR_RXFIFO_FULL|UART_INTR_RXFIFO_TOUT, &prev_mask);
|
||||
while(true) {
|
||||
if(p_uart->rx_head_ptr) {
|
||||
uart_disable_intr_mask_and_return_prev(uart_num, UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT, &prev_mask);
|
||||
while (true) {
|
||||
if (p_uart->rx_head_ptr) {
|
||||
vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
|
||||
@ -1308,10 +1307,10 @@ esp_err_t uart_flush_input(uart_port_t uart_num)
|
||||
p_uart->rx_head_ptr = NULL;
|
||||
}
|
||||
data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (portTickType) 0);
|
||||
if(data == NULL) {
|
||||
if (data == NULL) {
|
||||
bool error = false;
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) {
|
||||
if ( p_uart_obj[uart_num]->rx_buffered_len != 0 ) {
|
||||
p_uart_obj[uart_num]->rx_buffered_len = 0;
|
||||
error = true;
|
||||
}
|
||||
@ -1329,9 +1328,9 @@ esp_err_t uart_flush_input(uart_port_t uart_num)
|
||||
uart_pattern_queue_update(uart_num, size);
|
||||
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
vRingbufferReturnItem(p_uart->rx_ring_buf, data);
|
||||
if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
|
||||
if (p_uart_obj[uart_num]->rx_buffer_full_flg) {
|
||||
BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
|
||||
if(res == pdTRUE) {
|
||||
if (res == pdTRUE) {
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
|
||||
p_uart_obj[uart_num]->rx_buffer_full_flg = false;
|
||||
@ -1366,9 +1365,9 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
||||
}
|
||||
#endif
|
||||
|
||||
if(p_uart_obj[uart_num] == NULL) {
|
||||
p_uart_obj[uart_num] = (uart_obj_t*) heap_caps_calloc(1, sizeof(uart_obj_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
||||
if(p_uart_obj[uart_num] == NULL) {
|
||||
if (p_uart_obj[uart_num] == NULL) {
|
||||
p_uart_obj[uart_num] = (uart_obj_t *) heap_caps_calloc(1, sizeof(uart_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
if (p_uart_obj[uart_num] == NULL) {
|
||||
ESP_LOGE(UART_TAG, "UART driver malloc error");
|
||||
return ESP_FAIL;
|
||||
}
|
||||
@ -1392,7 +1391,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
||||
p_uart_obj[uart_num]->rx_buffered_len = 0;
|
||||
uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
|
||||
|
||||
if(uart_queue) {
|
||||
if (uart_queue) {
|
||||
p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
|
||||
*uart_queue = p_uart_obj[uart_num]->xQueueUart;
|
||||
ESP_LOGI(UART_TAG, "queue free spaces: %d", uxQueueSpacesAvailable(p_uart_obj[uart_num]->xQueueUart));
|
||||
@ -1405,7 +1404,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
||||
p_uart_obj[uart_num]->rx_cur_remain = 0;
|
||||
p_uart_obj[uart_num]->rx_head_ptr = NULL;
|
||||
p_uart_obj[uart_num]->rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF);
|
||||
if(tx_buffer_size > 0) {
|
||||
if (tx_buffer_size > 0) {
|
||||
p_uart_obj[uart_num]->tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT);
|
||||
p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size;
|
||||
} else {
|
||||
@ -1427,10 +1426,14 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
||||
uart_module_enable(uart_num);
|
||||
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
|
||||
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
|
||||
r=uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle);
|
||||
if (r!=ESP_OK) goto err;
|
||||
r=uart_intr_config(uart_num, &uart_intr);
|
||||
if (r!=ESP_OK) goto err;
|
||||
r = uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle);
|
||||
if (r != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
r = uart_intr_config(uart_num, &uart_intr);
|
||||
if (r != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
return r;
|
||||
|
||||
err:
|
||||
@ -1442,7 +1445,7 @@ err:
|
||||
esp_err_t uart_driver_delete(uart_port_t uart_num)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
|
||||
if(p_uart_obj[uart_num] == NULL) {
|
||||
if (p_uart_obj[uart_num] == NULL) {
|
||||
ESP_LOGI(UART_TAG, "ALREADY NULL");
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1451,35 +1454,35 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
|
||||
uart_disable_tx_intr(uart_num);
|
||||
uart_pattern_link_free(uart_num);
|
||||
|
||||
if(p_uart_obj[uart_num]->tx_fifo_sem) {
|
||||
if (p_uart_obj[uart_num]->tx_fifo_sem) {
|
||||
vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);
|
||||
p_uart_obj[uart_num]->tx_fifo_sem = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->tx_done_sem) {
|
||||
if (p_uart_obj[uart_num]->tx_done_sem) {
|
||||
vSemaphoreDelete(p_uart_obj[uart_num]->tx_done_sem);
|
||||
p_uart_obj[uart_num]->tx_done_sem = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->tx_brk_sem) {
|
||||
if (p_uart_obj[uart_num]->tx_brk_sem) {
|
||||
vSemaphoreDelete(p_uart_obj[uart_num]->tx_brk_sem);
|
||||
p_uart_obj[uart_num]->tx_brk_sem = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->tx_mux) {
|
||||
if (p_uart_obj[uart_num]->tx_mux) {
|
||||
vSemaphoreDelete(p_uart_obj[uart_num]->tx_mux);
|
||||
p_uart_obj[uart_num]->tx_mux = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->rx_mux) {
|
||||
if (p_uart_obj[uart_num]->rx_mux) {
|
||||
vSemaphoreDelete(p_uart_obj[uart_num]->rx_mux);
|
||||
p_uart_obj[uart_num]->rx_mux = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->xQueueUart) {
|
||||
if (p_uart_obj[uart_num]->xQueueUart) {
|
||||
vQueueDelete(p_uart_obj[uart_num]->xQueueUart);
|
||||
p_uart_obj[uart_num]->xQueueUart = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->rx_ring_buf) {
|
||||
if (p_uart_obj[uart_num]->rx_ring_buf) {
|
||||
vRingbufferDelete(p_uart_obj[uart_num]->rx_ring_buf);
|
||||
p_uart_obj[uart_num]->rx_ring_buf = NULL;
|
||||
}
|
||||
if(p_uart_obj[uart_num]->tx_ring_buf) {
|
||||
if (p_uart_obj[uart_num]->tx_ring_buf) {
|
||||
vRingbufferDelete(p_uart_obj[uart_num]->tx_ring_buf);
|
||||
p_uart_obj[uart_num]->tx_ring_buf = NULL;
|
||||
}
|
||||
@ -1528,15 +1531,15 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
|
||||
}
|
||||
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
uart_hal_set_mode(&(uart_context[uart_num].hal), mode);
|
||||
if(mode == UART_MODE_RS485_COLLISION_DETECT) {
|
||||
if (mode == UART_MODE_RS485_COLLISION_DETECT) {
|
||||
// This mode allows read while transmitting that allows collision detection
|
||||
p_uart_obj[uart_num]->coll_det_flg = false;
|
||||
// Enable collision detection interrupts
|
||||
uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT
|
||||
| UART_INTR_RXFIFO_FULL
|
||||
| UART_INTR_RS485_CLASH
|
||||
| UART_INTR_RS485_FRM_ERR
|
||||
| UART_INTR_RS485_PARITY_ERR);
|
||||
| UART_INTR_RXFIFO_FULL
|
||||
| UART_INTR_RS485_CLASH
|
||||
| UART_INTR_RS485_FRM_ERR
|
||||
| UART_INTR_RS485_PARITY_ERR);
|
||||
}
|
||||
p_uart_obj[uart_num]->uart_mode = mode;
|
||||
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
|
||||
@ -1592,7 +1595,7 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag)
|
||||
esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool *collision_flag)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
|
||||
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
|
||||
@ -1616,7 +1619,7 @@ esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold)
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_threshold)
|
||||
esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int *out_wakeup_threshold)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
|
||||
UART_CHECK((out_wakeup_threshold != NULL), "argument is NULL", ESP_ERR_INVALID_ARG);
|
||||
@ -1627,7 +1630,7 @@ esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_thresh
|
||||
esp_err_t uart_wait_tx_idle_polling(uart_port_t uart_num)
|
||||
{
|
||||
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
|
||||
while(!uart_hal_is_tx_idle(&(uart_context[uart_num].hal)));
|
||||
while (!uart_hal_is_tx_idle(&(uart_context[uart_num].hal)));
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user