Merge branch 'feature/ld_change' into 'master'

update ld and heap region

Divide origin fpga ld to several lds,  choose specific ld for normal/BT/Trace by menuconfig, change iram/dram len in ld to full use hardware ram region.

See merge request !28

components/bootloader/src/main/Makefile

@@ -7,7 +7,7 @@
 # please read the esp-idf build system document if you need to do this.
 #
 
-COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T eagle.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/eagle.fpga32.rom.addr.v7.ld 
+COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T esp32.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/esp32.rom.ld 
 COMPONENT_EXTRA_INCLUDES := $(IDF_PATH)/components/esp32/include 
 
 include $(IDF_PATH)/make/component.mk

components/esp32/Makefile

@@ -6,16 +6,32 @@
 # lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
 # please read the esp-idf build system document if you need to do this.
 #
+-include $(PROJECT_PATH)/build/include/config/auto.conf
 
 LIBS := crypto core net80211 phy rtc pp wpa wps
 
+ifeq ($(CONFIG_MEMMAP_BT),y)
+    ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
+        LINKER_SCRIPTS = -T esp32.bt.trace.ld
+    else
+        LINKER_SCRIPTS = -T esp32.bt.ld
+    endif
+else
+    ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
+        LINKER_SCRIPTS = -T esp32.trace.ld
+    else
+        LINKER_SCRIPTS = -T esp32.ld
+    endif
+endif
+
+LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld
+
 COMPONENT_ADD_LDFLAGS := -lesp32 \
                            $(abspath libhal.a) \
                            -L$(abspath lib) \
                            $(addprefix -l,$(LIBS)) \
                           -L $(abspath ld) \
-                          -T eagle.fpga32.v7.ld \
+                          $(LINKER_SCRIPTS)
-                          -T eagle.fpga32.rom.addr.v7.ld
 
 include $(IDF_PATH)/make/component.mk
 

components/esp32/heap_alloc_caps.c

@@ -77,9 +77,9 @@ This array is *NOT* const because it gets modified depending on what pools are/a
 */
 static HeapRegionTagged_t regions[]={
 	{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
-//	{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- can be used for BT <- THIS POOL DOESN'T WORK for some reason! Hw seems fine. ToDo: Figure out.
+	{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
 	{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
-	{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14
+	{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT
 	{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
 	{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
 	{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
@@ -158,7 +158,6 @@ static void disable_mem_region(void *from, void *to) {
 ToDo: These are very dependent on the linker script, and the logic involving this works only
 because we're not using the SPI flash yet! If we enable that, this will break. ToDo: Rewrite by then.
 */
-extern int _init_start, _text_end;
 extern int _bss_start, _heap_start;
 
 /*
@@ -170,12 +169,23 @@ Same with loading of apps. Same with using SPI RAM.
 void heap_alloc_caps_init() {
 	int i;
 	//Disable the bits of memory where this code is loaded.
-	disable_mem_region(&_init_start, &_text_end);
 	disable_mem_region(&_bss_start, &_heap_start);
 	disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
-	disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
 	disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
 	disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
+	disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5
+
+	// TODO: this region should be checked, since we don't need to knock out all region finally
+	disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
+
+#if CONFIG_MEMMAP_BT
+	disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region
+#endif
+
+#if CONFIG_MEMMAP_TRACEMEM
+	disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region
+#endif
+
 #if 0
 	enable_spi_sram();
 #else

components/esp32/ld/esp32.bt.ld

@@ -0,0 +1,14 @@
+/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
+/* The load addresses are defined later using the AT statements. */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000  /* Even though the segment name is iram, it is actually mapped to flash */
+  dram0_0_seg (RW) :                 org = 0x3FFC0000, len = 0x40000   /* Shared RAM, minus rom bss/data/stack.*/
+  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
+}
+
+_heap_end = 0x40000000;

components/esp32/ld/esp32.bt.trace.ld

@@ -0,0 +1,14 @@
+/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
+/* The load addresses are defined later using the AT statements. */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000  /* Even though the segment name is iram, it is actually mapped to flash */
+  dram0_0_seg (RW) :                 org = 0x3FFC0000, len = 0x38000   /* Shared RAM, minus rom bss/data/stack.*/
+  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
+}
+
+_heap_end = 0x3FFF8000;

components/esp32/ld/esp32.common.ld

@@ -1,18 +1,3 @@
-/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
-/* The load addresses are defined later using the AT statements. */
-MEMORY
-{
-  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
-  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
-  are connected to the data port of the CPU and eg allow bytewise access. */
-  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x18000   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
-  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000  /* Even though the segment name is iram, it is actually mapped to flash */
-  dram0_0_seg (RW) :                 org = 0x3FFC0000, len = 0x20000   /* Shared RAM, minus rom bss/data/stack.*/
-  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
-}
-
-_heap_end = 0x3fffe000;
-
 /*  Default entry point:  */
 ENTRY(call_user_start_cpu0);
 

components/esp32/ld/esp32.ld

@@ -0,0 +1,14 @@
+/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
+/* The load addresses are defined later using the AT statements. */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000  /* Even though the segment name is iram, it is actually mapped to flash */
+  dram0_0_seg (RW) :                 org = 0x3FFB0000, len = 0x50000   /* Shared RAM, minus rom bss/data/stack.*/
+  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
+}
+
+_heap_end = 0x40000000;

components/esp32/ld/esp32.trace.ld

@@ -0,0 +1,14 @@
+/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
+/* The load addresses are defined later using the AT statements. */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000  /* Even though the segment name is iram, it is actually mapped to flash */
+  dram0_0_seg (RW) :                 org = 0x3FFB0000, len = 0x48000   /* Shared RAM, minus rom bss/data/stack.*/
+  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
+}
+
+_heap_end = 0x3FFF8000;