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Merge branch 'bugfix/cache2phys_xip_v5.2' into 'release/v5.2'

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fix(mmap): fixed spi_flash_cache2phys return addr in PSRAM issue (v5.2)

See merge request espressif/esp-idf!31106
This commit is contained in:
Jiang Jiang Jian 2024-08-28 13:39:20 +08:00
commit f42dcf03b6
1 changed files with 34 additions and 32 deletions
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66
components/spi_flash/flash_mmap.c
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@ -270,38 +270,6 @@ uint32_t spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory)
return len / CONFIG_MMU_PAGE_SIZE; return len / CONFIG_MMU_PAGE_SIZE;
} }
size_t spi_flash_cache2phys(const void *cached)
{
if (cached == NULL) {
return SPI_FLASH_CACHE2PHYS_FAIL;
}
esp_err_t ret = ESP_FAIL;
uint32_t paddr = 0;
mmu_target_t target = 0;
ret = esp_mmu_vaddr_to_paddr((void *)cached, &paddr, &target);
if (ret != ESP_OK) {
return SPI_FLASH_CACHE2PHYS_FAIL;
}
int offset = 0;
#if CONFIG_SPIRAM_RODATA
if ((uint32_t)cached >= (uint32_t)&_rodata_reserved_start && (uint32_t)cached <= (uint32_t)&_rodata_reserved_end) {
offset = rodata_flash2spiram_offset();
}
#endif
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
if ((uint32_t)cached >= (uint32_t)&_instruction_reserved_start && (uint32_t)cached <= (uint32_t)&_instruction_reserved_end) {
offset = instruction_flash2spiram_offset();
}
#endif
return paddr + offset * CONFIG_MMU_PAGE_SIZE;
}
const void * spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory) const void * spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory)
{ {
esp_err_t ret = ESP_FAIL; esp_err_t ret = ESP_FAIL;
@ -384,3 +352,37 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
return ret; return ret;
} }
#endif //!CONFIG_SPI_FLASH_ROM_IMPL #endif //!CONFIG_SPI_FLASH_ROM_IMPL
#if !CONFIG_SPI_FLASH_ROM_IMPL || CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
//The ROM implementation returns physical address of the PSRAM when the .text or .rodata is in the PSRAM.
//Always patch it when SPIRAM_FETCH_INSTRUCTIONS or SPIRAM_RODATA is set.
size_t spi_flash_cache2phys(const void *cached)
{
if (cached == NULL) {
return SPI_FLASH_CACHE2PHYS_FAIL;
}
esp_err_t ret = ESP_FAIL;
uint32_t paddr = 0;
mmu_target_t target = 0;
ret = esp_mmu_vaddr_to_paddr((void *)cached, &paddr, &target);
if (ret != ESP_OK) {
return SPI_FLASH_CACHE2PHYS_FAIL;
}
int offset = 0;
#if CONFIG_SPIRAM_RODATA
if ((uint32_t)cached >= (uint32_t)&_rodata_reserved_start && (uint32_t)cached <= (uint32_t)&_rodata_reserved_end) {
offset = rodata_flash2spiram_offset();
}
#endif
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
if ((uint32_t)cached >= (uint32_t)&_instruction_reserved_start && (uint32_t)cached <= (uint32_t)&_instruction_reserved_end) {
offset = instruction_flash2spiram_offset();
}
#endif
return paddr + offset * CONFIG_MMU_PAGE_SIZE;
}
#endif