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Merge branch 'bugfix/fix_esp32_psram_cs_hold_time_issue_when_under_80m_v4.3' into 'release/v4.3'

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esp_psram: fix esp32 psram cs hold time issue when under 40m (v4.3)

See merge request espressif/esp-idf!19649
This commit is contained in:
morris 2022-09-15 15:30:30 +08:00
commit f425cd9d15
1 changed files with 12 additions and 1 deletions
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13
components/esp32/spiram_psram.c
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@ -131,6 +131,17 @@ typedef enum {
#define PICO_V3_02_PSRAM_CLK_IO 10
#define PICO_V3_02_PSRAM_CS_IO 9
#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
#define PSRAM_CS_HOLD_TIME 0
#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
#define PSRAM_CS_HOLD_TIME 0
#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
#define PSRAM_CS_HOLD_TIME 1
#else
#error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
#endif
typedef struct {
uint8_t flash_clk_io;
uint8_t flash_cs_io;
@ -667,7 +678,7 @@ void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
if (clk_mode == PSRAM_CLK_MODE_NORM) {
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
// Set cs time.
SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, PSRAM_CS_HOLD_TIME, SPI_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
} else {
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);