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Merge branch 'bugfix/usb_reg_header_definition_upd' into 'master'
USB: usb_reg.h update missing register bitfield description See merge request espressif/esp-idf!22766
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commit
f3de7e574d
@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@ -1491,6 +1483,17 @@ extern "C" {
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#define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S)
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#define USB_NZSTSOUTHSHK_V 0x00000001
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#define USB_NZSTSOUTHSHK_S 2
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/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0;
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* This bit can be set only if FS PHY interface is selected.
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* Otherwise, this bit needs to be set to zero.
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* 1'b0: USB 1.1 Full-Speed Serial transiver not selected
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* 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
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* must be switched from 48 MHz to 32 KHz
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*/
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#define USB_ENA32KHZSUSP (BIT(3))
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#define USB_ENA32KHZSUSP_M (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S)
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#define USB_ENA32KHZSUSP_V 0x00000001
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#define USB_ENA32KHZSUSP_S 3
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/** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0;
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* Device Address.
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*/
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@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@ -1492,6 +1484,17 @@ extern "C" {
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#define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S)
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#define USB_NZSTSOUTHSHK_V 0x00000001
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#define USB_NZSTSOUTHSHK_S 2
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/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0;
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* This bit can be set only if FS PHY interface is selected.
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* Otherwise, this bit needs to be set to zero.
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* 1'b0: USB 1.1 Full-Speed Serial transiver not selected
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* 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
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* must be switched from 48 MHz to 32 KHz
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*/
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#define USB_ENA32KHZSUSP (BIT(3))
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#define USB_ENA32KHZSUSP_M (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S)
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#define USB_ENA32KHZSUSP_V 0x00000001
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#define USB_ENA32KHZSUSP_S 3
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/** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0;
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* Device Address.
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*/
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@ -922,7 +922,6 @@ components/soc/esp32s2/include/soc/touch_sensor_pins.h
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components/soc/esp32s2/include/soc/uart_pins.h
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components/soc/esp32s2/include/soc/uart_reg.h
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components/soc/esp32s2/include/soc/uhci_reg.h
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components/soc/esp32s2/include/soc/usb_reg.h
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components/soc/esp32s2/include/soc/usb_struct.h
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components/soc/esp32s2/include/soc/usb_types.h
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components/soc/esp32s2/include/soc/usb_wrap_reg.h
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@ -994,7 +993,6 @@ components/soc/esp32s3/include/soc/uart_reg.h
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components/soc/esp32s3/include/soc/uart_struct.h
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components/soc/esp32s3/include/soc/uhci_reg.h
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components/soc/esp32s3/include/soc/uhci_struct.h
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components/soc/esp32s3/include/soc/usb_reg.h
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components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
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components/soc/esp32s3/include/soc/usb_struct.h
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components/soc/esp32s3/include/soc/usb_types.h
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