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Merge branch 'feature/mac_clock_config' into 'master'
Feature/mac clock config Closes IDFGH-4761 and IDFGH-5356 See merge request espressif/esp-idf!13671
This commit is contained in:
commit
f379076ac8
@ -21,9 +21,6 @@ menu "Ethernet"
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config ETH_PHY_INTERFACE_RMII
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config ETH_PHY_INTERFACE_RMII
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bool "Reduced Media Independent Interface (RMII)"
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bool "Reduced Media Independent Interface (RMII)"
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config ETH_PHY_INTERFACE_MII
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bool "Media Independent Interface (MII)"
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endchoice
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endchoice
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if ETH_PHY_INTERFACE_RMII
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if ETH_PHY_INTERFACE_RMII
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@ -287,17 +287,98 @@ struct esp_eth_mac_s {
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esp_err_t (*del)(esp_eth_mac_t *mac);
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esp_err_t (*del)(esp_eth_mac_t *mac);
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};
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};
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/**
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* @brief RMII Clock Mode Options
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*
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*/
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typedef enum {
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/**
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* @brief Default values configured using Kconfig are going to be used when "Default" selected.
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*
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*/
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EMAC_CLK_DEFAULT,
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/**
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* @brief Input RMII Clock from external. EMAC Clock GPIO number needs to be configured when this option is selected.
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*
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* @note MAC will get RMII clock from outside. Note that ESP32 only supports GPIO0 to input the RMII clock.
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*
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*/
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EMAC_CLK_EXT_IN,
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/**
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* @brief Output RMII Clock from internal APLL Clock. EMAC Clock GPIO number needs to be configured when this option is selected.
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*
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*/
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EMAC_CLK_OUT
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} emac_rmii_clock_mode_t;
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/**
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* @brief RMII Clock GPIO number Options
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*
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*/
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typedef enum {
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/**
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* @brief MAC will get RMII clock from outside at this GPIO.
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*
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* @note ESP32 only supports GPIO0 to input the RMII clock.
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*
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*/
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EMAC_CLK_IN_GPIO = 0,
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/**
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* @brief Output RMII Clock from internal APLL Clock available at GPIO0
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*
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* @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
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* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
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* You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
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* If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
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*
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*/
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EMAC_APPL_CLK_OUT_GPIO = 0,
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/**
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* @brief Output RMII Clock from internal APLL Clock available at GPIO16
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*
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*/
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EMAC_CLK_OUT_GPIO = 16,
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/**
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* @brief Inverted Output RMII Clock from internal APLL Clock available at GPIO17
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*
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*/
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EMAC_CLK_OUT_180_GPIO = 17
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} emac_rmii_clock_gpio_t;
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/**
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* @brief Ethernet MAC Clock Configuration
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*
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*/
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typedef union {
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struct {
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// MII interface is not fully implemented...
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// Reserved for GPIO number, clock source, etc. in MII mode
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} mii; /*!< EMAC MII Clock Configuration */
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struct {
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emac_rmii_clock_mode_t clock_mode; /*!< RMII Clock Mode Configuration */
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emac_rmii_clock_gpio_t clock_gpio; /*!< RMII Clock GPIO Configuration */
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} rmii; /*!< EMAC RMII Clock Configuration */
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} eth_mac_clock_config_t;
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/**
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/**
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* @brief Configuration of Ethernet MAC object
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* @brief Configuration of Ethernet MAC object
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*
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*
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*/
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*/
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typedef struct {
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typedef struct {
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uint32_t sw_reset_timeout_ms; /*!< Software reset timeout value (Unit: ms) */
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uint32_t sw_reset_timeout_ms; /*!< Software reset timeout value (Unit: ms) */
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uint32_t rx_task_stack_size; /*!< Stack size of the receive task */
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uint32_t rx_task_stack_size; /*!< Stack size of the receive task */
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uint32_t rx_task_prio; /*!< Priority of the receive task */
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uint32_t rx_task_prio; /*!< Priority of the receive task */
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int smi_mdc_gpio_num; /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
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int smi_mdc_gpio_num; /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
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int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
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int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
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uint32_t flags; /*!< Flags that specify extra capability for mac driver */
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uint32_t flags; /*!< Flags that specify extra capability for mac driver */
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eth_data_interface_t interface; /*!< EMAC Data interface to PHY (MII/RMII) */
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eth_mac_clock_config_t clock_config; /*!< EMAC Interface clock configuration */
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} eth_mac_config_t;
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} eth_mac_config_t;
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#define ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE (1 << 0) /*!< MAC driver can work when cache is disabled */
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#define ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE (1 << 0) /*!< MAC driver can work when cache is disabled */
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@ -307,14 +388,16 @@ typedef struct {
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* @brief Default configuration for Ethernet MAC object
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* @brief Default configuration for Ethernet MAC object
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*
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*
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*/
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*/
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#define ETH_MAC_DEFAULT_CONFIG() \
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#define ETH_MAC_DEFAULT_CONFIG() \
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{ \
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{ \
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.sw_reset_timeout_ms = 100, \
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.sw_reset_timeout_ms = 100, \
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.rx_task_stack_size = 4096, \
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.rx_task_stack_size = 4096, \
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.rx_task_prio = 15, \
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.rx_task_prio = 15, \
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.smi_mdc_gpio_num = 23, \
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.smi_mdc_gpio_num = 23, \
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.smi_mdio_gpio_num = 18, \
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.smi_mdio_gpio_num = 18, \
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.flags = 0, \
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.flags = 0, \
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.interface = EMAC_DATA_INTERFACE_RMII, \
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.clock_config.rmii.clock_mode = EMAC_CLK_DEFAULT, \
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}
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}
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#if CONFIG_ETH_USE_ESP32_EMAC
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#if CONFIG_ETH_USE_ESP32_EMAC
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@ -57,6 +57,8 @@ typedef struct {
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uint32_t flow_control_low_water_mark;
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uint32_t flow_control_low_water_mark;
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int smi_mdc_gpio_num;
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int smi_mdc_gpio_num;
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int smi_mdio_gpio_num;
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int smi_mdio_gpio_num;
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eth_data_interface_t interface;
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eth_mac_clock_config_t clock_config;
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uint8_t addr[6];
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uint8_t addr[6];
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uint8_t *rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM];
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uint8_t *rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM];
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uint8_t *tx_buf[CONFIG_ETH_DMA_TX_BUFFER_NUM];
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uint8_t *tx_buf[CONFIG_ETH_DMA_TX_BUFFER_NUM];
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@ -303,7 +305,6 @@ static void emac_esp32_init_smi_gpio(emac_esp32_t *emac)
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}
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}
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}
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}
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#if CONFIG_ETH_RMII_CLK_OUTPUT
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static void emac_config_apll_clock(void)
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static void emac_config_apll_clock(void)
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{
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{
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/* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) */
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/* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) */
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@ -329,7 +330,6 @@ static void emac_config_apll_clock(void)
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break;
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break;
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}
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}
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}
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}
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#endif
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static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
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static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
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{
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{
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@ -340,40 +340,38 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
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periph_module_enable(PERIPH_EMAC_MODULE);
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periph_module_enable(PERIPH_EMAC_MODULE);
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/* init clock, config gpio, etc */
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/* init clock, config gpio, etc */
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#if CONFIG_ETH_PHY_INTERFACE_MII
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if (emac->interface == EMAC_DATA_INTERFACE_MII) {
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/* MII interface GPIO initialization */
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/* MII interface GPIO initialization */
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emac_hal_iomux_init_mii();
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emac_hal_iomux_init_mii();
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/* Enable MII clock */
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/* Enable MII clock */
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emac_ll_clock_enable_mii(emac->hal.ext_regs);
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emac_ll_clock_enable_mii(emac->hal.ext_regs);
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#elif CONFIG_ETH_PHY_INTERFACE_RMII
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} else if (emac->interface == EMAC_DATA_INTERFACE_RMII) {
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/* RMII interface GPIO initialization */
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/* RMII interface GPIO initialization */
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emac_hal_iomux_init_rmii();
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emac_hal_iomux_init_rmii();
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/* If ref_clk is configured as input */
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/* If ref_clk is configured as input */
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#if CONFIG_ETH_RMII_CLK_INPUT
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if (emac->clock_config.rmii.clock_mode == EMAC_CLK_EXT_IN) {
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#if CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_CLK_IN_GPIO,
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emac_hal_iomux_rmii_clk_input();
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ESP_ERR_INVALID_ARG, err, TAG, "ESP32 EMAC only support input RMII clock to GPIO0");
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#else
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emac_hal_iomux_rmii_clk_input();
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#error "ESP32 EMAC only support input RMII clock to GPIO0"
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emac_ll_clock_enable_rmii_input(emac->hal.ext_regs);
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#endif // CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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} else if (emac->clock_config.rmii.clock_mode == EMAC_CLK_OUT) {
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emac_ll_clock_enable_rmii_input(emac->hal.ext_regs);
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ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO ||
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#endif // CONFIG_ETH_RMII_CLK_INPUT
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emac->clock_config.rmii.clock_gpio == EMAC_CLK_OUT_GPIO ||
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emac->clock_config.rmii.clock_gpio == EMAC_CLK_OUT_180_GPIO,
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/* If ref_clk is configured as output */
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ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC clock output GPIO");
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#if CONFIG_ETH_RMII_CLK_OUTPUT
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emac_hal_iomux_rmii_clk_ouput(emac->clock_config.rmii.clock_gpio);
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#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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if (emac->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO) {
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emac_hal_iomux_rmii_clk_ouput(0);
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REG_SET_FIELD(PIN_CTRL, CLK_OUT1, 6);
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/* Choose the APLL clock1 to output on specific GPIO */
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}
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REG_SET_FIELD(PIN_CTRL, CLK_OUT1, 6);
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/* Enable RMII clock */
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#elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 16
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emac_ll_clock_enable_rmii_output(emac->hal.ext_regs);
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emac_hal_iomux_rmii_clk_ouput(16);
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emac_config_apll_clock();
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#elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 17
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} else {
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emac_hal_iomux_rmii_clk_ouput(17);
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ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC clock mode");
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#endif // CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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}
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/* Enable RMII clock */
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} else {
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emac_ll_clock_enable_rmii_output(emac->hal.ext_regs);
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ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC interface");
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emac_config_apll_clock();
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}
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#endif // CONFIG_ETH_RMII_CLK_OUTPUT
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#endif // CONFIG_ETH_PHY_INTERFACE_MII
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/* init gpio used by smi interface */
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/* init gpio used by smi interface */
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emac_esp32_init_smi_gpio(emac);
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emac_esp32_init_smi_gpio(emac);
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@ -516,6 +514,34 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_mac_config_t *config)
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emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
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emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
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emac->smi_mdc_gpio_num = config->smi_mdc_gpio_num;
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emac->smi_mdc_gpio_num = config->smi_mdc_gpio_num;
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emac->smi_mdio_gpio_num = config->smi_mdio_gpio_num;
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emac->smi_mdio_gpio_num = config->smi_mdio_gpio_num;
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ESP_GOTO_ON_FALSE(config->interface == EMAC_DATA_INTERFACE_MII || config->interface == EMAC_DATA_INTERFACE_RMII,
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NULL, err, TAG, "invalid EMAC Data Interface");
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emac->interface = config->interface;
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if (emac->interface == EMAC_DATA_INTERFACE_RMII) {
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if (config->clock_config.rmii.clock_mode == EMAC_CLK_DEFAULT) {
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#if CONFIG_ETH_RMII_CLK_INPUT && CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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emac->clock_config.rmii.clock_mode = EMAC_CLK_EXT_IN;
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emac->clock_config.rmii.clock_gpio = CONFIG_ETH_RMII_CLK_IN_GPIO;
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#else
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#error "ESP32 EMAC only support input RMII clock to GPIO0"
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#endif // CONFIG_ETH_RMII_CLK_INPUT && CONFIG_ETH_RMII_CLK_IN_GPIO == 0
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/* If ref_clk is configured as output */
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#if CONFIG_ETH_RMII_CLK_OUTPUT
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emac->clock_config.rmii.clock_mode = EMAC_CLK_OUT;
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#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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emac->clock_config.rmii.clock_gpio = 0;
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#elif CONFIG_ETH_RMII_CLK_OUT_GPIO
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emac->clock_config.rmii.clock_gpio = CONFIG_ETH_RMII_CLK_OUT_GPIO;
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#endif // CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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#endif // CONFIG_ETH_RMII_CLK_OUTPUT
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} else {
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emac->clock_config = config->clock_config;
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}
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} else if (emac->interface == EMAC_DATA_INTERFACE_MII) {
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emac->clock_config = config->clock_config;
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}
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emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
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emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
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emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
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emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
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emac->parent.set_mediator = emac_esp32_set_mediator;
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emac->parent.set_mediator = emac_esp32_set_mediator;
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@ -24,8 +24,8 @@
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*
|
*
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*/
|
*/
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typedef enum {
|
typedef enum {
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EMAC_INTERFACE_MII, /*!< Media Independent Interface */
|
EMAC_DATA_INTERFACE_RMII, /*!< Reduced Media Independent Interface */
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EMAC_INTERFACE_RMII /*!< Reduced Media Independent Interface */
|
EMAC_DATA_INTERFACE_MII, /*!< Media Independent Interface */
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} eth_data_interface_t;
|
} eth_data_interface_t;
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|
|
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/**
|
/**
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||||||
|
@ -130,6 +130,9 @@ Ethernet driver is composed of two parts: MAC and PHY. The communication between
|
|||||||
* Some PHY chip uses an external connected 50MHz crystal oscillator or other clock source, which can also be used as the ``REF_CLK`` for MAC side (as seen the option *b* in the picture). In this case, you still need to select ``CONFIG_ETH_RMII_CLK_INPUT`` in :ref:`CONFIG_ETH_RMII_CLK_MODE`.
|
* Some PHY chip uses an external connected 50MHz crystal oscillator or other clock source, which can also be used as the ``REF_CLK`` for MAC side (as seen the option *b* in the picture). In this case, you still need to select ``CONFIG_ETH_RMII_CLK_INPUT`` in :ref:`CONFIG_ETH_RMII_CLK_MODE`.
|
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* Some EMAC controller can generate the ``REF_CLK`` using its internal high precision PLL (as seen the option *c* in the picture). In this case, you should select ``CONFIG_ETH_RMII_CLK_OUTPUT`` in :ref:`CONFIG_ETH_RMII_CLK_MODE`.
|
* Some EMAC controller can generate the ``REF_CLK`` using its internal high precision PLL (as seen the option *c* in the picture). In this case, you should select ``CONFIG_ETH_RMII_CLK_OUTPUT`` in :ref:`CONFIG_ETH_RMII_CLK_MODE`.
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|
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.. note::
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|
``REF_CLK`` is configured via Project Configuration as described above by default. However, it can be overwritten from user application code by appropriately setting :cpp:member:`interface` and :cpp:member:`clock_config` members of :cpp:class:`eth_mac_config_t` structure. See :cpp:enum:`emac_rmii_clock_mode_t` and :cpp:enum:`emac_rmii_clock_gpio_t` for more details.
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|
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.. warning::
|
.. warning::
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If the RMII clock mode is selected to ``CONFIG_ETH_RMII_CLK_OUTPUT``, then ``GPIO0`` can be used to output the ``REF_CLK`` signal. See :ref:`CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0` for more information.
|
If the RMII clock mode is selected to ``CONFIG_ETH_RMII_CLK_OUTPUT``, then ``GPIO0`` can be used to output the ``REF_CLK`` signal. See :ref:`CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0` for more information.
|
||||||
What's more, if you're not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock. See :ref:`CONFIG_ETH_RMII_CLK_OUT_GPIO` for more information.
|
What's more, if you're not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock. See :ref:`CONFIG_ETH_RMII_CLK_OUT_GPIO` for more information.
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||||||
@ -160,6 +163,8 @@ Configuration for MAC is described in :cpp:class:`eth_mac_config_t`, including:
|
|||||||
* :cpp:member:`sw_reset_timeout_ms`: software reset timeout value, in milliseconds, typically MAC reset should be finished within 100ms.
|
* :cpp:member:`sw_reset_timeout_ms`: software reset timeout value, in milliseconds, typically MAC reset should be finished within 100ms.
|
||||||
* :cpp:member:`rx_task_stack_size` and :cpp:member:`rx_task_prio`: the MAC driver creates a dedicated task to process incoming packets, these two parameters are used to set the stack size and priority of the task.
|
* :cpp:member:`rx_task_stack_size` and :cpp:member:`rx_task_prio`: the MAC driver creates a dedicated task to process incoming packets, these two parameters are used to set the stack size and priority of the task.
|
||||||
* :cpp:member:`smi_mdc_gpio_num` and :cpp:member:`smi_mdio_gpio_num`: the GPIO number used to connect the SMI signals.
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* :cpp:member:`smi_mdc_gpio_num` and :cpp:member:`smi_mdio_gpio_num`: the GPIO number used to connect the SMI signals.
|
||||||
|
* :cpp:member:`interface`: configuration of MAC Data interface to PHY (MII/RMII).
|
||||||
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* :cpp:member:`clock_config`: configuration of EMAC Interface clock (``REF_CLK`` mode and GPIO number in case of RMII).
|
||||||
* :cpp:member:`flags`: specifying extra features that the MAC driver should have, it could be useful in some special situations. The value of this field can be OR'd with macros prefixed with ``ETH_MAC_FLAG_``. For example, if the MAC driver should work when cache is disabled, then you should configure this field with :c:macro:`ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE`.
|
* :cpp:member:`flags`: specifying extra features that the MAC driver should have, it could be useful in some special situations. The value of this field can be OR'd with macros prefixed with ``ETH_MAC_FLAG_``. For example, if the MAC driver should work when cache is disabled, then you should configure this field with :c:macro:`ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE`.
|
||||||
|
|
||||||
Configuration for PHY is described in :cpp:class:`eth_phy_config_t`, including:
|
Configuration for PHY is described in :cpp:class:`eth_phy_config_t`, including:
|
||||||
@ -199,6 +204,24 @@ Ethernet driver is implemented in an Object-Oriented style. Any operation on MAC
|
|||||||
Care should be taken, when creating MAC and PHY instance for SPI-Ethernet modules (e.g. DM9051), the constructor function must have the same suffix (e.g. `esp_eth_mac_new_dm9051` and `esp_eth_phy_new_dm9051`). This is because we don't have other choices but the integrated PHY.
|
Care should be taken, when creating MAC and PHY instance for SPI-Ethernet modules (e.g. DM9051), the constructor function must have the same suffix (e.g. `esp_eth_mac_new_dm9051` and `esp_eth_phy_new_dm9051`). This is because we don't have other choices but the integrated PHY.
|
||||||
Besides that, we have to create an SPI device handle firstly and then pass it to the MAC constructor function. More instructions on creating SPI device handle, please refer to :doc:`SPI Master <../peripherals/spi_master>`.
|
Besides that, we have to create an SPI device handle firstly and then pass it to the MAC constructor function. More instructions on creating SPI device handle, please refer to :doc:`SPI Master <../peripherals/spi_master>`.
|
||||||
|
|
||||||
|
Optional Runtime MAC Clock Configuration
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
EMAC ``REF_CLK`` can be optionally configured from user application code.
|
||||||
|
|
||||||
|
.. highlight:: c
|
||||||
|
|
||||||
|
::
|
||||||
|
|
||||||
|
eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); // apply default MAC configuration
|
||||||
|
|
||||||
|
// ...
|
||||||
|
|
||||||
|
mac_config.interface = EMAC_DATA_INTERFACE_RMII; // alter EMAC Data Interface
|
||||||
|
mac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT; // select EMAC REF_CLK mode
|
||||||
|
mac_config.clock_config.rmii.clock_gpio = EMAC_CLK_OUT_GPIO; // select GPIO number used to input/output EMAC REF_CLK
|
||||||
|
esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&mac_config); // create MAC instance
|
||||||
|
|
||||||
Install Driver
|
Install Driver
|
||||||
--------------
|
--------------
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user