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Merge branch 'feat/parlio_tx_support_psram_buffer_v5.2' into 'release/v5.2'

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fix(parlio_tx): Fixed errors in the first transfer (v5.2)

See merge request espressif/esp-idf!33358
This commit is contained in:
morris 2024-09-25 15:25:01 +08:00
commit f2482e7aed
1 changed files with 4 additions and 2 deletions
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6
components/driver/parlio/parlio_tx.c
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@ -270,6 +270,8 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par
tx_unit->out_clk_freq_hz = hal_utils_calc_clk_div_integer(&clk_info, &clk_div.integer); tx_unit->out_clk_freq_hz = hal_utils_calc_clk_div_integer(&clk_info, &clk_div.integer);
#endif #endif
PARLIO_CLOCK_SRC_ATOMIC() { PARLIO_CLOCK_SRC_ATOMIC() {
// turn on the tx module clock to sync the register configuration to the module
parlio_ll_tx_enable_clock(hal->regs, true);
parlio_ll_tx_set_clock_source(hal->regs, clk_src); parlio_ll_tx_set_clock_source(hal->regs, clk_src);
// set clock division // set clock division
parlio_ll_tx_set_clock_div(hal->regs, &clk_div); parlio_ll_tx_set_clock_div(hal->regs, &clk_div);
@ -371,8 +373,8 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge); parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge);
#if SOC_PARLIO_TX_SIZE_BY_DMA #if SOC_PARLIO_TX_SIZE_BY_DMA
// Always use DMA EOF as the Parlio TX EOF // Always use DATA LEN EOF as the Parlio TX EOF
parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF); parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN);
#endif // SOC_PARLIO_TX_SIZE_BY_DMA #endif // SOC_PARLIO_TX_SIZE_BY_DMA
// clear any pending interrupt // clear any pending interrupt