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Merge branch 'bugfix/bod_glitch_reset_c6_v4.4' into 'release/v4.4'

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bootloader: fix BOD and glitch reset on C6 and H2 (v4.4)

See merge request espressif/esp-idf!24936
This commit is contained in:
morris 2023-07-28 10:30:29 +08:00
commit f1d3f04afd
8 changed files with 22 additions and 38 deletions
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12
components/bootloader_support/src/esp32/bootloader_soc.c
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@ -3,18 +3,10 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdbool.h> #include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable) //Not supported but common bootloader calls the function. Do nothing
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_clock_glitch_reset_config(bool enable) void bootloader_ana_clock_glitch_reset_config(bool enable)
{ {
(void)enable; (void)enable;

18
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
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@ -268,29 +268,29 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
/* /*
For origin chip & ECO1: only support swt reset; For origin chip & ECO1: brownout & clock glitch reset not available
For ECO2: fix brownout reset bug, support swt & brownout reset; For ECO2: fix brownout reset bug
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. For ECO3: fix clock glitch reset bug
*/ */
switch (efuse_hal_chip_revision()) { switch (efuse_hal_chip_revision()) {
case 0: case 0:
case 1: case 1:
//Enable WDT reset. Disable BOR and GLITCH reset //Disable BOD and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(false); bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false); bootloader_ana_clock_glitch_reset_config(false);
break; break;
case 2: case 2:
//Enable WDT and BOR reset. Disable GLITCH reset //Enable BOD reset. Disable GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false); bootloader_ana_clock_glitch_reset_config(false);
break; break;
case 3: case 3:
default: default:
//Enable WDT, BOR, and GLITCH reset //Enable BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true); bootloader_ana_clock_glitch_reset_config(true);
break; break;

6
components/bootloader_support/src/esp32c3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} }
} }
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

12
components/bootloader_support/src/esp32s2/bootloader_soc.c
View File

@ -3,18 +3,10 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdbool.h> #include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable) //Not supported but common bootloader calls the function. Do nothing
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_clock_glitch_reset_config(bool enable) void bootloader_ana_clock_glitch_reset_config(bool enable)
{ {
(void)enable; (void)enable;

2
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -322,7 +322,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
//Enable WDT, BOR, and GLITCH reset //Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true); bootloader_ana_clock_glitch_reset_config(true);

6
components/bootloader_support/src/esp32s3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} }
} }
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

2
components/soc/esp32c3/include/soc/rtc_cntl_reg.h
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@ -2361,7 +2361,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110)

2
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
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@ -3577,7 +3577,7 @@ ork.*/
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C)