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adc: refactor adc single read api on esp32c3

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This commit is contained in:
Armando 2021-02-23 21:40:15 +08:00
parent ea20966c29
commit f1be501271
7 changed files with 232 additions and 451 deletions
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12
components/driver/adc_common.c
View File

@ -552,6 +552,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel)
*/
esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
{
esp_err_t ret = ESP_OK;
int adc_value = 0;
ADC_CHECK(raw_out != NULL, "ADC out value err", ESP_ERR_INVALID_ARG);
@ -591,7 +592,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif //CONFIG_PM_ENABLE
#endif //CONFIG_IDF_TARGET_ESP32
if (adc_hal_convert(ADC_NUM_2, channel, &adc_value)) {
ret = adc_hal_convert(ADC_NUM_2, channel, &adc_value);
if (ret != ESP_OK) {
ESP_LOGD( ADC_TAG, "ADC2 ARB: Return data is invalid." );
adc_value = -1;
}
@ -608,13 +611,8 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
adc_power_release();
SARADC2_RELEASE();
if (adc_value < 0) {
ESP_LOGD( ADC_TAG, "ADC2 ARB: Return data is invalid." );
return ESP_ERR_INVALID_STATE;
}
*raw_out = adc_value;
return ESP_OK;
return ret;
}
esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)

53
components/driver/esp32c3/adc.c
View File

@ -442,39 +442,20 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
int adc1_get_raw(adc1_channel_t channel)
{
int raw_out = 0;
adc_digi_config_t dig_cfg = {
.conv_limit_en = 0,
.conv_limit_num = 250,
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
};
ADC_DIGI_LOCK_ACQUIRE();
periph_module_enable(PERIPH_SARADC_MODULE);
adc_atten_t atten = s_atten1_single[channel];
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, channel, atten);
adc_hal_set_calibration_param(ADC_NUM_1, cal_val);
adc_hal_digi_controller_config(&dig_cfg);
adc_hal_set_power_manage(ADC_POWER_SW_ON);
adc_hal_set_atten(ADC_NUM_2, channel, atten);
adc_hal_convert(ADC_NUM_1, channel, &raw_out);
adc_hal_intr_clear(ADC_EVENT_ADC1_DONE);
adc_hal_adc1_onetime_sample_enable(true);
adc_hal_onetime_channel(ADC_NUM_1, channel);
adc_hal_set_onetime_atten(atten);
//Trigger single read.
adc_hal_onetime_start(&dig_cfg);
while (!adc_hal_intr_get_raw(ADC_EVENT_ADC1_DONE));
adc_hal_single_read(ADC_NUM_1, &raw_out);
adc_hal_intr_clear(ADC_EVENT_ADC1_DONE);
adc_hal_adc1_onetime_sample_enable(false);
adc_hal_digi_deinit();
adc_hal_set_power_manage(ADC_POWER_SW_OFF);
periph_module_disable(PERIPH_SARADC_MODULE);
ADC_DIGI_LOCK_RELEASE();
return raw_out;
@ -502,11 +483,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
}
esp_err_t ret = ESP_OK;
adc_digi_config_t dig_cfg = {
.conv_limit_en = 0,
.conv_limit_num = 250,
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
};
SAC_ADC2_LOCK_ACQUIRE();
ADC_DIGI_LOCK_ACQUIRE();
@ -516,25 +492,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten);
adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
adc_hal_digi_controller_config(&dig_cfg);
adc_hal_set_power_manage(ADC_POWER_SW_ON);
adc_hal_set_atten(ADC_NUM_2, channel, atten);
ret = adc_hal_convert(ADC_NUM_2, channel, raw_out);
adc_hal_intr_clear(ADC_EVENT_ADC2_DONE);
adc_hal_adc2_onetime_sample_enable(true);
adc_hal_onetime_channel(ADC_NUM_2, channel);
adc_hal_set_onetime_atten(atten);
//Trigger single read.
adc_hal_onetime_start(&dig_cfg);
while (!adc_hal_intr_get_raw(ADC_EVENT_ADC2_DONE));
ret = adc_hal_single_read(ADC_NUM_2, raw_out);
adc_hal_intr_clear(ADC_EVENT_ADC2_DONE);
adc_hal_adc2_onetime_sample_enable(false);
adc_hal_digi_deinit();
adc_hal_set_power_manage(ADC_POWER_SW_OFF);
periph_module_disable(PERIPH_SARADC_MODULE);
ADC_DIGI_LOCK_RELEASE();
SAC_ADC2_LOCK_RELEASE();

160
components/hal/adc_hal.c
View File

@ -23,6 +23,12 @@
#include "soc/gdma_channel.h"
#include "soc/soc.h"
#include "esp_rom_sys.h"
typedef enum {
ADC_EVENT_ADC1_DONE = BIT(0),
ADC_EVENT_ADC2_DONE = BIT(1),
} adc_hal_event_t;
#endif
void adc_hal_init(void)
@ -41,18 +47,6 @@ void adc_hal_deinit(void)
{
adc_ll_set_power_manage(ADC_POWER_SW_OFF);
}
#ifndef CONFIG_IDF_TARGET_ESP32C3
int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value)
{
adc_ll_rtc_enable_channel(adc_n, channel);
adc_ll_rtc_start_convert(adc_n, channel);
while (adc_ll_rtc_convert_is_done(adc_n) != true);
*value = adc_ll_rtc_get_convert_value(adc_n);
return (int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*value));
}
#endif
/*---------------------------------------------------------------
ADC calibration setting
---------------------------------------------------------------*/
@ -99,15 +93,9 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
#elif CONFIG_IDF_TARGET_ESP32C3
static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
{
adc_hal_set_controller(adc_n, ADC_CTRL_DIG); //Set controller
adc_digi_config_t dig_cfg = {
.conv_limit_en = 0,
.conv_limit_num = 250,
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
};
adc_hal_digi_controller_config(&dig_cfg);
adc_ll_onetime_sample_enable(ADC_NUM_1, false);
adc_ll_onetime_sample_enable(ADC_NUM_2, false);
adc_ll_set_power_manage(ADC_POWER_SW_ON);
/* Enable/disable internal connect GND (for calibration). */
if (internal_gnd) {
const int esp32c3_invalid_chan = (adc_n == ADC_NUM_1)? 0xF: 0x1;
@ -116,8 +104,7 @@ static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t att
adc_ll_onetime_set_channel(adc_n, channel);
}
adc_ll_onetime_set_atten(atten);
adc_hal_adc1_onetime_sample_enable((adc_n == ADC_NUM_1));
adc_hal_adc2_onetime_sample_enable((adc_n == ADC_NUM_2));
adc_ll_onetime_sample_enable(adc_n, true);
}
static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
@ -223,8 +210,8 @@ void adc_hal_digi_init(adc_hal_context_t *hal)
gdma_ll_clear_interrupt_status(hal->dev, hal->dma_chan, UINT32_MAX);
gdma_ll_enable_interrupt(hal->dev, hal->dma_chan, GDMA_LL_EVENT_RX_SUC_EOF, true);
adc_ll_digi_dma_set_eof_num(hal->eof_num);
adc_ll_adc1_onetime_sample_enable(false);
adc_ll_adc2_onetime_sample_enable(false);
adc_ll_onetime_sample_enable(ADC_NUM_1, false);
adc_ll_onetime_sample_enable(ADC_NUM_2, false);
}
void adc_hal_fifo_reset(adc_hal_context_t *hal)
@ -309,7 +296,32 @@ void adc_hal_digi_stop(adc_hal_context_t *hal)
/*---------------------------------------------------------------
Single Read
---------------------------------------------------------------*/
void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config)
//--------------------INTR-------------------------------//
static adc_ll_intr_t get_event_intr(adc_hal_event_t event)
{
adc_ll_intr_t intr_mask = 0;
if (event & ADC_EVENT_ADC1_DONE) {
intr_mask |= ADC_LL_INTR_ADC1_DONE;
}
if (event & ADC_EVENT_ADC2_DONE) {
intr_mask |= ADC_LL_INTR_ADC2_DONE;
}
return intr_mask;
}
static void adc_hal_intr_clear(adc_hal_event_t event)
{
adc_ll_intr_clear(get_event_intr(event));
}
static bool adc_hal_intr_get_raw(adc_hal_event_t event)
{
return adc_ll_intr_get_raw(get_event_intr(event));
}
//--------------------Single Read-------------------------------//
static void adc_hal_onetime_start(void)
{
/**
* There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
@ -335,74 +347,54 @@ void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config)
//No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
}
void adc_hal_adc1_onetime_sample_enable(bool enable)
static esp_err_t adc_hal_single_read(adc_ll_num_t adc_n, int *out_raw)
{
adc_ll_adc1_onetime_sample_enable(enable);
}
void adc_hal_adc2_onetime_sample_enable(bool enable)
{
adc_ll_adc2_onetime_sample_enable(enable);
}
void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel)
{
adc_ll_onetime_set_channel(unit, channel);
}
void adc_hal_set_onetime_atten(adc_atten_t atten)
{
adc_ll_onetime_set_atten(atten);
}
esp_err_t adc_hal_single_read(adc_ll_num_t unit, int *out_raw)
{
if (unit == ADC_NUM_1) {
if (adc_n == ADC_NUM_1) {
*out_raw = adc_ll_adc1_read();
} else if (unit == ADC_NUM_2) {
} else if (adc_n == ADC_NUM_2) {
*out_raw = adc_ll_adc2_read();
if (adc_ll_analysis_raw_data(unit, *out_raw)) {
if (adc_ll_analysis_raw_data(adc_n, *out_raw)) {
return ESP_ERR_INVALID_STATE;
}
}
return ESP_OK;
}
//--------------------INTR-------------------------------
static adc_ll_intr_t get_event_intr(adc_event_t event)
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
{
adc_ll_intr_t intr_mask = 0;
if (event & ADC_EVENT_ADC1_DONE) {
intr_mask |= ADC_LL_INTR_ADC1_DONE;
esp_err_t ret;
adc_hal_event_t event;
if (adc_n == ADC_NUM_1) {
event = ADC_EVENT_ADC1_DONE;
} else {
event = ADC_EVENT_ADC2_DONE;
}
if (event & ADC_EVENT_ADC2_DONE) {
intr_mask |= ADC_LL_INTR_ADC2_DONE;
adc_hal_intr_clear(event);
adc_ll_onetime_sample_enable(adc_n, true);
adc_ll_onetime_set_channel(adc_n, channel);
//Trigger single read.
adc_hal_onetime_start();
while (!adc_hal_intr_get_raw(event));
ret = adc_hal_single_read(adc_n, out_raw);
adc_ll_onetime_sample_enable(adc_n, false);
return ret;
}
#else // !CONFIG_IDF_TARGET_ESP32C3
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
{
adc_ll_rtc_enable_channel(adc_n, channel);
adc_ll_rtc_start_convert(adc_n, channel);
while (adc_ll_rtc_convert_is_done(adc_n) != true);
*out_raw = adc_ll_rtc_get_convert_value(adc_n);
if ((int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*out_raw))) {
return ESP_ERR_INVALID_STATE;
} else {
return ESP_OK;
}
return intr_mask;
}
void adc_hal_intr_enable(adc_event_t event)
{
adc_ll_intr_enable(get_event_intr(event));
}
void adc_hal_intr_disable(adc_event_t event)
{
adc_ll_intr_disable(get_event_intr(event));
}
void adc_hal_intr_clear(adc_event_t event)
{
adc_ll_intr_clear(get_event_intr(event));
}
bool adc_hal_intr_get_raw(adc_event_t event)
{
return adc_ll_intr_get_raw(get_event_intr(event));
}
bool adc_hal_intr_get_status(adc_event_t event)
{
return adc_ll_intr_get_status(get_event_intr(event));
}
#endif
#endif //#if !CONFIG_IDF_TARGET_ESP32C3

1
components/hal/esp32c3/adc_hal.c
View File

@ -72,7 +72,6 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
}
}
adc_ll_set_controller(pattern_both, ADC_CTRL_DIG);
if (cfg->conv_limit_en) {
adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num);
adc_ll_digi_convert_limit_enable();

164
components/hal/esp32c3/include/hal/adc_ll.h
View File

@ -54,8 +54,12 @@ typedef enum {
} adc_ll_rtc_raw_data_t;
typedef enum {
ADC_LL_INTR_ADC2_DONE = BIT(30),
ADC_LL_INTR_ADC1_DONE = BIT(31),
ADC_LL_INTR_THRES1_LOW = BIT(26),
ADC_LL_INTR_THRES0_LOW = BIT(27),
ADC_LL_INTR_THRES1_HIGH = BIT(28),
ADC_LL_INTR_THRES0_HIGH = BIT(29),
ADC_LL_INTR_ADC2_DONE = BIT(30),
ADC_LL_INTR_ADC1_DONE = BIT(31),
} adc_ll_intr_t;
FLAG_ATTR(adc_ll_intr_t)
@ -391,136 +395,6 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
}
}
/**
* Enable interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 1;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc2_done = 1;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_ena.thres0_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_ena.thres0_low = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_ena.thres1_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_ena.thres1_low = 1;
}
}
/**
* Disable interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 0;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc2_done = 0;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_ena.thres0_high = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_ena.thres0_low = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_ena.thres1_high = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_ena.thres1_low = 0;
}
}
/**
* Clear interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_clr.adc1_done = 1;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_clr.adc2_done = 1;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_clr.thres0_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_clr.thres0_low = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_clr.thres1_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_clr.thres1_low = 1;
}
}
/**
* Get interrupt status mask of adc digital controller.
*
* @param adc_n ADC unit.
* @return
* - intr Interrupt bitmask.
*/
static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n)
{
uint32_t int_st = APB_SARADC.int_st.val;
uint32_t ret_msk = 0;
if (adc_n == ADC_NUM_1) {
if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
}
} else { // adc_n == ADC_NUM_2
if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
}
}
if (int_st & APB_SARADC_THRES0_HIGH_INT_ST) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_HIGH;
}
if (int_st & APB_SARADC_THRES0_LOW_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_LOW;
}
if (int_st & APB_SARADC_THRES1_HIGH_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_HIGH;
}
if (int_st & APB_SARADC_THRES1_LOW_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_LOW;
}
return ret_msk;
}
/**
* Set DMA eof num of adc digital controller.
* If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
@ -653,17 +527,6 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
return manage;
}
/**
* Set ADC module controller.
* @param adc_n ADC unit.
* @param ctrl ADC controller.
*/
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
{
//This is for chip version compability. On esp32c3, the ADC1 is only controlled by digital controller, whereas ADC2 controller is
//auto-selected by arbiter according to the priority.
}
/**
* Set ADC2 module arbiter work mode.
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
@ -911,10 +774,13 @@ static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
return (APB_SARADC.int_st.val & mask);
}
//--------------------------------adc1------------------------------//
static inline void adc_ll_adc1_onetime_sample_enable(bool enable)
static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable)
{
APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
if (adc_n == ADC_NUM_1) {
APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
} else {
APB_SARADC.onetime_sample.adc2_onetime_sample = enable;
}
}
static inline uint32_t adc_ll_adc1_read(void)
@ -923,12 +789,6 @@ static inline uint32_t adc_ll_adc1_read(void)
return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff);
}
//--------------------------------adc2------------------------------//
static inline void adc_ll_adc2_onetime_sample_enable(bool enable)
{
APB_SARADC.onetime_sample.adc2_onetime_sample = enable;
}
static inline uint32_t adc_ll_adc2_read(void)
{
//On ESP32C3, valid data width is 12-bit

255
components/hal/include/hal/adc_hal.h
View File

@ -3,6 +3,7 @@
#include "soc/soc_caps.h"
#include "hal/adc_types.h"
#include "hal/adc_ll.h"
#include "esp_err.h"
#if CONFIG_IDF_TARGET_ESP32C3
#include "soc/gdma_struct.h"
@ -62,14 +63,6 @@ void adc_hal_init(void);
*/
void adc_hal_deinit(void);
/**
* Set adc sample cycle.
*
* @note Normally, please use default value.
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
*/
#define adc_hal_set_sample_cycle(sample_cycle) adc_ll_set_sample_cycle(sample_cycle)
/**
* Set ADC module power management.
*
@ -77,14 +70,6 @@ void adc_hal_deinit(void);
*/
#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
/**
* Get ADC module power management.
*
* @return
* - ADC power status.
*/
#define adc_hal_get_power_manage() adc_ll_get_power_manage()
/**
* ADC module clock division factor setting. ADC clock devided from APB clock.
*
@ -92,6 +77,7 @@ void adc_hal_deinit(void);
*/
#define adc_hal_digi_set_clk_div(div) adc_ll_digi_set_clk_div(div)
#if !CONFIG_IDF_TARGET_ESP32C3
/**
* ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`.
*
@ -110,7 +96,106 @@ void adc_hal_deinit(void);
* @prarm ctrl ADC controller.
*/
#define adc_hal_set_controller(adc_n, ctrl) adc_ll_set_controller(adc_n, ctrl)
#endif //#if !CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
/**
* Get the attenuation of a particular channel on ADCn.
*
* @param adc_n ADC unit.
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
#define adc_hal_get_atten(adc_n, channel) adc_ll_get_atten(adc_n, channel)
#endif
#if CONFIG_IDF_TARGET_ESP32
/**
* Close ADC AMP module if don't use it for power save.
*/
#define adc_hal_amp_disable() adc_ll_amp_disable()
#endif
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
/**
* Set adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @prarm cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
/**
* Get adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @return cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
#if !CONFIG_IDF_TARGET_ESP32C3
/**
* Set adc output data format for RTC controller.
*
* @prarm adc_n ADC unit.
* @prarm bits Output data bits width option.
*/
#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
/**
* ADC module output data invert or not.
*
* @prarm adc_n ADC unit.
*/
#define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en)
/**
* Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels.
*
* This function routes the internal reference voltage of ADCn to one of
* ADC2's channels. This reference voltage can then be manually measured
* for calibration purposes.
*
* @note ESP32 only supports output of ADC2's internal reference voltage.
* @param[in] adc ADC unit select
* @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output
*/
#define adc_hal_vref_output(adc, channel, en) adc_ll_vref_output(adc, channel, en)
#endif //#if !CONFIG_IDF_TARGET_ESP32C3
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Digital controller deinitialization.
*/
void adc_hal_digi_deinit(void);
/**
* Setting the digital controller.
*
* @param cfg Pointer to digital controller paramter.
*/
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
* @param adc_n ADC unit.
*/
#define adc_hal_digi_clear_pattern_table(adc_n) adc_ll_digi_clear_pattern_table(adc_n)
/*---------------------------------------------------------------
ADC Single Read
---------------------------------------------------------------*/
#if !CONFIG_IDF_TARGET_ESP32C3
/**
* Set the attenuation of a particular channel on ADCn.
*
@ -140,117 +225,39 @@ void adc_hal_deinit(void);
*
* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
*
* @prarm adc_n ADC unit.
* @prarm channel ADCn channel number.
* @prarm atten The attenuation option.
* @param adc_n ADC unit.
* @param channel ADCn channel number.
* @param atten ADC attenuation. See ``adc_atten_t``
*/
#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_set_atten(adc_n, channel, atten)
#else // CONFIG_IDF_TARGET_ESP32C3
/**
* Get the attenuation of a particular channel on ADCn.
* Set the attenuation for ADC to single read
*
* @param adc_n ADC unit.
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
#define adc_hal_get_atten(adc_n, channel) adc_ll_get_atten(adc_n, channel)
/**
* Close ADC AMP module if don't use it for power save.
*/
#define adc_hal_amp_disable() adc_ll_amp_disable()
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
/**
* Set adc cct for PWDET controller.
* @note All ADC units and channels will share the setting. So PLEASE DO save your attenuations and reset them by calling this API again in your driver
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @prarm cct Range: 0 ~ 7.
* @param adc_n Not used, leave here for chip version compatibility
* @param channel Not used, leave here for chip version compatibility
* @param atten ADC attenuation. See ``adc_atten_t``
*/
#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
/**
* Get adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @return cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
#ifndef CONFIG_IDF_TARGET_ESP32C3
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_onetime_set_atten(atten)
#endif
/**
* Get the converted value for each ADCn for RTC controller.
*
* @note It may be block to wait conversion finish.
*
* @prarm adc_n ADC unit.
* @param channel adc channel number.
* @param value Pointer for touch value.
* @param adc_n ADC unit.
* @param channel ADC channel number.
* @param[out] out_raw ADC converted result
*
* @return
* - 0: The value is valid.
* - ~0: The value is invalid.
* - ESP_OK: The value is valid.
* - ESP_ERR_INVALID_STATE: The value is invalid.
*/
int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value);
/**
* Set adc output data format for RTC controller.
*
* @prarm adc_n ADC unit.
* @prarm bits Output data bits width option.
*/
#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
/**
* ADC module output data invert or not.
*
* @prarm adc_n ADC unit.
*/
#define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en)
#endif
/**
* Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels.
*
* This function routes the internal reference voltage of ADCn to one of
* ADC2's channels. This reference voltage can then be manually measured
* for calibration purposes.
*
* @note ESP32 only supports output of ADC2's internal reference voltage.
* @param[in] adc ADC unit select
* @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output
*/
#define adc_hal_vref_output(adc, channel, en) adc_ll_vref_output(adc, channel, en)
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Digital controller deinitialization.
*/
void adc_hal_digi_deinit(void);
/**
* Setting the digital controller.
*
* @param cfg Pointer to digital controller paramter.
*/
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
* @param adc_n ADC unit.
*/
#define adc_hal_digi_clear_pattern_table(adc_n) adc_ll_digi_clear_pattern_table(adc_n)
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw);
/*---------------------------------------------------------------
ADC calibration setting
@ -376,30 +383,4 @@ void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask);
*/
void adc_hal_digi_stop(adc_hal_context_t *hal);
/*---------------------------------------------------------------
Single Read
---------------------------------------------------------------*/
void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config);
void adc_hal_adc1_onetime_sample_enable(bool enable);
void adc_hal_adc2_onetime_sample_enable(bool enable);
void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel);
void adc_hal_set_onetime_atten(adc_atten_t atten);
esp_err_t adc_hal_single_read(adc_ll_num_t unit, int *out_raw);
void adc_hal_intr_enable(adc_event_t event);
void adc_hal_intr_disable(adc_event_t event);
void adc_hal_intr_clear(adc_event_t event);
bool adc_hal_intr_get_raw(adc_event_t event);
bool adc_hal_intr_get_status(adc_event_t event);
#endif //#if CONFIG_IDF_TARGET_ESP32C3

38
components/hal/include/hal/adc_types.h
View File

@ -223,6 +223,7 @@ typedef struct {
} adc_digi_clk_t;
#endif //!CONFIG_IDF_TARGET_ESP32
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*
@ -294,6 +295,18 @@ typedef struct {
#endif
} adc_digi_config_t;
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
/**
* @brief ADC digital controller (DMA mode) interrupt type options.
*/
typedef enum {
ADC_DIGI_INTR_MASK_MONITOR = 0x1,
ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2,
ADC_DIGI_INTR_MASK_ALL = 0x3,
} adc_digi_intr_t;
FLAG_ATTR(adc_digi_intr_t)
#endif
#if !CONFIG_IDF_TARGET_ESP32
/**
@ -332,24 +345,6 @@ typedef struct {
.pwdet_pri = 2, \
}
/**
* @brief ADC digital controller (DMA mode) interrupt type options.
*/
typedef enum {
#if CONFIG_IDF_TARGET_ESP32C3
ADC_DIGI_INTR_MASK_MONITOR0_HIGH = BIT(0),
ADC_DIGI_INTR_MASK_MONITOR0_LOW = BIT(1),
ADC_DIGI_INTR_MASK_MONITOR1_HIGH = BIT(2),
ADC_DIGI_INTR_MASK_MONITOR1_LOW = BIT(3),
ADC_DIGI_INTR_MASK_MEAS_DONE = BIT(4),
#else
ADC_DIGI_INTR_MASK_MONITOR = 0x1,
ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2,
ADC_DIGI_INTR_MASK_ALL = 0x3,
#endif
} adc_digi_intr_t;
FLAG_ATTR(adc_digi_intr_t)
/**
* @brief ADC digital controller (DMA mode) filter index options.
*
@ -444,10 +439,3 @@ typedef struct {
} adc_digi_monitor_t;
#endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#if CONFIG_IDF_TARGET_ESP32C3
typedef enum {
ADC_EVENT_ADC1_DONE = BIT(0),
ADC_EVENT_ADC2_DONE = BIT(1),
} adc_event_t;
#endif