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spiram: Support configure CLK onto the same pin as flash for ESP32-D0WD

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When using PSRAM of rev0, the Flash and PSRAM should use different clock pins. But if using newer PSRAM, this is not necesary. This MR fixed the issue that allocating CLK of PSRAM to the same pin as Flash may crash.
This commit is contained in:
Michael (XIAO Xufeng) 2022-04-01 02:42:17 +08:00 committed by Xiao Xufeng
parent ca087a174d
commit f168e9f174
2 changed files with 22 additions and 7 deletions
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8
components/esp_psram/esp32/Kconfig.spiram
View File

@ -300,6 +300,9 @@ menu "SPI RAM config"
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
If configured to the same pin as Flash, PSRAM shouldn't be rev0. Contact Espressif for more
information.
config D0WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on SPIRAM
@ -321,6 +324,9 @@ menu "SPI RAM config"
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
If configured to the same pin (GPIO6) as Flash, PSRAM shouldn't be rev0. Contact Espressif for more
information.
config D2WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on SPIRAM
@ -331,7 +337,7 @@ menu "SPI RAM config"
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-PICO"
menu "PSRAM clock and cs IO for ESP32-PICO-D4"
config PICO_PSRAM_CS_IO
int "PSRAM CS IO number"

21
components/esp_psram/esp32/esp_psram_impl_quad.c
View File

@ -838,14 +838,16 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
abort();
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
ESP_EARLY_LOGI(TAG, "This chip is %s",
(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)? "ESP32-PICO": "ESP32-U4WDH");
// We have better alternatives, though it's possible to use U4WDH together with PSRAM.
// U4WDH shares the same pin config with PICO for historical reasons.
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
psram_io.psram_cs_io = PICO_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
@ -855,7 +857,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO;
psram_io.psram_cs_io = PICO_V3_02_PSRAM_CS_IO;
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){
@ -869,7 +870,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
} else {
@ -902,6 +902,12 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
}
if (psram_io.flash_clk_io == psram_io.psram_clk_io) {
s_clk_mode = PSRAM_CLK_MODE_NORM;
} else {
s_clk_mode = PSRAM_CLK_MODE_DCLK;
}
assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
s_psram_mode = mode;
@ -956,7 +962,10 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
}
if (psram_is_32mbit_ver0()) {
s_clk_mode = PSRAM_CLK_MODE_DCLK;
if (s_clk_mode != PSRAM_CLK_MODE_DCLK) {
ESP_EARLY_LOGE(TAG, "PSRAM rev0 can't share CLK with Flash");
abort();
}
if (mode == PSRAM_CACHE_F80M_S80M) {
#ifdef CONFIG_SPIRAM_OCCUPY_NO_HOST
ESP_EARLY_LOGE(TAG, "This version of PSRAM needs to claim an extra SPI peripheral at 80MHz. Please either: choose lower frequency by SPIRAM_SPEED_, or select one SPI peripheral it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig.");