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timer_group: fix intr_enable
timer group interrupt enable is controled by level_int_ena instead of int_ena Closes https://github.com/espressif/esp-idf/issues/5103
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@ -258,7 +258,12 @@ esp_err_t timer_group_intr_enable(timer_group_t group_num, uint32_t en_mask)
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{
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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TG[group_num]->int_ena.val |= en_mask;
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for (int i = 0; i < 2; i++) {
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if (en_mask & (1 << i)) {
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TG[group_num]->hw_timer[i].config.level_int_en = 1;
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TG[group_num]->int_ena.val |= (1 << i);
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}
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}
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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return ESP_OK;
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}
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}
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@ -267,7 +272,12 @@ esp_err_t timer_group_intr_disable(timer_group_t group_num, uint32_t disable_mas
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{
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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TG[group_num]->int_ena.val &= (~disable_mask);
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for (int i = 0; i < 2; i++) {
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if (disable_mask & (1 << i)) {
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TG[group_num]->hw_timer[i].config.level_int_en = 0;
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TG[group_num]->int_ena.val &= ~(1 << i);
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}
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}
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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return ESP_OK;
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}
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}
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@ -276,14 +286,22 @@ esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
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{
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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return timer_group_intr_enable(group_num, BIT(timer_num));
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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TG[group_num]->hw_timer[timer_num].config.level_int_en = 1;
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TG[group_num]->int_ena.val |= (1 << timer_num);
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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}
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esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
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esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
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{
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{
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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return timer_group_intr_disable(group_num, BIT(timer_num));
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portENTER_CRITICAL(&timer_spinlock[group_num]);
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TG[group_num]->hw_timer[timer_num].config.level_int_en = 0;
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TG[group_num]->int_ena.val &= ~(1 << timer_num);
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portEXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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}
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@ -108,6 +108,7 @@ TEST_CASE("Scheduler disabled can handle a pending context switch on resume", "[
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// When we resume scheduler, we expect the counter task
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// When we resume scheduler, we expect the counter task
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// will preempt and count at least one more item
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// will preempt and count at least one more item
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esp_intr_noniram_enable();
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esp_intr_noniram_enable();
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timer_enable_intr(TIMER_GROUP_0, TIMER_0);
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xTaskResumeAll();
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xTaskResumeAll();
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TEST_ASSERT_NOT_EQUAL(count_config.counter, no_sched_task);
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TEST_ASSERT_NOT_EQUAL(count_config.counter, no_sched_task);
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@ -42,7 +42,7 @@ xQueueHandle timer_queue;
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static void inline print_timer_counter(uint64_t counter_value)
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static void inline print_timer_counter(uint64_t counter_value)
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{
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{
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printf("Counter: 0x%08x%08x\n", (uint32_t) (counter_value >> 32),
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printf("Counter: 0x%08x%08x\n", (uint32_t) (counter_value >> 32),
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(uint32_t) (counter_value));
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(uint32_t) (counter_value));
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printf("Time : %.8f s\n", (double) counter_value / TIMER_SCALE);
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printf("Time : %.8f s\n", (double) counter_value / TIMER_SCALE);
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}
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}
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@ -62,7 +62,7 @@ void IRAM_ATTR timer_group0_isr(void *para)
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from the timer that reported the interrupt */
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from the timer that reported the interrupt */
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uint32_t intr_status = TIMERG0.int_st_timers.val;
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uint32_t intr_status = TIMERG0.int_st_timers.val;
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TIMERG0.hw_timer[timer_idx].update = 1;
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TIMERG0.hw_timer[timer_idx].update = 1;
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uint64_t timer_counter_value =
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uint64_t timer_counter_value =
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((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32
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((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32
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| TIMERG0.hw_timer[timer_idx].cnt_low;
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| TIMERG0.hw_timer[timer_idx].cnt_low;
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@ -103,17 +103,17 @@ void IRAM_ATTR timer_group0_isr(void *para)
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* auto_reload - should the timer auto reload on alarm?
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* auto_reload - should the timer auto reload on alarm?
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* timer_interval_sec - the interval of alarm to set
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* timer_interval_sec - the interval of alarm to set
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*/
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*/
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static void example_tg0_timer_init(int timer_idx,
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static void example_tg0_timer_init(int timer_idx,
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bool auto_reload, double timer_interval_sec)
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bool auto_reload, double timer_interval_sec)
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{
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{
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/* Select and initialize basic parameters of the timer */
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/* Select and initialize basic parameters of the timer */
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timer_config_t config;
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timer_config_t config = {
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config.divider = TIMER_DIVIDER;
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.divider = TIMER_DIVIDER,
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config.counter_dir = TIMER_COUNT_UP;
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.counter_dir = TIMER_COUNT_UP,
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config.counter_en = TIMER_PAUSE;
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.counter_en = TIMER_PAUSE,
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config.alarm_en = TIMER_ALARM_EN;
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.alarm_en = TIMER_ALARM_EN,
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config.intr_type = TIMER_INTR_LEVEL;
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.auto_reload = auto_reload,
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config.auto_reload = auto_reload;
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}; // default clock source is APB
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timer_init(TIMER_GROUP_0, timer_idx, &config);
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timer_init(TIMER_GROUP_0, timer_idx, &config);
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/* Timer's counter will initially start from value below.
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/* Timer's counter will initially start from value below.
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@ -123,8 +123,8 @@ static void example_tg0_timer_init(int timer_idx,
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/* Configure the alarm value and the interrupt on alarm. */
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/* Configure the alarm value and the interrupt on alarm. */
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timer_set_alarm_value(TIMER_GROUP_0, timer_idx, timer_interval_sec * TIMER_SCALE);
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timer_set_alarm_value(TIMER_GROUP_0, timer_idx, timer_interval_sec * TIMER_SCALE);
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timer_enable_intr(TIMER_GROUP_0, timer_idx);
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timer_enable_intr(TIMER_GROUP_0, timer_idx);
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timer_isr_register(TIMER_GROUP_0, timer_idx, timer_group0_isr,
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timer_isr_register(TIMER_GROUP_0, timer_idx, timer_group0_isr,
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(void *) timer_idx, ESP_INTR_FLAG_IRAM, NULL);
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(void *) timer_idx, ESP_INTR_FLAG_IRAM, NULL);
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timer_start(TIMER_GROUP_0, timer_idx);
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timer_start(TIMER_GROUP_0, timer_idx);
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}
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}
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