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Merge branch 'feature/update_efuses_for_esp32s2_v4.2' into 'release/v4.2'

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efuse(esp32s2): Added flash_ver, psram_ver, pkg_ver efuses (v4.2)

See merge request espressif/esp-idf!14771
This commit is contained in:
Zim Kalinowski 2021-08-19 06:28:50 +00:00
commit f075275cd1
4 changed files with 60 additions and 32 deletions
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35
components/efuse/esp32s2/esp_efuse_table.c
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@ -17,7 +17,7 @@
#include <assert.h> #include <assert.h>
#include "esp_efuse_table.h" #include "esp_efuse_table.h"
// md5_digest_table d9cd89987a033ef74503daeb4dd8dd07 // md5_digest_table c345ec20bb033bf5d071108ae644b54c
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file // If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -388,16 +388,20 @@ static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A, {EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
}; };
static const esp_efuse_desc_t PKG_VERSION[] = { static const esp_efuse_desc_t FLASH_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32, {EFUSE_BLK1, 117, 4}, // Flash_version,
}; };
static const esp_efuse_desc_t BLOCK1_VERSION[] = { static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version 0:No calibration 1:With calibration, {EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
}; };
static const esp_efuse_desc_t SYS_DATA_PART0[] = { static const esp_efuse_desc_t PSRAM_VERSION[] = {
{EFUSE_BLK1, 126, 66}, // System configuration, {EFUSE_BLK1, 124, 4}, // PSRAM version,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 128, 4}, // Package version,
}; };
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
@ -405,7 +409,7 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
}; };
static const esp_efuse_desc_t BLOCK2_VERSION[] = { static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2, {EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
}; };
static const esp_efuse_desc_t USER_DATA[] = { static const esp_efuse_desc_t USER_DATA[] = {
@ -899,18 +903,23 @@ const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
NULL NULL
}; };
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
&PKG_VERSION[0], // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32 &FLASH_VERSION[0], // Flash_version
NULL NULL
}; };
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version 0:No calibration 1:With calibration &BLOCK1_VERSION[0], // BLOCK1 efuse version
NULL NULL
}; };
const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = { const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[] = {
&SYS_DATA_PART0[0], // System configuration &PSRAM_VERSION[0], // PSRAM version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // Package version
NULL NULL
}; };
@ -920,7 +929,7 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
}; };
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2 &BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
NULL NULL
}; };

10
components/efuse/esp32s2/esp_efuse_table.csv
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@ -124,14 +124,16 @@
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
PKG_VERSION, EFUSE_BLK1, 117, 4, Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32 FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version 0:No calibration 1:With calibration BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version
SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
# SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve)
# SYS_DATA_PART1 BLOCK# - System configuration # SYS_DATA_PART1 BLOCK# - System configuration
####################### #######################
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2 BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
################ ################
USER_DATA, EFUSE_BLK3, 0, 256, User data USER_DATA, EFUSE_BLK3, 0, 256, User data

Can't render this file because it contains an unexpected character in line 7 and column 87.

7
components/efuse/esp32s2/include/esp_efuse_table.h
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@ -17,7 +17,7 @@ extern "C" {
#endif #endif
// md5_digest_table d9cd89987a033ef74503daeb4dd8dd07 // md5_digest_table c345ec20bb033bf5d071108ae644b54c
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file // If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -114,9 +114,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];

40
components/soc/soc/esp32s2/include/soc/efuse_reg.h
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@ -917,12 +917,24 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_1_S 0 #define EFUSE_SPI_PAD_CONF_1_S 0
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) #define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ /* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: Stores the fist 14 bits of the zeroth part of system data.*/ /*description: PSRAM version */
#define EFUSE_SYS_DATA_PART0_0 0x00003FFF #define EFUSE_PSRAM_VERSION 0x0000000F
#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) #define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S))
#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF #define EFUSE_PSRAM_VERSION_V 0xF
#define EFUSE_SYS_DATA_PART0_0_S 18 #define EFUSE_PSRAM_VERSION_S 28
/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Flash version */
#define EFUSE_FLASH_VERSION 0x0000000F
#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S))
#define EFUSE_FLASH_VERSION_V 0xF
#define EFUSE_FLASH_VERSION_S 21
/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: WAFER version 0:A */
#define EFUSE_WAFER_VERSION 0x00000007
#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
#define EFUSE_WAFER_VERSION_V 0x7
#define EFUSE_WAFER_VERSION_S 18
/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ /* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
/*description: Stores the second part of SPI_PAD_CONF.*/ /*description: Stores the second part of SPI_PAD_CONF.*/
#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF #define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
@ -931,12 +943,18 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_2_S 0 #define EFUSE_SPI_PAD_CONF_2_S 0
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) #define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054)
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */
/*description: Stores the fist 32 bits of the zeroth part of system data.*/ /*description: Stores the fist 32 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) #define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_S 0 #define EFUSE_SYS_DATA_PART0_1_S 4
/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: Package version */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 0
#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) #define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058)
/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@ -2298,5 +2316,3 @@ extern "C" {
#endif /*_SOC_EFUSE_REG_H_ */ #endif /*_SOC_EFUSE_REG_H_ */