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Merge branch 'feature/update_efuses_for_esp32s2_v4.2' into 'release/v4.2'
efuse(esp32s2): Added flash_ver, psram_ver, pkg_ver efuses (v4.2) See merge request espressif/esp-idf!14771
This commit is contained in:
commit
f075275cd1
@ -17,7 +17,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table d9cd89987a033ef74503daeb4dd8dd07
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// md5_digest_table c345ec20bb033bf5d071108ae644b54c
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -388,16 +388,20 @@ static const esp_efuse_desc_t WAFER_VERSION[] = {
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{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
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};
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static const esp_efuse_desc_t PKG_VERSION[] = {
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{EFUSE_BLK1, 117, 4}, // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32,
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static const esp_efuse_desc_t FLASH_VERSION[] = {
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{EFUSE_BLK1, 117, 4}, // Flash_version,
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};
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static const esp_efuse_desc_t BLOCK1_VERSION[] = {
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{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version 0:No calibration 1:With calibration,
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{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
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};
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static const esp_efuse_desc_t SYS_DATA_PART0[] = {
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{EFUSE_BLK1, 126, 66}, // System configuration,
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static const esp_efuse_desc_t PSRAM_VERSION[] = {
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{EFUSE_BLK1, 124, 4}, // PSRAM version,
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};
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static const esp_efuse_desc_t PKG_VERSION[] = {
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{EFUSE_BLK1, 128, 4}, // Package version,
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};
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static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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@ -405,7 +409,7 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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};
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static const esp_efuse_desc_t BLOCK2_VERSION[] = {
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{EFUSE_BLK2, 132, 3}, // Version of BLOCK2,
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{EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
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};
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static const esp_efuse_desc_t USER_DATA[] = {
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@ -899,18 +903,23 @@ const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
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&PKG_VERSION[0], // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
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const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
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&FLASH_VERSION[0], // Flash_version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
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&BLOCK1_VERSION[0], // BLOCK1 efuse version 0:No calibration 1:With calibration
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&BLOCK1_VERSION[0], // BLOCK1 efuse version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = {
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&SYS_DATA_PART0[0], // System configuration
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const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[] = {
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&PSRAM_VERSION[0], // PSRAM version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
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&PKG_VERSION[0], // Package version
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NULL
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};
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@ -920,7 +929,7 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
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};
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const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
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&BLOCK2_VERSION[0], // Version of BLOCK2
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&BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
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NULL
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};
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@ -124,14 +124,16 @@
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SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
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SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
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WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
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PKG_VERSION, EFUSE_BLK1, 117, 4, Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
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BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version 0:No calibration 1:With calibration
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SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration
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FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
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BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version
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PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
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PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
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# SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve)
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# SYS_DATA_PART1 BLOCK# - System configuration
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#######################
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OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
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BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2
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BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
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################
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USER_DATA, EFUSE_BLK3, 0, 256, User data
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Can't render this file because it contains an unexpected character in line 7 and column 87.
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@ -17,7 +17,7 @@ extern "C" {
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#endif
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// md5_digest_table d9cd89987a033ef74503daeb4dd8dd07
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// md5_digest_table c345ec20bb033bf5d071108ae644b54c
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -114,9 +114,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
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@ -917,12 +917,24 @@ extern "C" {
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#define EFUSE_SPI_PAD_CONF_1_S 0
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#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
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/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
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/*description: Stores the fist 14 bits of the zeroth part of system data.*/
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#define EFUSE_SYS_DATA_PART0_0 0x00003FFF
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#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
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#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF
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#define EFUSE_SYS_DATA_PART0_0_S 18
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/* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */
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/*description: PSRAM version */
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#define EFUSE_PSRAM_VERSION 0x0000000F
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#define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S))
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#define EFUSE_PSRAM_VERSION_V 0xF
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#define EFUSE_PSRAM_VERSION_S 28
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/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
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/*description: Flash version */
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#define EFUSE_FLASH_VERSION 0x0000000F
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#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S))
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#define EFUSE_FLASH_VERSION_V 0xF
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#define EFUSE_FLASH_VERSION_S 21
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/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
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/*description: WAFER version 0:A */
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#define EFUSE_WAFER_VERSION 0x00000007
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#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
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#define EFUSE_WAFER_VERSION_V 0x7
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#define EFUSE_WAFER_VERSION_S 18
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/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
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/*description: Stores the second part of SPI_PAD_CONF.*/
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#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
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@ -931,12 +943,18 @@ extern "C" {
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#define EFUSE_SPI_PAD_CONF_2_S 0
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#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054)
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/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */
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/*description: Stores the fist 32 bits of the zeroth part of system data.*/
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#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF
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#define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF
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#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
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#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF
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#define EFUSE_SYS_DATA_PART0_1_S 0
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#define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF
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#define EFUSE_SYS_DATA_PART0_1_S 4
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/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */
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/*description: Package version */
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#define EFUSE_PKG_VERSION 0x0000000F
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#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
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#define EFUSE_PKG_VERSION_V 0xF
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#define EFUSE_PKG_VERSION_S 0
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#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058)
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/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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@ -2298,5 +2316,3 @@ extern "C" {
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#endif /*_SOC_EFUSE_REG_H_ */
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