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https://github.com/espressif/esp-idf.git
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ESP32C3: auto adjust voltage dbias storing in efuse and open glitch reset for ECO3
1. add some efuse api to get rtc & digital voltage 2. set dig_rtc voltage to a fix value storing in efuse no mater which cpu frequency 3. modify hardware code in bootloader to fit all c3 ECO3 version
This commit is contained in:
parent
f975329429
commit
eea76d14bb
@ -275,10 +275,15 @@ static inline void bootloader_hardware_init(void)
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static inline void bootloader_glitch_reset_disable(void)
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{
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = bootloader_common_get_chip_revision();
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if (chip_version < 2) {
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
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} else {
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} else if (chip_version == 2) {
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
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}
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}
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@ -17,7 +17,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59
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// md5_digest_table 61baa79d296df996c838bc2adc1837e5
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -484,6 +484,30 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = {
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{EFUSE_BLK10, 0, 256}, // System configuration,
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};
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static const esp_efuse_desc_t K_RTC_LDO[] = {
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{EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO,
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};
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static const esp_efuse_desc_t K_DIG_LDO[] = {
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{EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO,
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};
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static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
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{EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20,
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};
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static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
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{EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20,
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};
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static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
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{EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt,
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};
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static const esp_efuse_desc_t THRES_HVT[] = {
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{EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt,
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};
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@ -1062,3 +1086,33 @@ const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
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&SYS_DATA_PART2[0], // System configuration
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
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&K_RTC_LDO[0], // BLOCK1 K_RTC_LDO
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
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&K_DIG_LDO[0], // BLOCK1 K_DIG_LDO
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
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&V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
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&V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
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&DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = {
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&THRES_HVT[0], // BLOCK1 pvt threshold when hvt
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NULL
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};
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@ -153,3 +153,12 @@ KEY3, EFUSE_BLK7, 0, 256, Key3 or us
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KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
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KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
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SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
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# AUTO CONFIG DIG&RTC DBIAS#
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################
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K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
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K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO
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V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20
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V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
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DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt
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THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt
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Can't render this file because it contains an unexpected character in line 7 and column 87.
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@ -17,7 +17,7 @@ extern "C" {
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#endif
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// md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59
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// md5_digest_table 61baa79d296df996c838bc2adc1837e5
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -138,6 +138,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
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extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
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extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
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extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
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extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
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#ifdef __cplusplus
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}
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@ -121,18 +121,6 @@ bool rtc_clk_8md256_enabled(void)
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
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}
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static void wait_dig_dbias_valid(uint64_t rtc_cycles)
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{
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rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) {
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cal_clk = RTC_CAL_8MD256;
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}
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rtc_clk_cal(cal_clk, rtc_cycles);
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}
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void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
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@ -292,24 +280,15 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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*/
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
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int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
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int dbias = DIG_DBIAS_80M;
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int per_conf = DPORT_CPUPERIOD_SEL_80;
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if (cpu_freq_mhz == 80) {
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/* nothing to do */
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} else if (cpu_freq_mhz == 160) {
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dbias = DIG_DBIAS_160M;
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per_conf = DPORT_CPUPERIOD_SEL_160;
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} else {
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SOC_LOGE(TAG, "invalid frequency");
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abort();
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}
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
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if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M)
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|| (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) && (0 == origin_cpuperiod_sel)))) {
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wait_dig_dbias_valid(2);
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}
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REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
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@ -457,18 +436,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
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*/
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void rtc_clk_cpu_freq_to_xtal(int freq, int div)
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{
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int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
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int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT);
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ets_update_cpu_frequency(freq);
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/* lower the voltage */
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if (freq <= 2) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M);
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} else {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
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}
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if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 0)) {
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wait_dig_dbias_valid(2);
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}
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/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1);
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@ -480,13 +448,7 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
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int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT);
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ets_update_cpu_frequency(8);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
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if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 4)) {
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wait_dig_dbias_valid(2);
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}
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
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REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
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rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
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@ -31,6 +31,7 @@ static const char *TAG = "rtc_init";
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static void set_ocode_by_efuse(int calib_version);
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static void calibrate_ocode(void);
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static void set_rtc_dig_dbias(void);
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void rtc_init(rtc_config_t cfg)
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{
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@ -55,9 +56,21 @@ void rtc_init(rtc_config_t cfg)
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
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/* Reset RTC bias to default value (needed if waking up from deep sleep) */
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10);
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if (cfg.cali_ocode) {
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uint32_t rtc_calib_version = 0;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
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if (err != ESP_OK) {
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rtc_calib_version = 0;
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SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
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}
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if (rtc_calib_version == 1) {
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set_ocode_by_efuse(rtc_calib_version);
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} else {
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calibrate_ocode();
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}
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}
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set_rtc_dig_dbias();
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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@ -138,16 +151,6 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
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}
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if (cfg.cali_ocode) {
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uint32_t rtc_calib_version = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
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if (rtc_calib_version == 1) {
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set_ocode_by_efuse(rtc_calib_version);
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} else {
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calibrate_ocode();
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}
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}
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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}
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@ -195,7 +198,9 @@ static void set_ocode_by_efuse(int calib_version)
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assert(calib_version == 1);
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// use efuse ocode.
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uint32_t ocode;
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ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8));
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
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assert(err == ESP_OK);
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(void) err;
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
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}
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@ -250,3 +255,85 @@ static void calibrate_ocode(void)
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}
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rtc_clk_cpu_freq_set_config(&old_config);
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}
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static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
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{
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assert(chip_version >= 3);
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uint32_t dig_dbias = 28;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
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if (err != ESP_OK) {
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dig_dbias = 28;
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SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
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}
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return dig_dbias;
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}
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uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
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{
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assert(chip_version >= 3);
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uint32_t rtc_dbias = 0;
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signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
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esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
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esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
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esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
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esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
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if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
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k_rtc_ldo = 0;
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k_dig_ldo = 0;
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v_rtc_bias20 = 0;
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v_dig_bias20 = 0;
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SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
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}
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k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
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k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
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v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
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v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
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uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
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uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
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signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
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signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
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uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
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uint32_t v_rtc_nearest_1v15_mul10000 = 0;
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for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) {
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v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
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if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
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break;
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}
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return rtc_dbias;
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}
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static void set_rtc_dig_dbias()
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{
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/*
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1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
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2. also we store some value in efuse, include:
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k_rtc_ldo (slope of rtc voltage & rtc_dbias);
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k_dig_ldo (slope of digital voltage & digital_dbias);
|
||||
v_rtc_bias20 (rtc voltage when rtc dbais is 20);
|
||||
v_dig_bias20 (digital voltage when digital dbais is 20).
|
||||
3. a reasonable rtc_dbias can be calculated by a certion formula.
|
||||
*/
|
||||
uint32_t rtc_dbias = 28, dig_dbias = 28;
|
||||
uint8_t chip_version = esp_efuse_get_chip_ver();
|
||||
if (chip_version >= 3) {
|
||||
dig_dbias = get_dig_dbias_by_efuse(chip_version);
|
||||
if (dig_dbias != 0) {
|
||||
if (dig_dbias + 4 > 28) {
|
||||
dig_dbias = 28;
|
||||
} else {
|
||||
dig_dbias += 4;
|
||||
}
|
||||
rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
|
||||
} else {
|
||||
dig_dbias = 28;
|
||||
SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
|
||||
}
|
||||
}
|
||||
else {
|
||||
SOC_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
|
||||
}
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
|
||||
}
|
||||
|
@ -120,9 +120,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
|
||||
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
|
||||
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak);
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak);
|
||||
|
||||
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
|
||||
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
|
||||
|
@ -122,6 +122,15 @@ set sleep_init default param
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
|
Loading…
Reference in New Issue
Block a user