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Merge branch 'bugfix/esp_rom_clic_thresh_bug_v5.3' into 'release/v5.3'

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fix(rom): fixed esprv_int_set_threshold on C5/C61 (v5.3)

See merge request espressif/esp-idf!31490
This commit is contained in:
Jiang Jiang Jian 2024-06-13 18:57:18 +08:00
commit edc2bd8aab
5 changed files with 16 additions and 3 deletions
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2
components/esp_rom/CMakeLists.txt
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@ -69,7 +69,7 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL)
list(APPEND sources "patches/esp_rom_wdt.c") list(APPEND sources "patches/esp_rom_wdt.c")
endif() endif()
if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH) if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH OR CONFIG_ESP_ROM_CLIC_INT_THRESH_PATCH)
list(APPEND sources "patches/esp_rom_clic.c") list(APPEND sources "patches/esp_rom_clic.c")
endif() endif()

4
components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in
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@ -82,3 +82,7 @@ config ESP_ROM_HAS_VERSION
config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
bool bool
default y default y
config ESP_ROM_CLIC_INT_THRESH_PATCH
bool
default y

1
components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h
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@ -28,3 +28,4 @@
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information
#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF

1
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld
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@ -276,7 +276,6 @@ gpio_pad_hold = 0x40000740;
/* Functions */ /* Functions */
esprv_intc_int_set_priority = 0x40000744; esprv_intc_int_set_priority = 0x40000744;
esprv_intc_int_set_threshold = 0x40000748;
esprv_intc_int_enable = 0x4000074c; esprv_intc_int_enable = 0x4000074c;
esprv_intc_int_disable = 0x40000750; esprv_intc_int_disable = 0x40000750;
esprv_intc_int_set_type = 0x40000754; esprv_intc_int_set_type = 0x40000754;

11
components/esp_rom/patches/esp_rom_clic.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -7,6 +7,7 @@
#include "esp_rom_caps.h" #include "esp_rom_caps.h"
#include "soc/clic_reg.h" #include "soc/clic_reg.h"
#include "riscv/interrupt.h" #include "riscv/interrupt.h"
#include "riscv/rv_utils.h"
#if ESP_ROM_CLIC_INT_TYPE_PATCH #if ESP_ROM_CLIC_INT_TYPE_PATCH
@ -20,3 +21,11 @@ void esprv_int_set_type(int rv_int_num, enum intr_type type)
REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG, type); REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG, type);
} }
#endif #endif
#if ESP_ROM_CLIC_INT_THRESH_PATCH
void esprv_int_set_threshold(int priority_threshold)
{
/* ROM functions assume minimum MINTTHRESH is 0x1F, but it is actually 0xF */
rv_utils_set_intlevel(priority_threshold);
}
#endif //ESP_ROM_CLIC_INT_THRESH_PATCH