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component/esp32 : update rtc phy lib
RTC V230 add BT AGC saturation protection, replace RTC V229. PHY V362 Power up print: "phy_version: 362.0, 61e8d92, Sep 8 2017, 18:48:13" 1. esp_init_data_v3.bin modify TX target power modify WIFI & BT RX gain table 2. modify phy_close_rf() 3. add phy_set_most_tpw() 4. 26M crystal work OK 5. noise_check_loop ok
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@ -135,7 +135,9 @@ typedef struct {
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uint8_t spur_freq_cfg_div_3; /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_3 */
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uint8_t spur_freq_en_h_3; /*!< the seventh bit for total enable */
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uint8_t spur_freq_en_l_3; /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority, */
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uint8_t reserved[23]; /*!< reserved for future expansion */
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uint8_t force_freq_offset_enable;
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uint8_t force_freq_offset_num;
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uint8_t reserved[21]; /*!< reserved for future expansion */
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} esp_phy_init_data_t;
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/**
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@ -1 +1 @@
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Subproject commit de415111bd45cbc4147bfe5f6d4fcdc757b7748c
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Subproject commit f607c800b2ffc12ed88d0cbaf2d3d784aa1ce928
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@ -27,13 +27,13 @@ static const char phy_init_magic_pre[] = PHY_INIT_MAGIC;
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* @brief Structure containing default recommended PHY initialization parameters.
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*/
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static const esp_phy_init_data_t phy_init_data= {
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.param_ver_id = 1,
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.param_ver_id = 3,
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.crystal_select = 3,
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.wifi_rx_gain_swp_step_1 = 0x05,
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.wifi_rx_gain_swp_step_2 = 0x04,
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.wifi_rx_gain_swp_step_2 = 0x09,
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.wifi_rx_gain_swp_step_3 = 0x06,
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.wifi_rx_gain_swp_step_4 = 0x05,
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.wifi_rx_gain_swp_step_5 = 0x01,
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.wifi_rx_gain_swp_step_5 = 0x03,
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.wifi_rx_gain_swp_step_6 = 0x06,
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.wifi_rx_gain_swp_step_7 = 0x05,
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.wifi_rx_gain_swp_step_8 = 0x04,
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@ -45,10 +45,10 @@ static const esp_phy_init_data_t phy_init_data= {
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.wifi_rx_gain_swp_step_14 = 0x00,
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.wifi_rx_gain_swp_step_15 = 0x00,
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.bt_rx_gain_swp_step_1 = 0x05,
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.bt_rx_gain_swp_step_2 = 0x04,
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.bt_rx_gain_swp_step_2 = 0x09,
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.bt_rx_gain_swp_step_3 = 0x06,
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.bt_rx_gain_swp_step_4 = 0x05,
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.bt_rx_gain_swp_step_5 = 0x01,
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.bt_rx_gain_swp_step_5 = 0x03,
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.bt_rx_gain_swp_step_6 = 0x06,
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.bt_rx_gain_swp_step_7 = 0x05,
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.bt_rx_gain_swp_step_8 = 0x00,
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@ -59,9 +59,9 @@ static const esp_phy_init_data_t phy_init_data= {
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.bt_rx_gain_swp_step_13 = 0x00,
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.bt_rx_gain_swp_step_14 = 0x00,
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.bt_rx_gain_swp_step_15 = 0x00,
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.gain_cmp_1 = 0x0a,
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.gain_cmp_6 = 0x0a,
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.gain_cmp_11 = 0x0c,
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.gain_cmp_1 = 0xfc,
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.gain_cmp_6 = 0xfc,
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.gain_cmp_11 = 0xfe,
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.gain_cmp_ext2_1 = 0xf0,
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.gain_cmp_ext2_6 = 0xf0,
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.gain_cmp_ext2_11 = 0xf0,
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@ -72,15 +72,15 @@ static const esp_phy_init_data_t phy_init_data= {
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.gain_cmp_bt_ofs_6 = 0x18,
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.gain_cmp_bt_ofs_11 = 0x18,
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.target_power_qdb_0 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 78),
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.target_power_qdb_1 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 76),
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.target_power_qdb_2 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 74),
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.target_power_qdb_3 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 68),
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.target_power_qdb_4 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
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.target_power_qdb_1 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 72),
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.target_power_qdb_2 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 66),
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.target_power_qdb_3 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
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.target_power_qdb_4 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 56),
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.target_power_qdb_5 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
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.target_power_index_mcs0 = 0,
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.target_power_index_mcs1 = 0,
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.target_power_index_mcs1 = 1,
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.target_power_index_mcs2 = 1,
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.target_power_index_mcs3 = 1,
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.target_power_index_mcs3 = 2,
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.target_power_index_mcs4 = 2,
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.target_power_index_mcs5 = 3,
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.target_power_index_mcs6 = 4,
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@ -132,6 +132,8 @@ static const esp_phy_init_data_t phy_init_data= {
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.spur_freq_cfg_div_3 = 0,
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.spur_freq_en_h_3 = 0,
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.spur_freq_en_l_3 = 0,
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.force_freq_offset_enable = 0,
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.force_freq_offset_num = 0,
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.reserved = {0}
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};
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