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driver(uart): fix uart module reset issue (release/v4.1)

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On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue,

  while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory

  before the software reset to solve this problem.
This commit is contained in:
houwenxiang 2020-05-01 20:40:24 +08:00 committed by Michael (XIAO Xufeng)
parent f68b6e6c60
commit eda943b7c5
2 changed files with 3 additions and 1 deletions
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2
components/esp32/system_api_esp32.c
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@ -102,7 +102,7 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset timer/spi/uart
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST);
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
// Set CPU back to XTAL source, no PLL, same as hard reset

2
components/soc/esp32/include/hal/uart_ll.h
View File

@ -215,6 +215,8 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
/**
* @brief Reset the UART hw txfifo.
*
* Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo.
*
* @param hw Beginning address of the peripheral registers.
*
* @return None