From ecca6fb1c2d4e53da824d828833be2640ec86f06 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 6 Dec 2023 20:37:28 +0800 Subject: [PATCH] change(esp_hw_support/sleep): rename ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY 1. Rename ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY to ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2. Set ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY visible for all targets --- components/esp_hw_support/Kconfig | 34 ++++++++++++------- .../esp_hw_support/sdkconfig.rename.esp32 | 3 +- .../esp_hw_support/sdkconfig.rename.esp32s3 | 3 +- components/esp_hw_support/sleep_modes.c | 23 ++++++------- tools/ldgen/samples/sdkconfig | 2 +- 5 files changed, 37 insertions(+), 28 deletions(-) diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index a7459afd23..5aa11dc938 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -143,24 +143,34 @@ menu "Hardware Settings" This option provides a software workaround for this issue. Configure to isolate all GPIO pins in sleep state. - config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY - int "Extra delay in deep sleep wake stub (in us)" - depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 - default 2000 + config ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY + int "Extra delay (in us) after flash powerdown sleep wakeup to wait flash ready" + default 2000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 + default 0 range 0 5000 help - When the chip exits deep sleep, the CPU and the flash chip are powered on - at the same time. CPU will run deep sleep stub first, and then - proceed to load code from flash. Some flash chips need sufficient - time to pass between power on and first read operation. By default, - without any extra delay, this time is approximately 900us, although + When the chip exits sleep, the CPU and the flash chip are powered on at the same time. + CPU will run rom code (deepsleep) or ram code (lightsleep) first, and then load or execute + code from flash. + + Some flash chips need sufficient time to pass between power on and first read operation. + By default, without any extra delay, this time is approximately 900us, although some flash chip types need more than that. - By default extra delay is set to 2000us. When optimizing startup time + (!!! Please adjust this value according to the Data Sheet of SPI Flash used in your project.) + In Flash Data Sheet, the parameters that define the Flash ready timing after power-up (minimum + time from Vcc(min) to CS activeare) usually named tVSL in ELECTRICAL CHARACTERISTICS chapter, + and the configuration value here should be: + ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY = tVSL - 900 + + For esp32 and esp32s3, the default extra delay is set to 2000us. When optimizing startup time for applications which require it, this value may be reduced. - If you are seeing "flash read err, 1000" message printed to the - console after deep sleep reset, try increasing this value. + If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset + on esp32, or triggered RTC_WDT/LP_WDT after lightsleep wakeup, try increasing this value. + (For esp32, the delay will be executed in both deep sleep and light sleep wake up flow. + For chips after esp32, the delay will be executed only in light sleep flow, the delay + controlled by the EFUSE_FLASH_TPUW in ROM will be executed in deepsleep wake up flow.) config ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS bool "Allow to enable internal pull-up/downs for the Deep-Sleep wakeup IOs" diff --git a/components/esp_hw_support/sdkconfig.rename.esp32 b/components/esp_hw_support/sdkconfig.rename.esp32 index 91bac13a64..058f851538 100644 --- a/components/esp_hw_support/sdkconfig.rename.esp32 +++ b/components/esp_hw_support/sdkconfig.rename.esp32 @@ -21,7 +21,8 @@ CONFIG_SPIRAM_SUPPORT CONFIG_SPIRAM CONFIG_ESP32_SPIRAM_SUPPORT CONFIG_SPIRAM CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP -CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY CONFIG_ESP32_XTAL_FREQ_26 CONFIG_XTAL_FREQ_26 CONFIG_ESP32_XTAL_FREQ_40 CONFIG_XTAL_FREQ_40 diff --git a/components/esp_hw_support/sdkconfig.rename.esp32s3 b/components/esp_hw_support/sdkconfig.rename.esp32s3 index 77e595a907..39a3d34cca 100644 --- a/components/esp_hw_support/sdkconfig.rename.esp32s3 +++ b/components/esp_hw_support/sdkconfig.rename.esp32s3 @@ -10,4 +10,5 @@ CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RE CONFIG_ESP32S3_SPIRAM_SUPPORT CONFIG_SPIRAM -CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 3b87c290c1..b6f30498b8 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -114,8 +114,8 @@ // If light sleep time is less than that, don't power down flash #define FLASH_PD_MIN_SLEEP_TIME_US 2000 -// Time from VDD_SDIO power up to first flash read in ROM code -#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700 +// Default waiting time for the software to wait for Flash ready after waking up from sleep +#define ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US 700 // Cycles for RTC Timer clock source (internal oscillator) calibrate #define RTC_CLK_SRC_CAL_CYCLES (10) @@ -164,12 +164,6 @@ #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) #endif -#if CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY -#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY -#else -#define DEEP_SLEEP_WAKEUP_DELAY 0 -#endif - // Minimal amount of time we can sleep for #define LIGHT_SLEEP_MIN_TIME_US 200 @@ -353,13 +347,16 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR); _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG, _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR)); -#if DEEP_SLEEP_WAKEUP_DELAY > 0 +#if CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY > 0 // ROM code has not started yet, so we need to set delay factor // used by esp_rom_delay_us first. ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000); - // This delay is configured in menuconfig, it can be used to give - // the flash chip some time to become ready. - esp_rom_delay_us(DEEP_SLEEP_WAKEUP_DELAY); + // Time from VDD_SDIO power up to first flash read in ROM code is 700 us, + // for some flash chips is not sufficient, this delay is configured in menuconfig, + // it can be used to give the flash chip some extra time to become ready. + // For later chips, we have EFUSE_FLASH_TPUW field to configure it and do + // this delay in the ROM. + esp_rom_delay_us(CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY); #endif #elif CONFIG_IDF_TARGET_ESP32S2 REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN); @@ -1106,7 +1103,7 @@ esp_err_t esp_light_sleep_start(void) // Decide if VDD_SDIO needs to be powered down; // If it needs to be powered down, adjust sleep time. - const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + DEEP_SLEEP_WAKEUP_DELAY; + const uint32_t flash_enable_time_us = ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US + CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY; /** * If VDD_SDIO power domain is requested to be turned off, bit `RTC_SLEEP_PD_VDDSDIO` diff --git a/tools/ldgen/samples/sdkconfig b/tools/ldgen/samples/sdkconfig index ed107d9dc7..6f3fd92aef 100644 --- a/tools/ldgen/samples/sdkconfig +++ b/tools/ldgen/samples/sdkconfig @@ -184,7 +184,7 @@ CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_RTC_CLK_SRC_EXT_CRYS= CONFIG_RTC_CLK_CAL_CYCLES=1024 CONFIG_RTC_XTAL_BOOTSTRAP_CYCLES=100 -CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=2000 CONFIG_XTAL_FREQ_40=y CONFIG_XTAL_FREQ_26= CONFIG_XTAL_FREQ_AUTO=