alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'bugfix/rng_disabled_wifi_stop_2' into 'master'

Browse Source 
esp32: Fix hardware rng after esp_wifi_stop (second implementation)

Ensures hardware RNG remains enabled at all times.

Reworked  version of !534

See merge request !536
This commit is contained in:
Ivan Grokhotkov 2017-03-02 10:51:30 +08:00
commit ecbe5a66f2
4 changed files with 27 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
components/bootloader_support/src/bootloader_random.c
View File

@ -62,6 +62,11 @@ void bootloader_fill_random(void *buffer, size_t length)
void bootloader_random_enable(void) void bootloader_random_enable(void)
{ {
/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
never disabled while the CPU is running), this is a "belts and braces" type check.
*/
SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
reference via I2S into the RNG entropy input. reference via I2S into the RNG entropy input.

20
components/esp32/include/soc/dport_reg.h
View File

@ -1035,11 +1035,27 @@
#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF #define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_S 0 #define DPORT_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15 */
#define DPORT_WIFI_CLK_WIFI_EN 0x000007cf
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x1FF
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Remaining single bit clock masks */
#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13)
#define DPORT_WIFI_CLK_EMAC_EN BIT(14)
#define DPORT_WIFI_CLK_RNG_EN BIT(15)
#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) #define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */ /*description: */
#define DPROT_RW_BTLP_RST (BIT(10)) #define DPORT_RW_BTLP_RST (BIT(10))
#define DPROT_RW_BTMAC_RST (BIT(9)) #define DPORT_RW_BTMAC_RST (BIT(9))
#define DPORT_MACPWR_RST (BIT(8)) #define DPORT_MACPWR_RST (BIT(8))
#define DPORT_EMAC_RST (BIT(7)) #define DPORT_EMAC_RST (BIT(7))
#define DPORT_SDIO_HOST_RST (BIT(6)) #define DPORT_SDIO_HOST_RST (BIT(6))

6
components/esp32/phy_init.c
View File

@ -60,7 +60,7 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data,
} }
} }
// Enable WiFi peripheral clock // Enable WiFi peripheral clock
SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, 0x87cf); SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN | DPORT_WIFI_CLK_RNG_EN);
ESP_LOGV(TAG, "register_chipv7_phy, init_data=%p, cal_data=%p, mode=%d", ESP_LOGV(TAG, "register_chipv7_phy, init_data=%p, cal_data=%p, mode=%d",
init_data, calibration_data, mode); init_data, calibration_data, mode);
phy_set_wifi_mode_only(0); phy_set_wifi_mode_only(0);
@ -84,8 +84,8 @@ esp_err_t esp_phy_rf_deinit(void)
if (s_phy_rf_init_count == 1) { if (s_phy_rf_init_count == 1) {
// Disable PHY and RF. // Disable PHY and RF.
phy_close_rf(); phy_close_rf();
// Disable WiFi peripheral clock. Do not disable clock for generating random number. // Disable WiFi peripheral clock. Do not disable clock for hardware RNG
CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, 0x874f); CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
} else { } else {
#if CONFIG_SW_COEXIST_ENABLE #if CONFIG_SW_COEXIST_ENABLE
coex_deinit(); coex_deinit();

2
components/esp32/system_api.c
View File

@ -132,7 +132,7 @@ void IRAM_ATTR esp_restart_noos()
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
DPROT_RW_BTMAC_RST | DPROT_RW_BTLP_RST); DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
REG_WRITE(DPORT_CORE_RST_EN_REG, 0); REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart // Reset timer/spi/uart