From 4786f2d88af1d43c87cf2067d854fe194d60e244 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 7 Jun 2021 10:47:19 +0800 Subject: [PATCH] aes/sha/rsa: update registers for ESP32-S3 Updates register headers for ESP32-S3 and default crypto accelerators for S3 to enabled --- components/mbedtls/Kconfig | 3 - .../soc/esp32s3/include/soc/hwcrypto_reg.h | 94 +------------------ components/soc/esp32s3/include/soc/soc_caps.h | 22 ++--- 3 files changed, 8 insertions(+), 111 deletions(-) diff --git a/components/mbedtls/Kconfig b/components/mbedtls/Kconfig index 9770497391..13c8a01522 100644 --- a/components/mbedtls/Kconfig +++ b/components/mbedtls/Kconfig @@ -237,7 +237,6 @@ menu "mbedTLS" config MBEDTLS_HARDWARE_AES bool "Enable hardware AES acceleration" - default n if IDF_TARGET_ESP32S3 default y depends on !SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST help @@ -270,7 +269,6 @@ menu "mbedTLS" config MBEDTLS_HARDWARE_MPI bool "Enable hardware MPI (bignum) acceleration" - default n if IDF_TARGET_ESP32S3 default y depends on !SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST help @@ -283,7 +281,6 @@ menu "mbedTLS" config MBEDTLS_HARDWARE_SHA bool "Enable hardware SHA acceleration" - default n if IDF_TARGET_ESP32S3 default y depends on !SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST help diff --git a/components/soc/esp32s3/include/soc/hwcrypto_reg.h b/components/soc/esp32s3/include/soc/hwcrypto_reg.h index 97ce6e35b2..064100149a 100644 --- a/components/soc/esp32s3/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s3/include/soc/hwcrypto_reg.h @@ -43,15 +43,6 @@ #define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) #define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) -#define SHA_MODE_SHA1 0 -#define SHA_MODE_SHA224 1 -#define SHA_MODE_SHA256 2 -#define SHA_MODE_SHA384 3 -#define SHA_MODE_SHA512 4 -#define SHA_MODE_SHA512_224 5 -#define SHA_MODE_SHA512_256 6 -#define SHA_MODE_SHA512_T 7 - /* SHA acceleration registers */ #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) #define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04) @@ -68,15 +59,6 @@ #define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) #define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) -/* AES Block operation modes */ -#define AES_BLOCK_MODE_ECB 0 -#define AES_BLOCK_MODE_CBC 1 -#define AES_BLOCK_MODE_OFB 2 -#define AES_BLOCK_MODE_CTR 3 -#define AES_BLOCK_MODE_CFB8 4 -#define AES_BLOCK_MODE_CFB128 5 -#define AES_BLOCK_MODE_GCM 6 - /* AES Block operation modes (used with DMA) */ #define AES_BLOCK_MODE_ECB 0 #define AES_BLOCK_MODE_CBC 1 @@ -84,7 +66,6 @@ #define AES_BLOCK_MODE_CTR 3 #define AES_BLOCK_MODE_CFB8 4 #define AES_BLOCK_MODE_CFB128 5 -#define AES_BLOCK_MODE_GCM 6 /* AES acceleration registers */ #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) @@ -95,10 +76,8 @@ #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) -#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) -#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) #define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) -#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) #define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) #define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) #define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) @@ -115,49 +94,7 @@ #define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) #define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) #define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) -#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) -#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) -#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - -/* AES_STATE_REG values */ -#define AES_STATE_IDLE 0 -#define AES_STATE_BUSY 1 -#define AES_STATE_DONE 2 - - -/* Crypto DMA */ -#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) -#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) -#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) -#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) -#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) -#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) -#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) -#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) -#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) -#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) -#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) -#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) -#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) -#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) -#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) -#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) -#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) -#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) -#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) -#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) -#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) -#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) -#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) -#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) -#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) -#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) -#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) /* HMAC Module */ #define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) @@ -207,32 +144,3 @@ #define DS_QUERY_CHECK_INVALID_PADDING (1<<1) #define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) - -/* Crypto DMA */ -#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) -#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) -#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) -#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) -#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) -#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) -#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) -#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) -#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) -#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) -#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) -#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) -#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) -#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) -#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) -#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) -#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) -#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) -#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) -#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) -#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) -#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) -#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) -#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) -#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) -#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) -#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index c3f8cd0fc8..9a27c78e15 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -167,12 +167,6 @@ #define SOC_SHA_SUPPORT_SHA512_256 (1) #define SOC_SHA_SUPPORT_SHA512_T (1) -/* Supported HW algorithms */ -#define SOC_SHA_SUPPORT_SHA1 (1) -#define SOC_SHA_SUPPORT_SHA256 (1) -#define SOC_SHA_SUPPORT_SHA384 (1) -#define SOC_SHA_SUPPORT_SHA512 (1) - /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (4096) @@ -181,6 +175,13 @@ /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + + /*-------------------------- Power Management CAPS ---------------------------*/ #define SOC_PM_SUPPORT_EXT_WAKEUP (1) @@ -188,19 +189,10 @@ #define SOC_PM_SUPPORT_BT_WAKEUP (1) -/* Has a centralized DMA, which is shared with all peripherals */ -#define SOC_AES_GDMA (1) - -#define SOC_AES_SUPPORT_AES_128 (1) -#define SOC_AES_SUPPORT_AES_256 (1) /*-------------------------- Flash Encryption CAPS----------------------------*/ #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) -// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically -// Remove them when GDMA driver API is ready -#define SOC_GDMA_SHA_DMA_CHANNEL (3) -#define SOC_GDMA_AES_DMA_CHANNEL (4) /*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ #define SOC_WIFI_HW_TSF (1)