alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

fix(ahb_dma): temporarily disable ahb_dma on p4

Browse Source
This commit is contained in:
Armando 2023-07-11 15:39:26 +08:00
parent de3d690bde
commit ec88a3f018
6 changed files with 35 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
components/hal/esp32p4/include/ahb_dma_ll.h → components/hal/esp32p4/include/hal/ahb_dma_ll.h
View File

0
components/hal/esp32p4/include/axi_dma_ll.h → components/hal/esp32p4/include/hal/axi_dma_ll.h
View File

3
components/hal/esp32p4/include/gdma_ll.h → components/hal/esp32p4/include/hal/gdma_ll.h
View File

@ -19,6 +19,9 @@ extern "C" {
#define GDMA_LL_RX_EVENT_MASK (0x1F)
#define GDMA_LL_TX_EVENT_MASK (0x0F)
//To check this //TODO: IDF-6504
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
#define GDMA_LL_EVENT_TX_EOF (1<<1)

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -207,10 +207,6 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_ETM_GROUPS
int
default 1

62
components/soc/esp32p4/include/soc/ahb_dma_reg.h
View File

@ -3148,13 +3148,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c4)
/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH0_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH0_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH0 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH0_M (AHB_DMA_OUT_CRC_CLEAR_CH0_V << AHB_DMA_OUT_CRC_CLEAR_CH0_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH0_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH0_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@ -3277,13 +3277,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2ec)
/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH1_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH1_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH1 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH1_M (AHB_DMA_OUT_CRC_CLEAR_CH1_V << AHB_DMA_OUT_CRC_CLEAR_CH1_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH1_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH1_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@ -3406,15 +3406,15 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x314)
/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH2_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH2_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH2 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH2_M (AHB_DMA_OUT_CRC_CLEAR_CH2_V << AHB_DMA_OUT_CRC_CLEAR_CH2_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH2_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH2_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2 register
* This register is used to store ch0 crc result
*/
#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x318)
@ -3535,13 +3535,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x33c)
/** AHB_DMA_IN_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_M (AHB_DMA_IN_CRC_CLEAR_CH0_REG_V << AHB_DMA_IN_CRC_CLEAR_CH0_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH0 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH0_M (AHB_DMA_IN_CRC_CLEAR_CH0_V << AHB_DMA_IN_CRC_CLEAR_CH0_S)
#define AHB_DMA_IN_CRC_CLEAR_CH0_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH0_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@ -3664,13 +3664,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x364)
/** AHB_DMA_IN_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_M (AHB_DMA_IN_CRC_CLEAR_CH1_REG_V << AHB_DMA_IN_CRC_CLEAR_CH1_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH1 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH1_M (AHB_DMA_IN_CRC_CLEAR_CH1_V << AHB_DMA_IN_CRC_CLEAR_CH1_S)
#define AHB_DMA_IN_CRC_CLEAR_CH1_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH1_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@ -3793,13 +3793,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x38c)
/** AHB_DMA_IN_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_M (AHB_DMA_IN_CRC_CLEAR_CH2_REG_V << AHB_DMA_IN_CRC_CLEAR_CH2_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH2 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH2_M (AHB_DMA_IN_CRC_CLEAR_CH2_V << AHB_DMA_IN_CRC_CLEAR_CH2_S)
#define AHB_DMA_IN_CRC_CLEAR_CH2_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH2_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
* This register is used to store ch0 crc result

2
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -160,7 +160,7 @@
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_NUM_GROUPS_MAX 2
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM
// #define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM //TODO: IDF-6504
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups