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change(cache): swap cache hal arg 'type' and 'level'

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This commit is contained in:
Armando 2023-09-15 20:11:52 +08:00
parent 0a1503897c
commit ec27891af6
20 changed files with 70 additions and 69 deletions
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18
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
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@ -202,7 +202,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
Cache_Read_Disable(0);
Cache_Flush(0);
#else
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
//---------------Do mapping------------------------
@ -238,7 +238,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
cache_ll_invalidate_addr(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, MMU_BLOCK0_VADDR, actual_mapped_len);
#endif
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
mapped = true;
@ -255,7 +255,7 @@ void bootloader_munmap(const void *mapping)
Cache_Flush(0);
mmu_init(0);
#else
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
mmu_hal_unmap_all();
#endif
mapped = false;
@ -283,7 +283,7 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
Cache_Read_Disable(0);
Cache_Flush(0);
#else
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
@ -291,7 +291,7 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#else
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
return spi_to_esp_err(r);
@ -314,7 +314,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
Cache_Read_Disable(0);
Cache_Flush(0);
#else
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
//---------------Do mapping------------------------
@ -336,7 +336,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
cache_ll_invalidate_addr(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, MMU_BLOCK0_VADDR, actual_mapped_len);
#endif
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
}
map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));
@ -459,9 +459,9 @@ void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t fla
assert(false);
break;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
esp_rom_opiflash_cache_mode_config(flash_mode, &cache_rd);
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
#endif

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
View File

@ -127,10 +127,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
View File

@ -138,10 +138,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
View File

@ -103,10 +103,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
View File

@ -110,10 +110,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
View File

@ -97,10 +97,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
View File

@ -152,12 +152,12 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
// TODO: set mode
// TODO: set frequency
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
View File

@ -159,12 +159,12 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
// TODO: set mode
// TODO: set frequency
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)

4
components/bootloader_support/src/bootloader_utility.c
View File

@ -836,7 +836,7 @@ static void set_cache_and_start_app(
Cache_Read_Disable(0);
Cache_Flush(0);
#else
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
//reset MMU table first
mmu_hal_unmap_all();
@ -896,7 +896,7 @@ static void set_cache_and_start_app(
// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
Cache_Read_Enable(0);
#else
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
ESP_LOGD(TAG, "start: 0x%08"PRIx32, entry_addr);

4
components/esp_hw_support/dma/async_memcpy_gdma.c
View File

@ -163,10 +163,10 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi
atomic_init(&mcp_gdma->fsm, MCP_FSM_IDLE);
mcp_gdma->gdma_bus_id = gdma_bus_id;
uint32_t psram_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_EXT_MEM);
uint32_t psram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
uint32_t sram_cache_line_size = 0;
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_INT_MEM);
sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
#endif
// if the psram_trans_align is configured to zero, we should fall back to use the data cache line size

2
components/esp_hw_support/dma/gdma.c
View File

@ -358,7 +358,7 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t
ESP_RETURN_ON_FALSE((sram_alignment & (sram_alignment - 1)) == 0, ESP_ERR_INVALID_ARG,
TAG, "invalid sram alignment: %zu", sram_alignment);
uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_EXT_MEM);
uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
if (psram_alignment == 0) {
// fall back to use the same size of the psram data cache line size
psram_alignment = data_cache_line_size;

4
components/esp_hw_support/mspi_timing_tuning.c
View File

@ -474,7 +474,7 @@ void mspi_timing_change_speed_mode_cache_safe(bool switch_down)
* for preventing concurrent from MSPI to external memory
*/
#if SOC_CACHE_FREEZE_SUPPORTED
cache_hal_freeze(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_freeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
if (switch_down) {
@ -486,7 +486,7 @@ void mspi_timing_change_speed_mode_cache_safe(bool switch_down)
}
#if SOC_CACHE_FREEZE_SUPPORTED
cache_hal_unfreeze(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_unfreeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
}

4
components/esp_hw_support/sleep_modes.c
View File

@ -404,7 +404,7 @@ static int s_cache_suspend_cnt = 0;
static void IRAM_ATTR suspend_cache(void) {
s_cache_suspend_cnt++;
if (s_cache_suspend_cnt == 1) {
cache_hal_suspend(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
}
@ -413,7 +413,7 @@ static void IRAM_ATTR resume_cache(void) {
s_cache_suspend_cnt--;
assert(s_cache_suspend_cnt >= 0 && DRAM_STR("cache resume doesn't match suspend ops"));
if (s_cache_suspend_cnt == 0) {
cache_hal_resume(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
}

2
components/esp_lcd/src/esp_lcd_panel_io_i80.c
View File

@ -492,7 +492,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons
trans_desc->user_ctx = i80_device->user_ctx;
if (esp_ptr_external_ram(color)) {
uint32_t dcache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, CACHE_LL_LEVEL_EXT_MEM);
uint32_t dcache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
// flush frame buffer from cache to the physical PSRAM
// note the esp_cache_msync function will check the alignment of the address and size, make sure they're aligned to current cache line size
esp_cache_msync((void *)ALIGN_DOWN((intptr_t)color, dcache_line_size), ALIGN_UP(color_size, dcache_line_size), 0);

6
components/esp_mm/esp_cache.c
View File

@ -51,7 +51,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
if (flags & ESP_CACHE_MSYNC_FLAG_TYPE_INST) {
cache_type = CACHE_TYPE_INSTRUCTION;
}
uint32_t cache_line_size = cache_hal_get_cache_line_size(cache_type, cache_level);
uint32_t cache_line_size = cache_hal_get_cache_line_size(cache_level, cache_type);
if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
bool aligned_addr = (((uint32_t)addr % cache_line_size) == 0) && ((size % cache_line_size) == 0);
ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address: 0x%x, or the size: 0x%x is(are) not aligned with cache line size (0x%x)B", (uint32_t)addr, size, cache_line_size);
@ -111,10 +111,10 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr,
}
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, cache_level);
data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
#else
if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA, cache_level);
data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
} else {
data_cache_line_size = 4;
}

4
components/esp_system/port/cpu_start.c
View File

@ -341,7 +341,7 @@ void IRAM_ATTR do_multicore_settings(void)
cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);
#ifndef CONFIG_IDF_TARGET_ESP32
// 1. disable the cache before changing its settings.
cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) {
// 2. change cache settings. All cores must have the same settings.
@ -349,7 +349,7 @@ void IRAM_ATTR do_multicore_settings(void)
}
#ifndef CONFIG_IDF_TARGET_ESP32
// 3. enable the cache after changing its settings.
cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
}
#endif //#if !CONFIG_IDF_TARGET_ESP32P4

16
components/hal/cache_hal.c
View File

@ -167,7 +167,7 @@ bool s_get_cache_state(uint32_t cache_level, cache_type_t type)
}
#endif //#if CACHE_LL_ENABLE_DISABLE_STATE_SW
void cache_hal_disable(cache_type_t type, uint32_t cache_level)
void cache_hal_disable(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
@ -178,7 +178,7 @@ void cache_hal_disable(cache_type_t type, uint32_t cache_level)
#endif
}
void cache_hal_enable(cache_type_t type, uint32_t cache_level)
void cache_hal_enable(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
@ -193,7 +193,7 @@ void cache_hal_enable(cache_type_t type, uint32_t cache_level)
#endif
}
void cache_hal_suspend(cache_type_t type, uint32_t cache_level)
void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
@ -204,7 +204,7 @@ void cache_hal_suspend(cache_type_t type, uint32_t cache_level)
#endif
}
void cache_hal_resume(cache_type_t type, uint32_t cache_level)
void cache_hal_resume(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
@ -219,7 +219,7 @@ void cache_hal_resume(cache_type_t type, uint32_t cache_level)
#endif
}
bool cache_hal_is_cache_enabled(cache_type_t type, uint32_t cache_level)
bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
{
bool enabled = false;
#if CACHE_LL_ENABLE_DISABLE_STATE_SW
@ -269,14 +269,14 @@ bool cache_hal_writeback_addr(uint32_t vaddr, uint32_t size)
#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
#if SOC_CACHE_FREEZE_SUPPORTED
void cache_hal_freeze(cache_type_t type, uint32_t cache_level)
void cache_hal_freeze(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
cache_ll_freeze_cache(cache_level, type, CACHE_LL_ID_ALL);
}
void cache_hal_unfreeze(cache_type_t type, uint32_t cache_level)
void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
@ -284,7 +284,7 @@ void cache_hal_unfreeze(cache_type_t type, uint32_t cache_level)
}
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
uint32_t cache_hal_get_cache_line_size(cache_type_t type, uint32_t cache_level)
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));

8
components/hal/esp32/cache_hal_esp32.c
View File

@ -14,7 +14,7 @@ static uint32_t s_cache_status[2];
* There's a bug that Cache_Read_Disable requires a call to Cache_Flush
* before Cache_Read_Enable, even if cached data was not modified.
*/
void cache_hal_suspend(cache_type_t type, uint32_t cache_level)
void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
{
s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
cache_ll_l1_disable_cache(0);
@ -25,7 +25,7 @@ void cache_hal_suspend(cache_type_t type, uint32_t cache_level)
}
void cache_hal_resume(cache_type_t type, uint32_t cache_level)
void cache_hal_resume(uint32_t cache_level, cache_type_t type)
{
cache_ll_l1_enable_cache(0);
cache_ll_l1_enable_bus(0, s_cache_status[0]);
@ -36,7 +36,7 @@ void cache_hal_resume(cache_type_t type, uint32_t cache_level)
}
bool cache_hal_is_cache_enabled(cache_type_t type, uint32_t cache_level)
bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
{
bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL);
#if !CONFIG_FREERTOS_UNICORE
@ -53,7 +53,7 @@ bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint3
return cache_ll_vaddr_to_cache_level_id(vaddr_start, len, out_level, out_id);
}
uint32_t cache_hal_get_cache_line_size(cache_type_t type, uint32_t cache_level)
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
{
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
return 4;

33
components/hal/include/hal/cache_hal.h
View File

@ -29,20 +29,20 @@ void cache_hal_init(void);
*
* @note If the autoload feature is enabled, this API will return until the ICache autoload is disabled.
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_disable(cache_type_t type, uint32_t cache_level);
void cache_hal_disable(uint32_t cache_level, cache_type_t type);
/**
* @brief Enable Cache
*
* Enable the ICache or DCache or both, of a certain level or all levels.
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_enable(cache_type_t type, uint32_t cache_level);
void cache_hal_enable(uint32_t cache_level, cache_type_t type);
/**
* @brief Suspend Cache
@ -50,30 +50,30 @@ void cache_hal_enable(cache_type_t type, uint32_t cache_level);
* Suspend the ICache or DCache or both, of a certain level or all levels.
* This API suspends the CPU access to cache for a while, without invalidation.
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_suspend(cache_type_t type, uint32_t cache_level);
void cache_hal_suspend(uint32_t cache_level, cache_type_t type);
/**
* @brief Resume Cache
*
* Resume the ICache or DCache or both, of a certain level or all levels.
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_resume(cache_type_t type, uint32_t cache_level);
void cache_hal_resume(uint32_t cache_level, cache_type_t type);
/**
* @brief Check if corresponding cache is enabled or not
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*
* @return true: enabled; false: disabled
*/
bool cache_hal_is_cache_enabled(cache_type_t type, uint32_t cache_level);
bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type);
/**
* @brief Invalidate Cache supported addr
@ -107,30 +107,31 @@ bool cache_hal_writeback_addr(uint32_t vaddr, uint32_t size);
*
* Freeze cache, CPU access to cache will be suspended, until the cache is unfrozen.
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_freeze(cache_type_t type, uint32_t cache_level);
void cache_hal_freeze(uint32_t cache_level, cache_type_t type);
/**
* @brief Unfreeze cache
*
* Unfreeze cache, CPU access to cache will be restored
*
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
*/
void cache_hal_unfreeze(cache_type_t type, uint32_t cache_level);
void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type);
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
/**
* @brief Get cache line size, in bytes
*
* @param cache_level Level of the Cache(s)
* @param type see `cache_type_t`
* @param cache_level Level of the Cache(s) *
*
* @return cache line size, in bytes
*/
uint32_t cache_hal_get_cache_line_size(cache_type_t type, uint32_t cache_level);
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type);
/**
* @brief Get Cache level and the ID of the vaddr

6
components/spi_flash/cache_utils.c
View File

@ -360,17 +360,17 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
cache_hal_suspend(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
cache_hal_resume(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
bool IRAM_ATTR spi_flash_cache_enabled(void)
{
return cache_hal_is_cache_enabled(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
return cache_hal_is_cache_enabled(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
#if CONFIG_IDF_TARGET_ESP32S2