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fix(freertos/idf): Fix utility function performance
This commit optimizes the following utility functions to achieve higher overall system performance: xTaskGetCurrentTaskHandle(): - Made into stand alone function instead of wrapper call to "ForCore" variant - Replaced critical sections with disabling interrupts. Lack of lock contention improves performance. xTaskGetCurrentTaskHandleForCore(): - Removed unecessary critical sections xTaskGetSchedulerState(): - Replaced critical sections with disabling interrupts. Lack of lock contention improves performance.
This commit is contained in:
Darian Leung
parent
b13b9c1163
commit
ec1ba78b7c
@ -117,6 +117,10 @@ The following functions were modified to accommodate SMP behavior:
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- Updated logic to determine whether sleep is possible in SMP by checking the status of both cores.
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- `prvCheckTasksWaitingTermination()`
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- Updated logic so that we don't delete tasks on `xTasksWaitingTermination` which are still currently running on the other core.
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- `xTaskGetCurrentTaskHandle()`
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- In SMP, the function will now disables interrupts to ensure that the calling task does not switch cores while fetching the current core's TCB.
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- `xTaskGetSchedulerState()`
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- In SMP, the function now disables interrupts to ensure that the calling task does not switch cores while checking its own copy of `uxSchedulerSuspended`.
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- `prvAddCurrentTaskToDelayedList()`
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- Added extra check to see if current blocking task has already been deleted by the other core.
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@ -68,16 +68,19 @@
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/* Some code sections require extra critical sections when building for SMP
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* ( configNUMBER_OF_CORES > 1 ). */
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#if ( configNUMBER_OF_CORES > 1 )
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/* Macros that Enter/exit a critical section only when building for SMP */
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#define taskENTER_CRITICAL_SMP_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SMP_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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#define taskENTER_CRITICAL_ISR_SMP_ONLY( pxLock ) taskENTER_CRITICAL_ISR( pxLock )
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#define taskEXIT_CRITICAL_ISR_SMP_ONLY( pxLock ) taskEXIT_CRITICAL_ISR( pxLock )
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#define taskENTER_CRITICAL_SAFE_SMP_ONLY( pxLock ) prvTaskEnterCriticalSafeSMPOnly( pxLock )
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#define taskEXIT_CRITICAL_SAFE_SMP_ONLY( pxLock ) prvTaskExitCriticalSafeSMPOnly( pxLock )
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/* Macros that Enter/exit a critical section only when building for single-core */
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#define taskENTER_CRITICAL_SC_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SC_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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/* Macros that enter/exit a critical section only when building for SMP */
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#define taskENTER_CRITICAL_SMP_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SMP_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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#define taskENTER_CRITICAL_ISR_SMP_ONLY( pxLock ) taskENTER_CRITICAL_ISR( pxLock )
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#define taskEXIT_CRITICAL_ISR_SMP_ONLY( pxLock ) taskEXIT_CRITICAL_ISR( pxLock )
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#define taskENTER_CRITICAL_SAFE_SMP_ONLY( pxLock ) prvTaskEnterCriticalSafeSMPOnly( pxLock )
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#define taskEXIT_CRITICAL_SAFE_SMP_ONLY( pxLock ) prvTaskExitCriticalSafeSMPOnly( pxLock )
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/* Macros that enter/exit a critical section only when building for single-core */
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#define taskENTER_CRITICAL_SC_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SC_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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/* Macros that enable/disable interrupts only when building for SMP */
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#define taskDISABLE_INTERRUPTS_ISR_SMP_ONLY() portSET_INTERRUPT_MASK_FROM_ISR()
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#define taskEnable_INTERRUPTS_ISR_SMP_ONLY( uxStatus ) portCLEAR_INTERRUPT_MASK_FROM_ISR( uxStatus )
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static inline __attribute__( ( always_inline ) )
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void prvTaskEnterCriticalSafeSMPOnly( portMUX_TYPE * pxLock )
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@ -114,16 +117,20 @@
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}
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#else /* configNUMBER_OF_CORES > 1 */
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/* Macros that Enter/exit a critical section only when building for SMP */
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/* Macros that enter/exit a critical section only when building for SMP */
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#define taskENTER_CRITICAL_SMP_ONLY( pxLock )
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#define taskEXIT_CRITICAL_SMP_ONLY( pxLock )
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#define taskENTER_CRITICAL_ISR_SMP_ONLY( pxLock )
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#define taskEXIT_CRITICAL_ISR_SMP_ONLY( pxLock )
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#define taskENTER_CRITICAL_SAFE_SMP_ONLY( pxLock )
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#define taskEXIT_CRITICAL_SAFE_SMP_ONLY( pxLock )
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/* Macros that Enter/exit a critical section only when building for single-core */
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#define taskENTER_CRITICAL_SC_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SC_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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/* Macros that enter/exit a critical section only when building for single-core */
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#define taskENTER_CRITICAL_SC_ONLY( pxLock ) taskENTER_CRITICAL( pxLock )
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#define taskEXIT_CRITICAL_SC_ONLY( pxLock ) taskEXIT_CRITICAL( pxLock )
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/* Macros that enable/disable interrupts only when building for SMP */
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#define taskDISABLE_INTERRUPTS_ISR_SMP_ONLY() ( ( UBaseType_t ) 0 )
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#define taskEnable_INTERRUPTS_ISR_SMP_ONLY( uxStatus ) ( ( void ) uxStatus )
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#endif /* configNUMBER_OF_CORES > 1 */
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#if ( configUSE_PREEMPTION == 0 )
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@ -4832,7 +4839,24 @@ static void prvResetNextTaskUnblockTime( void )
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TaskHandle_t xTaskGetCurrentTaskHandle( void )
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{
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return xTaskGetCurrentTaskHandleForCore( portGET_CORE_ID() );
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TaskHandle_t xReturn;
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UBaseType_t uxSavedInterruptStatus;
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/* For SMP, we need to disable interrupts to ensure the caller does not
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* switch cores in between portGET_CORE_ID() and fetching the current
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* core's TCB. We use the ISR versions of interrupt macros as this
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* function could be called inside critical sections.
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*
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* For single-core a critical section is not required as this is not
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* called from an interrupt and the current TCB will always be the same
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* for any individual execution thread. */
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uxSavedInterruptStatus = taskDISABLE_INTERRUPTS_ISR_SMP_ONLY();
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{
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xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
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}
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taskEnable_INTERRUPTS_ISR_SMP_ONLY( uxSavedInterruptStatus );
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return xReturn;
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}
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#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
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@ -4843,10 +4867,18 @@ static void prvResetNextTaskUnblockTime( void )
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BaseType_t xTaskGetSchedulerState( void )
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{
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BaseType_t xReturn;
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UBaseType_t uxSavedInterruptStatus;
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/* For SMP, we need to take the kernel lock here as we are about to
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* access kernel data structures. */
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taskENTER_CRITICAL_SMP_ONLY( &xKernelLock );
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/* For SMP, we need to disable interrupts here to ensure we don't switch
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* cores midway. We forego taking the kernel lock here as a minor
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* optimization as it is not required.
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*
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* - xSchedulerRunning is only ever set by core 0 atomically
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* - Each core will only ever update its own copy of uxSchedulerSuspended.
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*
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* We use the ISR versions of interrupt macros as this function could be
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* called inside critical sections. */
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uxSavedInterruptStatus = taskDISABLE_INTERRUPTS_ISR_SMP_ONLY();
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{
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if( xSchedulerRunning == pdFALSE )
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{
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@ -4864,8 +4896,7 @@ static void prvResetNextTaskUnblockTime( void )
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}
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}
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}
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/* Release the previously taken kernel lock. */
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taskEXIT_CRITICAL_SMP_ONLY( &xKernelLock );
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taskEnable_INTERRUPTS_ISR_SMP_ONLY( uxSavedInterruptStatus );
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return xReturn;
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}
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@ -482,16 +482,10 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask )
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configASSERT( xCoreID < configNUMBER_OF_CORES );
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configASSERT( xCoreID != tskNO_AFFINITY );
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/* For SMP, we need to take the kernel lock here as we are about to
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* access kernel data structures. For single core, a critical section is
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* not required as this is not called from an interrupt and the current
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* TCB will always be the same for any individual execution thread. */
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taskENTER_CRITICAL_SMP_ONLY( &xKernelLock );
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{
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xReturn = pxCurrentTCBs[ xCoreID ];
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}
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/* Release the previously taken kernel lock. */
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taskEXIT_CRITICAL_SMP_ONLY( &xKernelLock );
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/* A critical section is not required as this function does not
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* guarantee that the TCB will still be valid when this function
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* returns. */
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xReturn = pxCurrentTCBs[ xCoreID ];
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}
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#endif /* CONFIG_FREERTOS_SMP */
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@ -861,7 +855,7 @@ uint8_t * pxTaskGetStackStart( TaskHandle_t xTask )
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struct _reent * __getreent( void )
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{
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/* No lock needed because if this changes, we won't be running anymore. */
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TCB_t * pxCurTask = xTaskGetCurrentTaskHandle();
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TCB_t * pxCurTask = ( TCB_t * ) xTaskGetCurrentTaskHandle();
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struct _reent * ret;
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if( pxCurTask == NULL )
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