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support esp32 eco revision 2 and 3

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This commit is contained in:
suda-morris 2019-09-18 13:25:50 +08:00
parent b1ee664367
commit eb4c8d9991
18 changed files with 240 additions and 109 deletions
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4
Kconfig
View File

@ -8,6 +8,10 @@ config IDF_CMAKE
bool
option env="IDF_CMAKE"
config IDF_FIRMWARE_CHIP_ID
hex
default 0x0000
menu "SDK tool configuration"
config TOOLPREFIX
string "Compiler toolchain path/prefix"

2
components/app_update/esp_ota_ops.c
View File

@ -146,7 +146,7 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
// must erase the partition before writing to it
assert(it->erased_size > 0 && "must erase the partition before writing to it");
if (it->wrote_size == 0 && it->partial_bytes == 0 && size > 0 && data_bytes[0] != ESP_IMAGE_HEADER_MAGIC) {
ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x", data_bytes[0]);
ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x)", data_bytes[0]);
return ESP_ERR_OTA_VALIDATE_FAILED;
}

12
components/bootloader_support/include/bootloader_common.h
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@ -14,6 +14,7 @@
#pragma once
#include "esp_flash_data_types.h"
#include "esp_image_format.h"
/// Type of hold a GPIO in low state
typedef enum {
@ -92,6 +93,17 @@ bool bootloader_common_label_search(const char *list, char *label);
*/
esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
/**
* @brief Check if the image (bootloader and application) has valid chip ID and revision
*
* @param img_hdr: image header
* @return
* - ESP_OK: image and chip are matched well
* - ESP_FAIL: image doesn't match to the chip
*/
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr);
/**
* @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
*/

7
components/bootloader_support/include/esp_efuse.h
View File

@ -91,6 +91,13 @@ esp_err_t esp_efuse_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_wor
*/
void esp_efuse_write_random_key(uint32_t blk_wdata0_reg);
/**
* @brief Returns chip version from efuse
*
* @return chip version
*/
uint8_t esp_efuse_get_chip_ver(void);
#ifdef __cplusplus
}
#endif

21
components/bootloader_support/include/esp_image_format.h
View File

@ -55,6 +55,19 @@ typedef enum {
#define ESP_IMAGE_HEADER_MAGIC 0xE9
/**
* @brief ESP chip ID
*
*/
typedef enum {
ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;
/** @cond */
_Static_assert(sizeof(esp_chip_id_t) == 2, "esp_chip_id_t should be 16 bit");
/* Main header of binary image */
typedef struct {
uint8_t magic;
@ -71,8 +84,12 @@ typedef struct {
uint8_t wp_pin;
/* Drive settings for the SPI flash pins (read by ROM bootloader) */
uint8_t spi_pin_drv[3];
/* Reserved bytes in ESP32 additional header space, currently unused */
uint8_t reserved[11];
/*!< Chip identification number */
esp_chip_id_t chip_id;
/*!< Minimum chip revision supported by image */
uint8_t min_chip_rev;
/*!< Reserved bytes in additional header space, currently unused */
uint8_t reserved[8];
/* If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum. Included in image length. This digest
* is separate to secure boot and only used for detecting corruption. For secure boot signed images, the signature
* is appended after this (and the simple hash is included in the signed data). */

21
components/bootloader_support/src/bootloader_common.c
View File

@ -32,6 +32,7 @@
#include "soc/spi_reg.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
#include "esp_efuse.h"
#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
@ -220,3 +221,23 @@ void bootloader_common_set_flash_cs_timing()
SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
}
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr)
{
esp_err_t err = ESP_OK;
esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
if (chip_id != img_hdr->chip_id) {
ESP_LOGE(TAG, "image has invalid chip ID, expected at least %d, found %d", chip_id, img_hdr->chip_id);
err = ESP_FAIL;
}
uint8_t revision = esp_efuse_get_chip_ver();
if (revision < img_hdr->min_chip_rev) {
ESP_LOGE(TAG, "image has invalid chip revision, expected at least %d, found %d", revision, img_hdr->min_chip_rev);
err = ESP_FAIL;
} else if (revision != img_hdr->min_chip_rev) {
ESP_LOGI(TAG, "This chip is revision %d but project was configured for minimum revision %d. "\
"Suggest setting project minimum revision to %d if safe to do so.",
revision, img_hdr->min_chip_rev, revision);
}
return err;
}

7
components/bootloader_support/src/bootloader_init.c
View File

@ -17,6 +17,7 @@
#include <sys/param.h>
#include "esp_attr.h"
#include "esp_efuse.h"
#include "esp_log.h"
#include "rom/cache.h"
@ -125,6 +126,12 @@ static esp_err_t bootloader_main()
ESP_LOGE(TAG, "failed to load bootloader header!");
return ESP_FAIL;
}
/* Check chip ID and minimum chip revision that supported by this image */
uint8_t revision = esp_efuse_get_chip_ver();
ESP_LOGI(TAG, "Chip Revision: %d", revision);
if (bootloader_common_check_chip_validity(&fhdr) != ESP_OK) {
return ESP_FAIL;
}
flash_gpio_configure(&fhdr);
#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
//Check if ESP32 is rated for a CPU frequency of 160MHz only

30
components/bootloader_support/src/efuse.c
View File

@ -15,6 +15,7 @@
#include "esp_log.h"
#include <string.h>
#include "bootloader_random.h"
#include "soc/apb_ctrl_reg.h"
#define EFUSE_CONF_WRITE 0x5A5A /* efuse_pgm_op_ena, force no rd/wr disable */
#define EFUSE_CONF_READ 0x5AA5 /* efuse_read_op_ena, release force */
@ -112,3 +113,32 @@ void esp_efuse_write_random_key(uint32_t blk_wdata0_reg)
bzero(buf, sizeof(buf));
bzero(raw, sizeof(raw));
}
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint8_t eco_bit0, eco_bit1, eco_bit2;
eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {
case 0:
chip_ver = 0;
break;
case 1:
chip_ver = 1;
break;
case 3:
chip_ver = 2;
break;
case 7:
chip_ver = 3;
break;
default:
chip_ver = 0;
break;
}
return chip_ver;
}

4
components/bootloader_support/src/esp_image_format.c
View File

@ -24,6 +24,7 @@
#include <bootloader_random.h>
#include <bootloader_sha.h>
#include "bootloader_util.h"
#include "bootloader_common.h"
/* Checking signatures as part of verifying images is necessary:
- Always if secure boot is enabled
@ -280,6 +281,9 @@ static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t
}
err = ESP_ERR_IMAGE_INVALID;
}
if (bootloader_common_check_chip_validity(image) != ESP_OK) {
err = ESP_ERR_IMAGE_INVALID;
}
if (!silent) {
if (image->spi_mode > ESP_IMAGE_SPI_MODE_SLOW_READ) {
ESP_LOGW(TAG, "image at 0x%x has invalid SPI mode %d", src_addr, image->spi_mode);

28
components/esp32/Kconfig
View File

@ -1,5 +1,33 @@
menu "ESP32-specific"
choice ESP32_REV_MIN
prompt "Minimum Supported ESP32 Revision"
default ESP32_REV_MIN_0
help
Minimum revision that ESP-IDF would support.
ESP-IDF performs different strategy on different esp32 revision.
config ESP32_REV_MIN_0
bool "Rev 0"
config ESP32_REV_MIN_1
bool "Rev 1"
config ESP32_REV_MIN_2
bool "Rev 2"
config ESP32_REV_MIN_3
bool "Rev 3"
endchoice
config ESP32_REV_MIN
int
default 0 if ESP32_REV_MIN_0
default 1 if ESP32_REV_MIN_1
default 2 if ESP32_REV_MIN_2
default 3 if ESP32_REV_MIN_3
config ESP32_DPORT_WORKAROUND
bool
default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2
choice ESP32_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP32_DEFAULT_CPU_FREQ_160

4
components/esp32/dport_access.c
View File

@ -249,7 +249,7 @@ void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address
*/
uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
{
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
return _DPORT_REG_READ(reg);
#else
uint32_t apb;
@ -295,7 +295,7 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
*/
uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
{
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
return _DPORT_REG_READ(reg);
#else
uint32_t apb;

2
components/esp32/include/esp_dport_access.h
View File

@ -33,7 +33,7 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
//only call in case of panic().
void esp_dport_access_int_abort(void);
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
#define DPORT_STALL_OTHER_CPU_START()
#define DPORT_STALL_OTHER_CPU_END()
#define DPORT_INTERRUPT_DISABLE()

23
components/esp32/system_api.c
View File

@ -16,6 +16,7 @@
#include "esp_system.h"
#include "esp_attr.h"
#include "esp_efuse.h"
#include "esp_wifi.h"
#include "esp_wifi_internal.h"
#include "esp_log.h"
@ -379,35 +380,27 @@ const char* esp_get_idf_version(void)
return IDF_VER;
}
static void get_chip_info_esp32(esp_chip_info_t* out_info)
void esp_chip_info(esp_chip_info_t* out_info)
{
uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {
out_info->revision = 1;
}
if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
out_info->revision = esp_efuse_get_chip_ver();
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
out_info->cores = 2;
} else {
out_info->cores = 1;
}
out_info->features = CHIP_FEATURE_WIFI_BGN;
if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
out_info->features |= CHIP_FEATURE_EMB_FLASH;
}
}
void esp_chip_info(esp_chip_info_t* out_info)
{
// Only ESP32 is supported now, in the future call one of the
// chip-specific functions based on sdkconfig choice
return get_chip_info_esp32(out_info);
}

4
components/esptool_py/Makefile.projbuild
View File

@ -31,6 +31,10 @@ endif
ESPTOOL_ELF2IMAGE_OPTIONS :=
ifdef CONFIG_ESP32_REV_MIN
ESPTOOL_ELF2IMAGE_OPTIONS += --min-rev $(CONFIG_ESP32_REV_MIN)
endif
ifdef CONFIG_SECURE_BOOT_ENABLED
ifndef CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION
ifndef IS_BOOTLOADER_BUILD

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit 9ad444a6e06e58833d5e6044c1d5f3eb3dd56023
Subproject commit 4f1e825d2d1ee33b896b3977905fb29ac6cc0794

4
components/esptool_py/project_include.cmake
View File

@ -16,6 +16,10 @@ set(ESPTOOLPY_ELF2IMAGE_FLASH_OPTIONS
--flash_size ${ESPFLASHSIZE}
)
if(CONFIG_ESP32_REV_MIN)
set(ESPTOOLPY_ELF2IMAGE_OPTIONS ${ESPTOOLPY_ELF2IMAGE_OPTIONS} --min-rev ${CONFIG_ESP32_REV_MIN})
endif()
if(CONFIG_ESPTOOLPY_FLASHSIZE_DETECT)
# Set ESPFLASHSIZE to 'detect' *after* elf2image options are generated,
# as elf2image can't have 'detect' as an option...

6
components/soc/esp32/include/soc/dport_access.h
View File

@ -73,7 +73,7 @@ extern "C" {
*/
static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
{
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
return _DPORT_REG_READ(reg);
#else
return esp_dport_access_reg_read(reg);
@ -106,7 +106,7 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
*/
static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg)
{
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
return _DPORT_REG_READ(reg);
#else
return esp_dport_access_sequence_reg_read(reg);
@ -166,7 +166,7 @@ static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg)
*/
static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t reg)
{
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
return _DPORT_REG_READ(reg);
#else
return esp_dport_access_reg_read(reg);

2
components/soc/esp32/include/soc/soc.h
View File

@ -147,7 +147,7 @@
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM )
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
#else
#define ASSERT_IF_DPORT_REG(_r, OP)