mirror of
https://github.com/espressif/esp-idf.git
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support esp32 eco revision 2 and 3
This commit is contained in:
suda-morris
parent
b1ee664367
commit
eb4c8d9991
10
Kconfig
10
Kconfig
@ -8,6 +8,10 @@ config IDF_CMAKE
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bool
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option env="IDF_CMAKE"
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config IDF_FIRMWARE_CHIP_ID
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hex
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default 0x0000
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menu "SDK tool configuration"
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config TOOLPREFIX
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string "Compiler toolchain path/prefix"
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@ -132,17 +136,17 @@ choice STACK_CHECK_MODE
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- In NORMAL mode (GCC flag: -fstack-protector) only functions that call alloca,
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and functions with buffers larger than 8 bytes are protected.
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- STRONG mode (GCC flag: -fstack-protector-strong) is like NORMAL, but includes
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additional functions to be protected -- those that have local array definitions,
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or have references to local frame addresses.
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- In OVERALL mode (GCC flag: -fstack-protector-all) all functions are protected.
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Modes have the following impact on code performance and coverage:
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- performance: NORMAL > STRONG > OVERALL
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- coverage: NORMAL < STRONG < OVERALL
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@ -38,9 +38,9 @@
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#include "esp_log.h"
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#define OTA_MAX(a,b) ((a) >= (b) ? (a) : (b))
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#define OTA_MIN(a,b) ((a) <= (b) ? (a) : (b))
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#define SUB_TYPE_ID(i) (i & 0x0F)
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#define OTA_MAX(a,b) ((a) >= (b) ? (a) : (b))
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#define OTA_MIN(a,b) ((a) <= (b) ? (a) : (b))
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#define SUB_TYPE_ID(i) (i & 0x0F)
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typedef struct ota_ops_entry_ {
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uint32_t handle;
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@ -146,7 +146,7 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
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// must erase the partition before writing to it
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assert(it->erased_size > 0 && "must erase the partition before writing to it");
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if (it->wrote_size == 0 && it->partial_bytes == 0 && size > 0 && data_bytes[0] != ESP_IMAGE_HEADER_MAGIC) {
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ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x", data_bytes[0]);
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ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x)", data_bytes[0]);
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return ESP_ERR_OTA_VALIDATE_FAILED;
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}
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@ -302,10 +302,10 @@ static esp_err_t esp_rewrite_ota_data(esp_partition_subtype_t subtype)
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//named data in first sector as s_ota_select[0], second sector data as s_ota_select[1]
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//e.g.
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//if s_ota_select[0].ota_seq == s_ota_select[1].ota_seq == 0xFFFFFFFF,means ota info partition is in init status
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//so it will boot factory application(if there is),if there's no factory application,it will boot ota[0] application
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//so it will boot factory application(if there is),if there's no factory application,it will boot ota[0] application
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//if s_ota_select[0].ota_seq != 0 and s_ota_select[1].ota_seq != 0,it will choose a max seq ,and get value of max_seq%max_ota_app_number
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//and boot a subtype (mask 0x0F) value is (max_seq - 1)%max_ota_app_number,so if want switch to run ota[x],can use next formulas.
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//for example, if s_ota_select[0].ota_seq = 4, s_ota_select[1].ota_seq = 5, and there are 8 ota application,
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//for example, if s_ota_select[0].ota_seq = 4, s_ota_select[1].ota_seq = 5, and there are 8 ota application,
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//current running is (5-1)%8 = 4,running ota[4],so if we want to switch to run ota[7],
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//we should add s_ota_select[0].ota_seq (is 4) to 4 ,(8-1)%8=7,then it will boot ota[7]
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//if A=(B - C)%D
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@ -14,6 +14,7 @@
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#pragma once
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#include "esp_flash_data_types.h"
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#include "esp_image_format.h"
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/// Type of hold a GPIO in low state
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typedef enum {
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@ -92,6 +93,17 @@ bool bootloader_common_label_search(const char *list, char *label);
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*/
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esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
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/**
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* @brief Check if the image (bootloader and application) has valid chip ID and revision
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*
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* @param img_hdr: image header
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* @return
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* - ESP_OK: image and chip are matched well
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* - ESP_FAIL: image doesn't match to the chip
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*/
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esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr);
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/**
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* @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
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*/
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@ -91,6 +91,13 @@ esp_err_t esp_efuse_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_wor
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*/
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void esp_efuse_write_random_key(uint32_t blk_wdata0_reg);
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/**
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* @brief Returns chip version from efuse
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*
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* @return chip version
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*/
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uint8_t esp_efuse_get_chip_ver(void);
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#ifdef __cplusplus
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}
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#endif
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@ -55,6 +55,19 @@ typedef enum {
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#define ESP_IMAGE_HEADER_MAGIC 0xE9
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/**
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* @brief ESP chip ID
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*
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*/
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typedef enum {
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ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */
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ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
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} __attribute__((packed)) esp_chip_id_t;
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/** @cond */
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_Static_assert(sizeof(esp_chip_id_t) == 2, "esp_chip_id_t should be 16 bit");
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/* Main header of binary image */
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typedef struct {
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uint8_t magic;
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@ -71,8 +84,12 @@ typedef struct {
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uint8_t wp_pin;
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/* Drive settings for the SPI flash pins (read by ROM bootloader) */
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uint8_t spi_pin_drv[3];
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/* Reserved bytes in ESP32 additional header space, currently unused */
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uint8_t reserved[11];
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/*!< Chip identification number */
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esp_chip_id_t chip_id;
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/*!< Minimum chip revision supported by image */
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uint8_t min_chip_rev;
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/*!< Reserved bytes in additional header space, currently unused */
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uint8_t reserved[8];
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/* If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum. Included in image length. This digest
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* is separate to secure boot and only used for detecting corruption. For secure boot signed images, the signature
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* is appended after this (and the simple hash is included in the signed data). */
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@ -32,6 +32,7 @@
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#include "soc/spi_reg.h"
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#include "esp_image_format.h"
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#include "bootloader_sha.h"
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#include "esp_efuse.h"
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#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
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@ -220,3 +221,23 @@ void bootloader_common_set_flash_cs_timing()
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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}
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esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr)
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{
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esp_err_t err = ESP_OK;
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esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
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if (chip_id != img_hdr->chip_id) {
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ESP_LOGE(TAG, "image has invalid chip ID, expected at least %d, found %d", chip_id, img_hdr->chip_id);
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err = ESP_FAIL;
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}
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uint8_t revision = esp_efuse_get_chip_ver();
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if (revision < img_hdr->min_chip_rev) {
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ESP_LOGE(TAG, "image has invalid chip revision, expected at least %d, found %d", revision, img_hdr->min_chip_rev);
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err = ESP_FAIL;
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} else if (revision != img_hdr->min_chip_rev) {
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ESP_LOGI(TAG, "This chip is revision %d but project was configured for minimum revision %d. "\
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"Suggest setting project minimum revision to %d if safe to do so.",
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revision, img_hdr->min_chip_rev, revision);
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}
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return err;
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}
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@ -17,6 +17,7 @@
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_efuse.h"
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#include "esp_log.h"
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#include "rom/cache.h"
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@ -125,6 +126,12 @@ static esp_err_t bootloader_main()
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ESP_LOGE(TAG, "failed to load bootloader header!");
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return ESP_FAIL;
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}
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/* Check chip ID and minimum chip revision that supported by this image */
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uint8_t revision = esp_efuse_get_chip_ver();
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ESP_LOGI(TAG, "Chip Revision: %d", revision);
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if (bootloader_common_check_chip_validity(&fhdr) != ESP_OK) {
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return ESP_FAIL;
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}
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flash_gpio_configure(&fhdr);
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#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
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//Check if ESP32 is rated for a CPU frequency of 160MHz only
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@ -15,6 +15,7 @@
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#include "esp_log.h"
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#include <string.h>
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#include "bootloader_random.h"
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#include "soc/apb_ctrl_reg.h"
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#define EFUSE_CONF_WRITE 0x5A5A /* efuse_pgm_op_ena, force no rd/wr disable */
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#define EFUSE_CONF_READ 0x5AA5 /* efuse_read_op_ena, release force */
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@ -112,3 +113,32 @@ void esp_efuse_write_random_key(uint32_t blk_wdata0_reg)
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bzero(buf, sizeof(buf));
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bzero(raw, sizeof(raw));
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}
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// Returns chip version from efuse
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uint8_t esp_efuse_get_chip_ver(void)
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{
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uint8_t eco_bit0, eco_bit1, eco_bit2;
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eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
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eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
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eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
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uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
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uint8_t chip_ver = 0;
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switch (combine_value) {
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case 0:
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chip_ver = 0;
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break;
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case 1:
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chip_ver = 1;
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break;
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case 3:
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chip_ver = 2;
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break;
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case 7:
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chip_ver = 3;
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break;
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default:
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chip_ver = 0;
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break;
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}
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return chip_ver;
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}
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@ -24,6 +24,7 @@
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#include <bootloader_random.h>
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#include <bootloader_sha.h>
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#include "bootloader_util.h"
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#include "bootloader_common.h"
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/* Checking signatures as part of verifying images is necessary:
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- Always if secure boot is enabled
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@ -280,6 +281,9 @@ static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t
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}
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err = ESP_ERR_IMAGE_INVALID;
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}
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if (bootloader_common_check_chip_validity(image) != ESP_OK) {
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err = ESP_ERR_IMAGE_INVALID;
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}
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if (!silent) {
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if (image->spi_mode > ESP_IMAGE_SPI_MODE_SLOW_READ) {
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ESP_LOGW(TAG, "image at 0x%x has invalid SPI mode %d", src_addr, image->spi_mode);
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@ -1,5 +1,33 @@
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menu "ESP32-specific"
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choice ESP32_REV_MIN
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prompt "Minimum Supported ESP32 Revision"
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default ESP32_REV_MIN_0
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help
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Minimum revision that ESP-IDF would support.
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ESP-IDF performs different strategy on different esp32 revision.
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config ESP32_REV_MIN_0
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bool "Rev 0"
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config ESP32_REV_MIN_1
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bool "Rev 1"
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config ESP32_REV_MIN_2
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bool "Rev 2"
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config ESP32_REV_MIN_3
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bool "Rev 3"
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endchoice
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config ESP32_REV_MIN
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int
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default 0 if ESP32_REV_MIN_0
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default 1 if ESP32_REV_MIN_1
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default 2 if ESP32_REV_MIN_2
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default 3 if ESP32_REV_MIN_3
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config ESP32_DPORT_WORKAROUND
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bool
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default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2
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choice ESP32_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP32_DEFAULT_CPU_FREQ_160
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@ -24,7 +52,7 @@ config SPIRAM_SUPPORT
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bool "Support for external, SPI-connected RAM"
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default "n"
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help
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This enables support for an external SPI RAM chip, connected in parallel with the
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This enables support for an external SPI RAM chip, connected in parallel with the
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main SPI flash chip.
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menu "SPI RAM config"
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@ -126,7 +154,7 @@ config SPIRAM_CACHE_WORKAROUND
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when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
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fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is vulnerable
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to this will not be emitted.
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This will also not use any bits of newlib that are located in ROM, opting for a version that is compiled
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with the workaround and located in flash instead.
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@ -147,9 +175,9 @@ config SPIRAM_BANKSWITCH_RESERVE
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default 8
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range 1 62
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help
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Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
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Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
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malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.
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Note that this reservation is only actually done if your program actually uses the himem API. Without
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any himem calls, the reservation is not done and the original amount of memory will be available
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to malloc/esp_heap_alloc_caps.
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@ -164,7 +192,7 @@ config SPIRAM_MALLOC_ALWAYSINTERNAL
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than this size in internal memory, while allocations larger than this will be done from external RAM.
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If allocation from the preferred region fails, an attempt is made to allocate from the non-preferred
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region instead, so malloc() will not suddenly fail when either internal or external memory is full.
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config WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
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bool "Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, allocate internal memory"
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depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
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@ -180,12 +208,12 @@ config SPIRAM_MALLOC_RESERVE_INTERNAL
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help
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Because the external/internal RAM allocation strategy is not always perfect, it sometimes may happen
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that the internal memory is entirely filled up. This causes allocations that are specifically done in
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internal memory, for example the stack for new tasks or memory to service DMA or have memory that's
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also available when SPI cache is down, to fail. This option reserves a pool specifically for requests
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internal memory, for example the stack for new tasks or memory to service DMA or have memory that's
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also available when SPI cache is down, to fail. This option reserves a pool specifically for requests
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like that; the memory in this pool is not given out when a normal malloc() is called.
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Set this to 0 to disable this feature.
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Note that because FreeRTOS stacks are forced to internal memory, they will also use this memory pool;
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be sure to keep this in mind when adjusting this value.
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@ -212,7 +240,7 @@ config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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help
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If enabled the option,and add EXT_RAM_ATTR defined your variable,then your variable will be placed
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in PSRAM instead of internal memory, and placed most of variables of lwip,net802.11,pp,bluedroid library
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to external memory defaultly.
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to external memory defaultly.
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choice SPIRAM_OCCUPY_SPI_HOST
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prompt "SPI host to use for 32MBit PSRAM"
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@ -348,8 +376,8 @@ choice ESP32_COREDUMP_TO_FLASH_OR_UART
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help
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Select place to store core dump: flash, uart or none (to disable core dumps generation).
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If core dump is configured to be stored in flash and custom partition table is used add
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corresponding entry to your CSV. For examples, please see predefined partition table CSV descriptions
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If core dump is configured to be stored in flash and custom partition table is used add
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corresponding entry to your CSV. For examples, please see predefined partition table CSV descriptions
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in the components/partition_table directory.
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config ESP32_ENABLE_COREDUMP_TO_FLASH
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@ -388,18 +416,18 @@ choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
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default FOUR_UNIVERSAL_MAC_ADDRESS
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help
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Configure the number of universally administered (by IEEE) MAC addresses.
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During initialisation, MAC addresses for each network interface are generated or derived from a
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During initialisation, MAC addresses for each network interface are generated or derived from a
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single base MAC address.
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If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
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Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
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If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
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Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
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sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
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If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
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receive a universally administered MAC address. These are generated sequentially by adding 0
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and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
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receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
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If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
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receive a universally administered MAC address. These are generated sequentially by adding 0
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and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
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receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
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addresses, respectively.
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When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
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a custom universal MAC address range, the correct setting will depend on the allocation of MAC
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When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
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a custom universal MAC address range, the correct setting will depend on the allocation of MAC
|
||||
addresses in this range (either 2 or 4 per device.)
|
||||
|
||||
config TWO_UNIVERSAL_MAC_ADDRESS
|
||||
@ -409,7 +437,7 @@ config FOUR_UNIVERSAL_MAC_ADDRESS
|
||||
endchoice
|
||||
|
||||
config NUMBER_OF_UNIVERSAL_MAC_ADDRESS
|
||||
int
|
||||
int
|
||||
default 2 if TWO_UNIVERSAL_MAC_ADDRESS
|
||||
default 4 if FOUR_UNIVERSAL_MAC_ADDRESS
|
||||
|
||||
@ -457,10 +485,10 @@ config TIMER_TASK_STACK_SIZE
|
||||
to dispatch callbacks of timers created using ets_timer and esp_timer
|
||||
APIs. If you are seing stack overflow errors in timer task, increase
|
||||
this value.
|
||||
|
||||
|
||||
Note that this is not the same as FreeRTOS timer task. To configure
|
||||
FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
|
||||
in "FreeRTOS" menu.
|
||||
in "FreeRTOS" menu.
|
||||
|
||||
choice NEWLIB_STDOUT_LINE_ENDING
|
||||
prompt "Line ending for UART output"
|
||||
@ -469,15 +497,15 @@ choice NEWLIB_STDOUT_LINE_ENDING
|
||||
This option allows configuring the desired line endings sent to UART
|
||||
when a newline ('\n', LF) appears on stdout.
|
||||
Three options are possible:
|
||||
|
||||
|
||||
CRLF: whenever LF is encountered, prepend it with CR
|
||||
|
||||
|
||||
LF: no modification is applied, stdout is sent as is
|
||||
|
||||
|
||||
CR: each occurence of LF is replaced with CR
|
||||
|
||||
|
||||
This option doesn't affect behavior of the UART driver (drivers/uart.h).
|
||||
|
||||
|
||||
config NEWLIB_STDOUT_LINE_ENDING_CRLF
|
||||
bool "CRLF"
|
||||
config NEWLIB_STDOUT_LINE_ENDING_LF
|
||||
@ -493,15 +521,15 @@ choice NEWLIB_STDIN_LINE_ENDING
|
||||
This option allows configuring which input sequence on UART produces
|
||||
a newline ('\n', LF) on stdin.
|
||||
Three options are possible:
|
||||
|
||||
|
||||
CRLF: CRLF is converted to LF
|
||||
|
||||
|
||||
LF: no modification is applied, input is sent to stdin as is
|
||||
|
||||
|
||||
CR: each occurence of CR is replaced with LF
|
||||
|
||||
|
||||
This option doesn't affect behavior of the UART driver (drivers/uart.h).
|
||||
|
||||
|
||||
config NEWLIB_STDIN_LINE_ENDING_CRLF
|
||||
bool "CRLF"
|
||||
config NEWLIB_STDIN_LINE_ENDING_LF
|
||||
@ -536,7 +564,7 @@ choice CONSOLE_UART
|
||||
default CONSOLE_UART_DEFAULT
|
||||
help
|
||||
Select whether to use UART for console output (through stdout and stderr).
|
||||
|
||||
|
||||
- Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
|
||||
- If "Custom" is selected, UART0 or UART1 can be chosen,
|
||||
and any pins can be selected.
|
||||
@ -650,10 +678,10 @@ config ESP32_DEBUG_OCDAWARE
|
||||
|
||||
config ESP32_DEBUG_STUBS_ENABLE
|
||||
bool "OpenOCD debug stubs"
|
||||
default OPTIMIZATION_LEVEL_DEBUG
|
||||
default OPTIMIZATION_LEVEL_DEBUG
|
||||
depends on !ESP32_TRAX
|
||||
help
|
||||
Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
|
||||
Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
|
||||
e.g. GCOV data dump.
|
||||
|
||||
config INT_WDT
|
||||
@ -687,7 +715,7 @@ config TASK_WDT
|
||||
help
|
||||
The Task Watchdog Timer can be used to make sure individual tasks are still
|
||||
running. Enabling this option will cause the Task Watchdog Timer to be
|
||||
initialized automatically at startup. The Task Watchdog timer can be
|
||||
initialized automatically at startup. The Task Watchdog timer can be
|
||||
initialized after startup as well (see Task Watchdog Timer API Reference)
|
||||
|
||||
config TASK_WDT_PANIC
|
||||
@ -801,7 +829,7 @@ choice ESP32_TIME_SYSCALL
|
||||
continue in deep sleep. Time will be reported at 1 microsecond
|
||||
resolution. This is the default, and the recommended option.
|
||||
- If only high-resolution timer is used, gettimeofday will
|
||||
provide time at microsecond resolution.
|
||||
provide time at microsecond resolution.
|
||||
Time will not be preserved when going into deep sleep mode.
|
||||
- If only RTC timer is used, timekeeping will continue in
|
||||
deep sleep, but time will be measured at 6.(6) microsecond
|
||||
@ -827,7 +855,7 @@ choice ESP32_RTC_CLOCK_SOURCE
|
||||
default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
|
||||
- "Internal 150kHz oscillator" option provides lowest deep sleep current
|
||||
consumption, and does not require extra external components. However
|
||||
frequency stability with respect to temperature is poor, so time may
|
||||
@ -843,7 +871,7 @@ choice ESP32_RTC_CLOCK_SOURCE
|
||||
ground. 32K_XN pin can not be used as a GPIO in this case.
|
||||
- "Internal 8.5MHz oscillator divided by 256" option results in higher
|
||||
deep sleep current (by 5uA) but has better frequency stability than
|
||||
the internal 150kHz oscillator. It does not require external components.
|
||||
the internal 150kHz oscillator. It does not require external components.
|
||||
|
||||
config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
|
||||
bool "Internal 150kHz RC oscillator"
|
||||
@ -881,7 +909,7 @@ config ESP32_RTC_CLK_CAL_CYCLES
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
@ -896,15 +924,15 @@ config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES
|
||||
default 5
|
||||
range 0 32768
|
||||
help
|
||||
To reduce the startup time of an external RTC crystal,
|
||||
we bootstrap it with a 32kHz square wave for a fixed number of cycles.
|
||||
Setting 0 will disable bootstrapping (if disabled, the crystal may take
|
||||
To reduce the startup time of an external RTC crystal,
|
||||
we bootstrap it with a 32kHz square wave for a fixed number of cycles.
|
||||
Setting 0 will disable bootstrapping (if disabled, the crystal may take
|
||||
longer to start up or fail to oscillate under some conditions).
|
||||
|
||||
If this value is too high, a faulty crystal may initially start and then fail.
|
||||
|
||||
If this value is too high, a faulty crystal may initially start and then fail.
|
||||
If this value is too low, an otherwise good crystal may not start.
|
||||
|
||||
To accurately determine if the crystal has started,
|
||||
|
||||
To accurately determine if the crystal has started,
|
||||
set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
|
||||
|
||||
config ESP32_DEEP_SLEEP_WAKEUP_DELAY
|
||||
@ -918,9 +946,9 @@ config ESP32_DEEP_SLEEP_WAKEUP_DELAY
|
||||
time to pass between power on and first read operation. By default,
|
||||
without any extra delay, this time is approximately 900us, although
|
||||
some flash chip types need more than that.
|
||||
|
||||
|
||||
By default extra delay is set to 2000us. When optimizing startup time
|
||||
for applications which require it, this value may be reduced.
|
||||
for applications which require it, this value may be reduced.
|
||||
|
||||
If you are seeing "flash read err, 1000" message printed to the
|
||||
console after deep sleep reset, try increasing this value.
|
||||
@ -1019,7 +1047,7 @@ config ESP32_RTCDATA_IN_FAST_MEM
|
||||
help
|
||||
This option allows to place .rtc_data and .rtc_rodata sections into
|
||||
RTC fast memory segment to free the slow memory region for ULP programs.
|
||||
This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
|
||||
This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
|
||||
can be accessed only by PRO_CPU core.
|
||||
|
||||
config ESP32_DPORT_DIS_INTERRUPT_LVL
|
||||
@ -1085,8 +1113,8 @@ config ESP32_WIFI_STATIC_RX_BUFFER_NUM
|
||||
until esp_wifi_deinit is called.
|
||||
|
||||
WiFi hardware use these buffers to receive all 802.11 frames.
|
||||
A higher number may allow higher throughput but increases memory use. If ESP32_WIFI_AMPDU_RX_ENABLED
|
||||
is enabled, this value is recommended to set equal or bigger than ESP32_WIFI_RX_BA_WIN in order to
|
||||
A higher number may allow higher throughput but increases memory use. If ESP32_WIFI_AMPDU_RX_ENABLED
|
||||
is enabled, this value is recommended to set equal or bigger than ESP32_WIFI_RX_BA_WIN in order to
|
||||
achieve better throughput and compatibility with both stations and APs.
|
||||
|
||||
config ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM
|
||||
@ -1170,8 +1198,8 @@ config ESP32_WIFI_CSI_ENABLED
|
||||
bool "WiFi CSI(Channel State Information)"
|
||||
default n
|
||||
help
|
||||
Select this option to enable CSI(Channel State Information) feature. CSI takes about
|
||||
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM KB of RAM. If CSI is not used, it is better to disable
|
||||
Select this option to enable CSI(Channel State Information) feature. CSI takes about
|
||||
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM KB of RAM. If CSI is not used, it is better to disable
|
||||
this feature in order to save memory.
|
||||
|
||||
config ESP32_WIFI_AMPDU_TX_ENABLED
|
||||
@ -1188,7 +1216,7 @@ config ESP32_WIFI_TX_BA_WIN
|
||||
default 6
|
||||
help
|
||||
Set the size of WiFi Block Ack TX window. Generally a bigger value means higher throughput but
|
||||
more memory. Most of time we should NOT change the default value unless special reason, e.g.
|
||||
more memory. Most of time we should NOT change the default value unless special reason, e.g.
|
||||
test the maximum UDP TX throughput with iperf etc. For iperf test in shieldbox, the recommended
|
||||
value is 9~12.
|
||||
|
||||
@ -1206,10 +1234,10 @@ config ESP32_WIFI_RX_BA_WIN
|
||||
default 6 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
|
||||
default 16 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
|
||||
help
|
||||
Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better
|
||||
Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better
|
||||
compatibility but more memory. Most of time we should NOT change the default value unless special reason, e.g.
|
||||
test the maximum UDP RX throughput with iperf etc. For iperf test in shieldbox, the recommended
|
||||
value is 9~12. If PSRAM is used and WiFi memory is prefered to allocat in PSRAM first, the default
|
||||
value is 9~12. If PSRAM is used and WiFi memory is prefered to allocat in PSRAM first, the default
|
||||
and minimum value should be 16 to achieve better throughput and compatibility with both stations and APs.
|
||||
|
||||
config ESP32_WIFI_NVS_ENABLED
|
||||
@ -1239,15 +1267,15 @@ config ESP32_WIFI_SOFTAP_BEACON_MAX_LEN
|
||||
ESP-MESH utilizes beacon frames to detect and resolve root node conflicts (see documentation). However the default
|
||||
length of a beacon frame can simultaneously hold only five root node identifier structures, meaning that a root node
|
||||
conflict of up to five nodes can be detected at one time. In the occurence of more root nodes conflict involving more
|
||||
than five root nodes, the conflict resolution process will detect five of the root nodes, resolve the conflict, and
|
||||
than five root nodes, the conflict resolution process will detect five of the root nodes, resolve the conflict, and
|
||||
re-detect more root nodes. This process will repeat until all root node conflicts are resolved. However this process
|
||||
can generally take a very long time.
|
||||
|
||||
|
||||
To counter this situation, the beacon frame length can be increased such that more root nodes can be detected simultaneously.
|
||||
Each additional root node will require 36 bytes and should be added ontop of the default beacon frame length of
|
||||
752 bytes. For example, if you want to detect 10 root nodes simultaneously, you need to set the beacon frame length as
|
||||
752 bytes. For example, if you want to detect 10 root nodes simultaneously, you need to set the beacon frame length as
|
||||
932 (752+36*5).
|
||||
|
||||
|
||||
Setting a longer beacon length also assists with debugging as the conflicting root nodes can be identified more quickly.
|
||||
|
||||
config ESP32_WIFI_IRAM_OPT
|
||||
@ -1274,7 +1302,7 @@ config ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
|
||||
help
|
||||
If this option is enabled, NVS will be initialized and calibration data will be loaded from there.
|
||||
PHY calibration will be skipped on deep sleep wakeup. If calibration data is not found, full calibration
|
||||
will be performed and stored in NVS. Normally, only partial calibration will be performed.
|
||||
will be performed and stored in NVS. Normally, only partial calibration will be performed.
|
||||
If this option is disabled, full calibration will be performed.
|
||||
|
||||
If it's easy that your board calibrate bad data, choose 'n'.
|
||||
@ -1298,7 +1326,7 @@ config ESP32_PHY_INIT_DATA_IN_PARTITION
|
||||
into the application binary.
|
||||
|
||||
If unsure, choose 'n'.
|
||||
|
||||
|
||||
config ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
int "Max WiFi TX power (dBm)"
|
||||
range 0 20
|
||||
@ -1323,7 +1351,7 @@ config PM_ENABLE
|
||||
This option has run-time overhead (increased interrupt latency,
|
||||
longer time to enter idle state), and it also reduces accuracy of
|
||||
RTOS ticks and timers used for timekeeping.
|
||||
Enable this option if application uses power management APIs.
|
||||
Enable this option if application uses power management APIs.
|
||||
|
||||
config PM_DFS_INIT_AUTO
|
||||
bool "Enable dynamic frequency scaling (DFS) at startup"
|
||||
@ -1360,7 +1388,7 @@ config PM_PROFILING
|
||||
This feature can be used to analyze which locks are preventing the chip
|
||||
from going into a lower power state, and see what time the chip spends
|
||||
in each power saving mode. This feature does incur some run-time
|
||||
overhead, so should typically be disabled in production builds.
|
||||
overhead, so should typically be disabled in production builds.
|
||||
|
||||
config PM_TRACE
|
||||
bool "Enable debug tracing of PM using GPIOs"
|
||||
@ -1373,6 +1401,6 @@ config PM_TRACE
|
||||
This feature is intended to be used when analyzing/debugging behavior
|
||||
of power management implementation, and should be kept disabled in
|
||||
applications.
|
||||
|
||||
|
||||
|
||||
endmenu # "Power Management"
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
* DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
|
||||
* This function will be initialize after FreeRTOS startup.
|
||||
* When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
|
||||
* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
|
||||
* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
@ -116,7 +116,7 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
|
||||
{
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
int cpu_id = xPortGetCoreID();
|
||||
|
||||
|
||||
if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
|
||||
|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
|
||||
return;
|
||||
@ -249,7 +249,7 @@ void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address
|
||||
*/
|
||||
uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
uint32_t apb;
|
||||
@ -295,7 +295,7 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
|
||||
*/
|
||||
uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
uint32_t apb;
|
||||
|
||||
@ -33,7 +33,7 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
|
||||
//only call in case of panic().
|
||||
void esp_dport_access_int_abort(void);
|
||||
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
#define DPORT_STALL_OTHER_CPU_START()
|
||||
#define DPORT_STALL_OTHER_CPU_END()
|
||||
#define DPORT_INTERRUPT_DISABLE()
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
|
||||
#include "esp_system.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_wifi.h"
|
||||
#include "esp_wifi_internal.h"
|
||||
#include "esp_log.h"
|
||||
@ -229,7 +230,7 @@ esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type)
|
||||
ESP_LOGW(TAG, "incorrect mac type");
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@ -320,10 +321,10 @@ void IRAM_ATTR esp_restart_noos()
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
||||
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
|
||||
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
|
||||
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
||||
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
||||
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
|
||||
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
|
||||
|
||||
@ -379,35 +380,27 @@ const char* esp_get_idf_version(void)
|
||||
return IDF_VER;
|
||||
}
|
||||
|
||||
static void get_chip_info_esp32(esp_chip_info_t* out_info)
|
||||
void esp_chip_info(esp_chip_info_t* out_info)
|
||||
{
|
||||
uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
|
||||
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
|
||||
memset(out_info, 0, sizeof(*out_info));
|
||||
|
||||
|
||||
out_info->model = CHIP_ESP32;
|
||||
if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {
|
||||
out_info->revision = 1;
|
||||
}
|
||||
if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
|
||||
out_info->revision = esp_efuse_get_chip_ver();
|
||||
|
||||
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
|
||||
out_info->cores = 2;
|
||||
} else {
|
||||
out_info->cores = 1;
|
||||
}
|
||||
out_info->features = CHIP_FEATURE_WIFI_BGN;
|
||||
if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
|
||||
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
|
||||
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
|
||||
}
|
||||
int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
|
||||
int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
|
||||
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
|
||||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
|
||||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
|
||||
out_info->features |= CHIP_FEATURE_EMB_FLASH;
|
||||
}
|
||||
}
|
||||
|
||||
void esp_chip_info(esp_chip_info_t* out_info)
|
||||
{
|
||||
// Only ESP32 is supported now, in the future call one of the
|
||||
// chip-specific functions based on sdkconfig choice
|
||||
return get_chip_info_esp32(out_info);
|
||||
}
|
||||
|
||||
@ -31,6 +31,10 @@ endif
|
||||
|
||||
ESPTOOL_ELF2IMAGE_OPTIONS :=
|
||||
|
||||
ifdef CONFIG_ESP32_REV_MIN
|
||||
ESPTOOL_ELF2IMAGE_OPTIONS += --min-rev $(CONFIG_ESP32_REV_MIN)
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SECURE_BOOT_ENABLED
|
||||
ifndef CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION
|
||||
ifndef IS_BOOTLOADER_BUILD
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit 9ad444a6e06e58833d5e6044c1d5f3eb3dd56023
|
||||
Subproject commit 4f1e825d2d1ee33b896b3977905fb29ac6cc0794
|
||||
@ -16,6 +16,10 @@ set(ESPTOOLPY_ELF2IMAGE_FLASH_OPTIONS
|
||||
--flash_size ${ESPFLASHSIZE}
|
||||
)
|
||||
|
||||
if(CONFIG_ESP32_REV_MIN)
|
||||
set(ESPTOOLPY_ELF2IMAGE_OPTIONS ${ESPTOOLPY_ELF2IMAGE_OPTIONS} --min-rev ${CONFIG_ESP32_REV_MIN})
|
||||
endif()
|
||||
|
||||
if(CONFIG_ESPTOOLPY_FLASHSIZE_DETECT)
|
||||
# Set ESPFLASHSIZE to 'detect' *after* elf2image options are generated,
|
||||
# as elf2image can't have 'detect' as an option...
|
||||
|
||||
@ -48,7 +48,7 @@ extern "C" {
|
||||
// After completing read operations, use DPORT_STALL_OTHER_CPU_END().
|
||||
// This method uses stall other CPU while reading DPORT registers.
|
||||
// Useful for compatibility, as well as for large consecutive readings.
|
||||
// This method is slower, but must be used if ROM functions or
|
||||
// This method is slower, but must be used if ROM functions or
|
||||
// other code is called which accesses DPORT without any other workaround.
|
||||
// *) The pre-readable APB register before reading the DPORT register
|
||||
// helps synchronize the operation of the two CPUs,
|
||||
@ -73,7 +73,7 @@ extern "C" {
|
||||
*/
|
||||
static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
return esp_dport_access_reg_read(reg);
|
||||
@ -106,7 +106,7 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
|
||||
*/
|
||||
static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
return esp_dport_access_sequence_reg_read(reg);
|
||||
@ -166,7 +166,7 @@ static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg)
|
||||
*/
|
||||
static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t reg)
|
||||
{
|
||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
|
||||
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
||||
return _DPORT_REG_READ(reg);
|
||||
#else
|
||||
return esp_dport_access_reg_read(reg);
|
||||
|
||||
@ -147,7 +147,7 @@
|
||||
|
||||
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
|
||||
|
||||
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
|
||||
#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM )
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
|
||||
#else
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user