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change(adc): refactor DMA memory allocation
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parent
b4b1906d2c
commit
ea9630d977
@ -37,7 +37,6 @@
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#include "adc_continuous_internal.h"
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#include "adc_continuous_internal.h"
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#include "esp_private/adc_dma.h"
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#include "esp_private/adc_dma.h"
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#include "adc_dma_internal.h"
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#include "adc_dma_internal.h"
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#include "esp_dma_utils.h"
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#include "esp_cache.h"
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#include "esp_cache.h"
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#include "esp_private/esp_cache_private.h"
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#include "esp_private/esp_cache_private.h"
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@ -192,11 +191,7 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi
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}
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}
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//malloc internal buffer used by DMA
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//malloc internal buffer used by DMA
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esp_dma_mem_info_t dma_mem_info = {
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adc_ctx->rx_dma_buf = heap_caps_calloc(INTERNAL_BUF_NUM, hdl_config->conv_frame_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
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.extra_heap_caps = (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA),
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.dma_alignment_bytes = 4,
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};
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esp_dma_capable_calloc(1, hdl_config->conv_frame_size * INTERNAL_BUF_NUM, &dma_mem_info, (void **)&adc_ctx->rx_dma_buf, NULL);
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if (!adc_ctx->rx_dma_buf) {
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if (!adc_ctx->rx_dma_buf) {
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ret = ESP_ERR_NO_MEM;
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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goto cleanup;
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@ -205,7 +200,7 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi
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//malloc dma descriptor
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//malloc dma descriptor
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uint32_t dma_desc_num_per_frame = (hdl_config->conv_frame_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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uint32_t dma_desc_num_per_frame = (hdl_config->conv_frame_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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uint32_t dma_desc_max_num = dma_desc_num_per_frame * INTERNAL_BUF_NUM;
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uint32_t dma_desc_max_num = dma_desc_num_per_frame * INTERNAL_BUF_NUM;
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esp_dma_capable_calloc(1, (sizeof(dma_descriptor_t)) * dma_desc_max_num, &dma_mem_info, (void **)&adc_ctx->hal.rx_desc, &adc_ctx->adc_desc_size);
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adc_ctx->hal.rx_desc = heap_caps_aligned_calloc(ADC_DMA_DESC_ALIGN, dma_desc_max_num, sizeof(dma_descriptor_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
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if (!adc_ctx->hal.rx_desc) {
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if (!adc_ctx->hal.rx_desc) {
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ret = ESP_ERR_NO_MEM;
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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goto cleanup;
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@ -550,12 +545,12 @@ esp_err_t adc_continuous_flush_pool(adc_continuous_handle_t handle)
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return ESP_OK;
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return ESP_OK;
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}
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}
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esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t * const unit_id, adc_channel_t * const channel)
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esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t *const unit_id, adc_channel_t *const channel)
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{
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{
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return adc_io_to_channel(io_num, unit_id, channel);
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return adc_io_to_channel(io_num, unit_id, channel);
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}
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}
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esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * const io_num)
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esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int *const io_num)
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{
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{
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return adc_channel_to_io(unit_id, channel, io_num);
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return adc_channel_to_io(unit_id, channel, io_num);
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}
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}
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@ -32,6 +32,8 @@ typedef struct {
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intr_handle_t dma_intr_hdl;
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intr_handle_t dma_intr_hdl;
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} adc_dma_t;
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} adc_dma_t;
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#define ADC_DMA_DESC_ALIGN 4
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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